]> cvs.zerfleddert.de Git - proxmark3-svn/blame_incremental - fpga/fpga.ucf
Limit hexsamples to just the amount of requested samples
[proxmark3-svn] / fpga / fpga.ucf
... / ...
CommitLineData
1# See the schematic for the pin assignment.\r
2\r
3NET "adc_d<0>" LOC = "P62" ; \r
4NET "adc_d<1>" LOC = "P60" ; \r
5NET "adc_d<2>" LOC = "P58" ; \r
6NET "adc_d<3>" LOC = "P57" ; \r
7NET "adc_d<4>" LOC = "P56" ; \r
8NET "adc_d<5>" LOC = "P55" ; \r
9NET "adc_d<6>" LOC = "P54" ; \r
10NET "adc_d<7>" LOC = "P53" ; \r
11#NET "cross_hi" LOC = "P88" ; \r
12#NET "miso" LOC = "P40" ; \r
13#PACE: Start of Constraints generated by PACE\r
14\r
15#PACE: Start of PACE I/O Pin Assignments\r
16NET "adc_clk" LOC = "P46" ; \r
17NET "adc_noe" LOC = "P47" ; \r
18NET "ck_1356meg" LOC = "P91" ; \r
19NET "ck_1356megb" LOC = "P93" ; \r
20NET "cross_lo" LOC = "P87" ; \r
21NET "dbg" LOC = "P22" ; \r
22NET "mosi" LOC = "P43" ; \r
23NET "ncs" LOC = "P44" ; \r
24NET "pck0" LOC = "P36" ; \r
25NET "pwr_hi" LOC = "P80" ; \r
26NET "pwr_lo" LOC = "P81" ; \r
27NET "pwr_oe1" LOC = "P82" ; \r
28NET "pwr_oe2" LOC = "P83" ; \r
29NET "pwr_oe3" LOC = "P84" ; \r
30NET "pwr_oe4" LOC = "P86" ; \r
31NET "spck" LOC = "P39" ; \r
32NET "ssp_clk" LOC = "P71" ; \r
33NET "ssp_din" LOC = "P32" ; \r
34NET "ssp_dout" LOC = "P34" ; \r
35NET "ssp_frame" LOC = "P31" ; \r
36\r
37#PACE: Start of PACE Area Constraints\r
38\r
39#PACE: Start of PACE Prohibit Constraints\r
40\r
41#PACE: End of Constraints generated by PACE\r
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