| 1 | //----------------------------------------------------------------------------- |
| 2 | // General-purpose miscellany. |
| 3 | // |
| 4 | // Jonathan Westhues, April 2006. |
| 5 | //----------------------------------------------------------------------------- |
| 6 | |
| 7 | module mux8(sel, y, x0, x1, x2, x3, x4, x5, x6, x7); |
| 8 | input [2:0] sel; |
| 9 | input x0, x1, x2, x3, x4, x5, x6, x7; |
| 10 | output y; |
| 11 | reg y; |
| 12 | |
| 13 | always @(x0 or x1 or x2 or x3 or x4 or x5 or x6 or x7 or sel) |
| 14 | begin |
| 15 | case (sel) |
| 16 | 3'b000: y = x0; |
| 17 | 3'b001: y = x1; |
| 18 | 3'b010: y = x2; |
| 19 | 3'b011: y = x3; |
| 20 | 3'b100: y = x4; |
| 21 | 3'b101: y = x5; |
| 22 | 3'b110: y = x6; |
| 23 | 3'b111: y = x7; |
| 24 | endcase |
| 25 | end |
| 26 | |
| 27 | endmodule |