1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
11 #include "../include/proxmark3.h"
14 #include "../include/hitag2.h"
15 #include "../common/crc16.h"
18 #include "mifareutil.h"
20 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
21 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
23 void LFSetupFPGAForADC(int divisor
, bool lf_field
)
25 FpgaDownloadAndGo(FPGA_BITSTREAM_LF
);
26 if ( (divisor
== 1) || (divisor
< 0) || (divisor
> 255) )
27 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 88); //134.8Khz
28 else if (divisor
== 0)
29 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
31 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, divisor
);
33 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC
| (lf_field
? FPGA_LF_ADC_READER_FIELD
: 0));
35 // Connect the A/D to the peak-detected low-frequency path.
36 SetAdcMuxFor(GPIO_MUXSEL_LOPKD
);
38 // Give it a bit of time for the resonant antenna to settle.
41 // Now set up the SSC to get the ADC samples that are now streaming at us.
45 void AcquireRawAdcSamples125k(int divisor
)
47 LFSetupFPGAForADC(divisor
, true);
51 void SnoopLFRawAdcSamples(int divisor
, int trigger_threshold
)
53 LFSetupFPGAForADC(divisor
, false);
54 DoAcquisition125k_threshold(trigger_threshold
);
57 // split into two routines so we can avoid timing issues after sending commands //
58 void DoAcquisition125k_internal(int trigger_threshold
, bool silent
)
60 uint8_t *dest
= mifare_get_bigbufptr();
63 memset(dest
, 0x00, n
);
66 if (AT91C_BASE_SSC
->SSC_SR
& AT91C_SSC_TXRDY
) {
67 AT91C_BASE_SSC
->SSC_THR
= 0x43;
70 if (AT91C_BASE_SSC
->SSC_SR
& AT91C_SSC_RXRDY
) {
71 dest
[i
] = (uint8_t)AT91C_BASE_SSC
->SSC_RHR
;
73 if (trigger_threshold
!= -1 && dest
[i
] < trigger_threshold
)
76 trigger_threshold
= -1;
81 Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",
82 dest
[0], dest
[1], dest
[2], dest
[3], dest
[4], dest
[5], dest
[6], dest
[7]);
85 void DoAcquisition125k_threshold(int trigger_threshold
) {
86 DoAcquisition125k_internal(trigger_threshold
, true);
88 void DoAcquisition125k() {
89 DoAcquisition125k_internal(-1, true);
92 void ModThenAcquireRawAdcSamples125k(int delay_off
, int period_0
, int period_1
, uint8_t *command
)
95 /* Make sure the tag is reset */
96 FpgaDownloadAndGo(FPGA_BITSTREAM_LF
);
97 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
100 int divisor_used
= 95; // 125 KHz
101 // see if 'h' was specified
103 if (command
[strlen((char *) command
) - 1] == 'h')
104 divisor_used
= 88; // 134.8 KHz
106 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, divisor_used
);
107 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC
| FPGA_LF_ADC_READER_FIELD
);
108 // Give it a bit of time for the resonant antenna to settle.
112 // And a little more time for the tag to fully power up
115 // Now set up the SSC to get the ADC samples that are now streaming at us.
118 // now modulate the reader field
119 while(*command
!= '\0' && *command
!= ' ') {
120 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
122 SpinDelayUs(delay_off
);
123 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, divisor_used
);
125 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC
| FPGA_LF_ADC_READER_FIELD
);
127 if(*(command
++) == '0')
128 SpinDelayUs(period_0
);
130 SpinDelayUs(period_1
);
132 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
134 SpinDelayUs(delay_off
);
135 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, divisor_used
);
137 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC
| FPGA_LF_ADC_READER_FIELD
);
140 DoAcquisition125k(-1);
143 /* blank r/w tag data stream
144 ...0000000000000000 01111111
145 1010101010101010101010101010101010101010101010101010101010101010
148 101010101010101[0]000...
150 [5555fe852c5555555555555555fe0000]
154 // some hardcoded initial params
155 // when we read a TI tag we sample the zerocross line at 2Mhz
156 // TI tags modulate a 1 as 16 cycles of 123.2Khz
157 // TI tags modulate a 0 as 16 cycles of 134.2Khz
158 #define FSAMPLE 2000000
159 #define FREQLO 123200
160 #define FREQHI 134200
162 signed char *dest
= (signed char *)BigBuf
;
163 int n
= sizeof(BigBuf
);
164 // int *dest = GraphBuffer;
165 // int n = GraphTraceLen;
167 // 128 bit shift register [shift3:shift2:shift1:shift0]
168 uint32_t shift3
= 0, shift2
= 0, shift1
= 0, shift0
= 0;
170 int i
, cycles
=0, samples
=0;
171 // how many sample points fit in 16 cycles of each frequency
172 uint32_t sampleslo
= (FSAMPLE
<<4)/FREQLO
, sampleshi
= (FSAMPLE
<<4)/FREQHI
;
173 // when to tell if we're close enough to one freq or another
174 uint32_t threshold
= (sampleslo
- sampleshi
+ 1)>>1;
176 // TI tags charge at 134.2Khz
177 FpgaDownloadAndGo(FPGA_BITSTREAM_LF
);
178 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 88); //134.8Khz
180 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
181 // connects to SSP_DIN and the SSP_DOUT logic level controls
182 // whether we're modulating the antenna (high)
183 // or listening to the antenna (low)
184 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU
);
186 // get TI tag data into the buffer
189 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
191 for (i
=0; i
<n
-1; i
++) {
192 // count cycles by looking for lo to hi zero crossings
193 if ( (dest
[i
]<0) && (dest
[i
+1]>0) ) {
195 // after 16 cycles, measure the frequency
198 samples
=i
-samples
; // number of samples in these 16 cycles
200 // TI bits are coming to us lsb first so shift them
201 // right through our 128 bit right shift register
202 shift0
= (shift0
>>1) | (shift1
<< 31);
203 shift1
= (shift1
>>1) | (shift2
<< 31);
204 shift2
= (shift2
>>1) | (shift3
<< 31);
207 // check if the cycles fall close to the number
208 // expected for either the low or high frequency
209 if ( (samples
>(sampleslo
-threshold
)) && (samples
<(sampleslo
+threshold
)) ) {
210 // low frequency represents a 1
212 } else if ( (samples
>(sampleshi
-threshold
)) && (samples
<(sampleshi
+threshold
)) ) {
213 // high frequency represents a 0
215 // probably detected a gay waveform or noise
216 // use this as gaydar or discard shift register and start again
217 shift3
= shift2
= shift1
= shift0
= 0;
221 // for each bit we receive, test if we've detected a valid tag
223 // if we see 17 zeroes followed by 6 ones, we might have a tag
224 // remember the bits are backwards
225 if ( ((shift0
& 0x7fffff) == 0x7e0000) ) {
226 // if start and end bytes match, we have a tag so break out of the loop
227 if ( ((shift0
>>16)&0xff) == ((shift3
>>8)&0xff) ) {
228 cycles
= 0xF0B; //use this as a flag (ugly but whatever)
236 // if flag is set we have a tag
238 DbpString("Info: No valid tag detected.");
240 // put 64 bit data into shift1 and shift0
241 shift0
= (shift0
>>24) | (shift1
<< 8);
242 shift1
= (shift1
>>24) | (shift2
<< 8);
244 // align 16 bit crc into lower half of shift2
245 shift2
= ((shift2
>>24) | (shift3
<< 8)) & 0x0ffff;
247 // if r/w tag, check ident match
248 if ( shift3
&(1<<15) ) {
249 DbpString("Info: TI tag is rewriteable");
250 // only 15 bits compare, last bit of ident is not valid
251 if ( ((shift3
>>16)^shift0
)&0x7fff ) {
252 DbpString("Error: Ident mismatch!");
254 DbpString("Info: TI tag ident is valid");
257 DbpString("Info: TI tag is readonly");
260 // WARNING the order of the bytes in which we calc crc below needs checking
261 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
262 // bytes in reverse or something
266 crc
= update_crc16(crc
, (shift0
)&0xff);
267 crc
= update_crc16(crc
, (shift0
>>8)&0xff);
268 crc
= update_crc16(crc
, (shift0
>>16)&0xff);
269 crc
= update_crc16(crc
, (shift0
>>24)&0xff);
270 crc
= update_crc16(crc
, (shift1
)&0xff);
271 crc
= update_crc16(crc
, (shift1
>>8)&0xff);
272 crc
= update_crc16(crc
, (shift1
>>16)&0xff);
273 crc
= update_crc16(crc
, (shift1
>>24)&0xff);
275 Dbprintf("Info: Tag data: %x%08x, crc=%x",
276 (unsigned int)shift1
, (unsigned int)shift0
, (unsigned int)shift2
& 0xFFFF);
277 if (crc
!= (shift2
&0xffff)) {
278 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc
);
280 DbpString("Info: CRC is good");
285 void WriteTIbyte(uint8_t b
)
289 // modulate 8 bits out to the antenna
293 // stop modulating antenna
300 // stop modulating antenna
310 void AcquireTiType(void)
313 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
314 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
315 #define TIBUFLEN 1250
318 memset(BigBuf
,0,sizeof(BigBuf
));
320 // Set up the synchronous serial port
321 AT91C_BASE_PIOA
->PIO_PDR
= GPIO_SSC_DIN
;
322 AT91C_BASE_PIOA
->PIO_ASR
= GPIO_SSC_DIN
;
324 // steal this pin from the SSP and use it to control the modulation
325 AT91C_BASE_PIOA
->PIO_PER
= GPIO_SSC_DOUT
;
326 AT91C_BASE_PIOA
->PIO_OER
= GPIO_SSC_DOUT
;
328 AT91C_BASE_SSC
->SSC_CR
= AT91C_SSC_SWRST
;
329 AT91C_BASE_SSC
->SSC_CR
= AT91C_SSC_RXEN
| AT91C_SSC_TXEN
;
331 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
332 // 48/2 = 24 MHz clock must be divided by 12
333 AT91C_BASE_SSC
->SSC_CMR
= 12;
335 AT91C_BASE_SSC
->SSC_RCMR
= SSC_CLOCK_MODE_SELECT(0);
336 AT91C_BASE_SSC
->SSC_RFMR
= SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF
;
337 AT91C_BASE_SSC
->SSC_TCMR
= 0;
338 AT91C_BASE_SSC
->SSC_TFMR
= 0;
345 // Charge TI tag for 50ms.
348 // stop modulating antenna and listen
355 if(AT91C_BASE_SSC
->SSC_SR
& AT91C_SSC_RXRDY
) {
356 BigBuf
[i
] = AT91C_BASE_SSC
->SSC_RHR
; // store 32 bit values in buffer
357 i
++; if(i
>= TIBUFLEN
) break;
362 // return stolen pin to SSP
363 AT91C_BASE_PIOA
->PIO_PDR
= GPIO_SSC_DOUT
;
364 AT91C_BASE_PIOA
->PIO_ASR
= GPIO_SSC_DIN
| GPIO_SSC_DOUT
;
366 char *dest
= (char *)BigBuf
;
369 for (i
=TIBUFLEN
-1; i
>=0; i
--) {
370 for (j
=0; j
<32; j
++) {
371 if(BigBuf
[i
] & (1 << j
)) {
380 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
381 // if crc provided, it will be written with the data verbatim (even if bogus)
382 // if not provided a valid crc will be computed from the data and written.
383 void WriteTItag(uint32_t idhi
, uint32_t idlo
, uint16_t crc
)
385 FpgaDownloadAndGo(FPGA_BITSTREAM_LF
);
387 crc
= update_crc16(crc
, (idlo
)&0xff);
388 crc
= update_crc16(crc
, (idlo
>>8)&0xff);
389 crc
= update_crc16(crc
, (idlo
>>16)&0xff);
390 crc
= update_crc16(crc
, (idlo
>>24)&0xff);
391 crc
= update_crc16(crc
, (idhi
)&0xff);
392 crc
= update_crc16(crc
, (idhi
>>8)&0xff);
393 crc
= update_crc16(crc
, (idhi
>>16)&0xff);
394 crc
= update_crc16(crc
, (idhi
>>24)&0xff);
396 Dbprintf("Writing to tag: %x%08x, crc=%x",
397 (unsigned int) idhi
, (unsigned int) idlo
, crc
);
399 // TI tags charge at 134.2Khz
400 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 88); //134.8Khz
401 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
402 // connects to SSP_DIN and the SSP_DOUT logic level controls
403 // whether we're modulating the antenna (high)
404 // or listening to the antenna (low)
405 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU
);
408 // steal this pin from the SSP and use it to control the modulation
409 AT91C_BASE_PIOA
->PIO_PER
= GPIO_SSC_DOUT
;
410 AT91C_BASE_PIOA
->PIO_OER
= GPIO_SSC_DOUT
;
412 // writing algorithm:
413 // a high bit consists of a field off for 1ms and field on for 1ms
414 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
415 // initiate a charge time of 50ms (field on) then immediately start writing bits
416 // start by writing 0xBB (keyword) and 0xEB (password)
417 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
418 // finally end with 0x0300 (write frame)
419 // all data is sent lsb firts
420 // finish with 15ms programming time
424 SpinDelay(50); // charge time
426 WriteTIbyte(0xbb); // keyword
427 WriteTIbyte(0xeb); // password
428 WriteTIbyte( (idlo
)&0xff );
429 WriteTIbyte( (idlo
>>8 )&0xff );
430 WriteTIbyte( (idlo
>>16)&0xff );
431 WriteTIbyte( (idlo
>>24)&0xff );
432 WriteTIbyte( (idhi
)&0xff );
433 WriteTIbyte( (idhi
>>8 )&0xff );
434 WriteTIbyte( (idhi
>>16)&0xff );
435 WriteTIbyte( (idhi
>>24)&0xff ); // data hi to lo
436 WriteTIbyte( (crc
)&0xff ); // crc lo
437 WriteTIbyte( (crc
>>8 )&0xff ); // crc hi
438 WriteTIbyte(0x00); // write frame lo
439 WriteTIbyte(0x03); // write frame hi
441 SpinDelay(50); // programming time
445 // get TI tag data into the buffer
448 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
449 DbpString("Now use tiread to check");
454 // PIO_CODR = Clear Output Data Register
455 // PIO_SODR = Set Output Data Register
456 //#define LOW(x) AT91C_BASE_PIOA->PIO_CODR = (x)
457 //#define HIGH(x) AT91C_BASE_PIOA->PIO_SODR = (x)
458 void SimulateTagLowFrequency(int period
, int gap
, int ledcontrol
)
461 uint8_t *buf
= (uint8_t *)BigBuf
;
463 FpgaDownloadAndGo(FPGA_BITSTREAM_LF
);
464 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
465 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT
);
467 // Connect the A/D to the peak-detected low-frequency path.
468 SetAdcMuxFor(GPIO_MUXSEL_LOPKD
);
470 // Now set up the SSC to get the ADC samples that are now streaming at us.
473 // Configure output and enable pin that is connected to the FPGA (for modulating)
474 // AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK; // (PIO_PER) PIO Enable Register
475 // AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT; // (PIO_OER) Output Enable Register
476 // AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK; // (PIO_ODR) Output Disable Register
478 AT91C_BASE_PIOA
->PIO_OER
= GPIO_PCK0
;
480 while(!BUTTON_PRESS()) {
483 // PIO_PDSR = Pin Data Status Register
484 // GPIO_SSC_CLK = SSC Transmit Clock
485 // wait ssp_clk == high
486 while(!(AT91C_BASE_PIOA
->PIO_PDSR
& GPIO_SSC_CLK
)) {
488 DbpString("Stopped at 0");
500 DbpString("Enter Sim3");
501 // wait ssp_clk == low
502 while( (AT91C_BASE_PIOA
->PIO_PDSR
& GPIO_SSC_CLK
) ) {
504 DbpString("stopped at 1");
510 DbpString("Enter Sim4 ");
522 DbpString("Stopped");
526 #define DEBUG_FRAME_CONTENTS 1
527 void SimulateTagLowFrequencyBidir(int divisor
, int t0
)
531 // compose fc/8 fc/10 waveform
532 static void fc(int c
, int *n
) {
533 uint8_t *dest
= (uint8_t *)BigBuf
;
536 // for when we want an fc8 pattern every 4 logical bits
547 // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples
549 for (idx
=0; idx
<6; idx
++) {
561 // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples
563 for (idx
=0; idx
<5; idx
++) {
578 // prepare a waveform pattern in the buffer based on the ID given then
579 // simulate a HID tag until the button is pressed
580 void CmdHIDsimTAG(int hi
, int lo
, int ledcontrol
)
584 HID tag bitstream format
585 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
586 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
587 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
588 A fc8 is inserted before every 4 bits
589 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
590 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
594 DbpString("Tags can only have 44 bits.");
598 // special start of frame marker containing invalid bit sequences
599 fc(8, &n
); fc(8, &n
); // invalid
600 fc(8, &n
); fc(10, &n
); // logical 0
601 fc(10, &n
); fc(10, &n
); // invalid
602 fc(8, &n
); fc(10, &n
); // logical 0
605 // manchester encode bits 43 to 32
606 for (i
=11; i
>=0; i
--) {
607 if ((i
%4)==3) fc(0,&n
);
609 fc(10, &n
); fc(8, &n
); // low-high transition
611 fc(8, &n
); fc(10, &n
); // high-low transition
616 // manchester encode bits 31 to 0
617 for (i
=31; i
>=0; i
--) {
618 if ((i
%4)==3) fc(0,&n
);
620 fc(10, &n
); fc(8, &n
); // low-high transition
622 fc(8, &n
); fc(10, &n
); // high-low transition
629 SimulateTagLowFrequency(n
, 0, ledcontrol
);
635 size_t fsk_demod(uint8_t * dest
, size_t size
)
637 uint32_t last_transition
= 0;
640 // we don't care about actual value, only if it's more or less than a
641 // threshold essentially we capture zero crossings for later analysis
642 uint8_t threshold_value
= 127;
644 // sync to first lo-hi transition, and threshold
646 //Need to threshold first sample
647 dest
[0] = (dest
[0] < threshold_value
) ? 0 : 1;
650 // count cycles between consecutive lo-hi transitions, there should be either 8 (fc/8)
651 // or 10 (fc/10) cycles but in practice due to noise etc we may end up with with anywhere
652 // between 7 to 11 cycles so fuzz it by treat anything <9 as 8 and anything else as 10
653 for(idx
= 1; idx
< size
; idx
++) {
654 // threshold current value
655 dest
[idx
] = (dest
[idx
] < threshold_value
) ? 0 : 1;
657 // Check for 0->1 transition
658 if (dest
[idx
-1] < dest
[idx
]) { // 0 -> 1 transition
660 dest
[numBits
] = (idx
-last_transition
< 9) ? 1 : 0;
661 last_transition
= idx
;
665 return numBits
; //Actually, it returns the number of bytes, but each byte represents a bit: 1 or 0
669 size_t aggregate_bits(uint8_t *dest
,size_t size
, uint8_t h2l_crossing_value
,uint8_t l2h_crossing_value
, uint8_t maxConsequtiveBits
)
671 uint8_t lastval
=dest
[0];
676 for( idx
=1; idx
< size
; idx
++) {
678 if (dest
[idx
]==lastval
) {
682 //if lastval was 1, we have a 1->0 crossing
684 n
=(n
+1) / h2l_crossing_value
;
685 } else {// 0->1 crossing
686 n
=(n
+1) / l2h_crossing_value
;
690 if(n
< maxConsequtiveBits
)
692 memset(dest
+numBits
, dest
[idx
-1] , n
);
702 // loop to capture raw HID waveform then FSK demodulate the TAG ID from it
703 void CmdHIDdemodFSK(int findone
, int *high
, int *low
, int ledcontrol
)
705 uint8_t *dest
= (uint8_t *)BigBuf
;
707 size_t size
=0,idx
=0; //, found=0;
708 uint32_t hi2
=0, hi
=0, lo
=0;
710 // Configure to go in 125Khz listen mode
711 LFSetupFPGAForADC(0, true);
713 while(!BUTTON_PRESS()) {
716 if (ledcontrol
) LED_A_ON();
718 DoAcquisition125k_internal(-1,true);
719 size
= sizeof(BigBuf
);
722 size
= fsk_demod(dest
, size
);
724 // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
725 // 1->0 : fc/8 in sets of 6
726 // 0->1 : fc/10 in sets of 5
727 size
= aggregate_bits(dest
,size
, 6,5,5);
731 // final loop, go over previously decoded manchester data and decode into usable tag ID
732 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
733 uint8_t frame_marker_mask
[] = {1,1,1,0,0,0};
736 while( idx
+ sizeof(frame_marker_mask
) < size
) {
737 // search for a start of frame marker
738 if ( memcmp(dest
+idx
, frame_marker_mask
, sizeof(frame_marker_mask
)) == 0)
739 { // frame marker found
740 idx
+=sizeof(frame_marker_mask
);
742 while(dest
[idx
] != dest
[idx
+1] && idx
< size
-2)
744 // Keep going until next frame marker (or error)
745 // Shift in a bit. Start by shifting high registers
746 hi2
=(hi2
<<1)|(hi
>>31);
748 //Then, shift in a 0 or one into low
749 if (dest
[idx
] && !dest
[idx
+1]) // 1 0
757 //Dbprintf("Num shifts: %d ", numshifts);
758 // Hopefully, we read a tag and hit upon the next frame marker
759 if(idx
+ sizeof(frame_marker_mask
) < size
)
761 if ( memcmp(dest
+idx
, frame_marker_mask
, sizeof(frame_marker_mask
)) == 0)
764 Dbprintf("TAG ID: %x%08x%08x (%d)",
765 (unsigned int) hi2
, (unsigned int) hi
, (unsigned int) lo
, (unsigned int) (lo
>>1) & 0xFFFF);
768 Dbprintf("TAG ID: %x%08x (%d)",
769 (unsigned int) hi
, (unsigned int) lo
, (unsigned int) (lo
>>1) & 0xFFFF);
786 DbpString("Stopped");
787 if (ledcontrol
) LED_A_OFF();
790 uint32_t bytebits_to_byte(uint8_t* src
, int numbits
)
793 for(int i
= 0 ; i
< numbits
; i
++)
795 num
= (num
<< 1) | (*src
);
802 void CmdIOdemodFSK(int findone
, int *high
, int *low
, int ledcontrol
)
804 uint8_t *dest
= (uint8_t *)BigBuf
;
806 size_t size
=0, idx
=0;
807 uint32_t code
=0, code2
=0;
809 // Configure to go in 125Khz listen mode
810 LFSetupFPGAForADC(0, true);
812 while(!BUTTON_PRESS()) {
814 if (ledcontrol
) LED_A_ON();
816 DoAcquisition125k_internal(-1,true);
817 size
= sizeof(BigBuf
);
820 size
= fsk_demod(dest
, size
);
822 // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
823 // 1->0 : fc/8 in sets of 7
824 // 0->1 : fc/10 in sets of 6
825 size
= aggregate_bits(dest
, size
, 7,6,13);
830 uint8_t mask
[] = {0,0,0,0,0,0,0,0,0,1};
831 for( idx
=0; idx
< size
- 64; idx
++) {
833 if ( memcmp(dest
+ idx
, mask
, sizeof(mask
)) ) continue;
835 Dbprintf("%d%d%d%d%d%d%d%d",dest
[idx
], dest
[idx
+1], dest
[idx
+2],dest
[idx
+3],dest
[idx
+4],dest
[idx
+5],dest
[idx
+6],dest
[idx
+7]);
836 Dbprintf("%d%d%d%d%d%d%d%d",dest
[idx
+8], dest
[idx
+9], dest
[idx
+10],dest
[idx
+11],dest
[idx
+12],dest
[idx
+13],dest
[idx
+14],dest
[idx
+15]);
837 Dbprintf("%d%d%d%d%d%d%d%d",dest
[idx
+16],dest
[idx
+17],dest
[idx
+18],dest
[idx
+19],dest
[idx
+20],dest
[idx
+21],dest
[idx
+22],dest
[idx
+23]);
838 Dbprintf("%d%d%d%d%d%d%d%d",dest
[idx
+24],dest
[idx
+25],dest
[idx
+26],dest
[idx
+27],dest
[idx
+28],dest
[idx
+29],dest
[idx
+30],dest
[idx
+31]);
839 Dbprintf("%d%d%d%d%d%d%d%d",dest
[idx
+32],dest
[idx
+33],dest
[idx
+34],dest
[idx
+35],dest
[idx
+36],dest
[idx
+37],dest
[idx
+38],dest
[idx
+39]);
840 Dbprintf("%d%d%d%d%d%d%d%d",dest
[idx
+40],dest
[idx
+41],dest
[idx
+42],dest
[idx
+43],dest
[idx
+44],dest
[idx
+45],dest
[idx
+46],dest
[idx
+47]);
841 Dbprintf("%d%d%d%d%d%d%d%d",dest
[idx
+48],dest
[idx
+49],dest
[idx
+50],dest
[idx
+51],dest
[idx
+52],dest
[idx
+53],dest
[idx
+54],dest
[idx
+55]);
842 Dbprintf("%d%d%d%d%d%d%d%d",dest
[idx
+56],dest
[idx
+57],dest
[idx
+58],dest
[idx
+59],dest
[idx
+60],dest
[idx
+61],dest
[idx
+62],dest
[idx
+63]);
844 code
= bytebits_to_byte(dest
+idx
,32);
845 code2
= bytebits_to_byte(dest
+idx
+32,32);
847 short version
= bytebits_to_byte(dest
+idx
+14,4);
848 char unknown
= bytebits_to_byte(dest
+idx
+19,8) ;
849 uint16_t number
= bytebits_to_byte(dest
+idx
+36,9);
851 Dbprintf("XSF(%02d)%02x:%d (%08x%08x)",version
,unknown
,number
,code
,code2
);
852 if (ledcontrol
) LED_D_OFF();
854 // if we're only looking for one tag
862 DbpString("Stopped");
863 if (ledcontrol
) LED_A_OFF();
866 /*------------------------------
867 * T5555/T5557/T5567 routines
868 *------------------------------
871 /* T55x7 configuration register definitions */
872 #define T55x7_POR_DELAY 0x00000001
873 #define T55x7_ST_TERMINATOR 0x00000008
874 #define T55x7_PWD 0x00000010
875 #define T55x7_MAXBLOCK_SHIFT 5
876 #define T55x7_AOR 0x00000200
877 #define T55x7_PSKCF_RF_2 0
878 #define T55x7_PSKCF_RF_4 0x00000400
879 #define T55x7_PSKCF_RF_8 0x00000800
880 #define T55x7_MODULATION_DIRECT 0
881 #define T55x7_MODULATION_PSK1 0x00001000
882 #define T55x7_MODULATION_PSK2 0x00002000
883 #define T55x7_MODULATION_PSK3 0x00003000
884 #define T55x7_MODULATION_FSK1 0x00004000
885 #define T55x7_MODULATION_FSK2 0x00005000
886 #define T55x7_MODULATION_FSK1a 0x00006000
887 #define T55x7_MODULATION_FSK2a 0x00007000
888 #define T55x7_MODULATION_MANCHESTER 0x00008000
889 #define T55x7_MODULATION_BIPHASE 0x00010000
890 #define T55x7_BITRATE_RF_8 0
891 #define T55x7_BITRATE_RF_16 0x00040000
892 #define T55x7_BITRATE_RF_32 0x00080000
893 #define T55x7_BITRATE_RF_40 0x000C0000
894 #define T55x7_BITRATE_RF_50 0x00100000
895 #define T55x7_BITRATE_RF_64 0x00140000
896 #define T55x7_BITRATE_RF_100 0x00180000
897 #define T55x7_BITRATE_RF_128 0x001C0000
899 /* T5555 (Q5) configuration register definitions */
900 #define T5555_ST_TERMINATOR 0x00000001
901 #define T5555_MAXBLOCK_SHIFT 0x00000001
902 #define T5555_MODULATION_MANCHESTER 0
903 #define T5555_MODULATION_PSK1 0x00000010
904 #define T5555_MODULATION_PSK2 0x00000020
905 #define T5555_MODULATION_PSK3 0x00000030
906 #define T5555_MODULATION_FSK1 0x00000040
907 #define T5555_MODULATION_FSK2 0x00000050
908 #define T5555_MODULATION_BIPHASE 0x00000060
909 #define T5555_MODULATION_DIRECT 0x00000070
910 #define T5555_INVERT_OUTPUT 0x00000080
911 #define T5555_PSK_RF_2 0
912 #define T5555_PSK_RF_4 0x00000100
913 #define T5555_PSK_RF_8 0x00000200
914 #define T5555_USE_PWD 0x00000400
915 #define T5555_USE_AOR 0x00000800
916 #define T5555_BITRATE_SHIFT 12
917 #define T5555_FAST_WRITE 0x00004000
918 #define T5555_PAGE_SELECT 0x00008000
921 * Relevant times in microsecond
922 * To compensate antenna falling times shorten the write times
923 * and enlarge the gap ones.
925 #define START_GAP 30*8 // 10 - 50fc 250
926 #define WRITE_GAP 20*8 // 8 - 30fc
927 #define WRITE_0 24*8 // 16 - 31fc 24fc 192
928 #define WRITE_1 54*8 // 48 - 63fc 54fc 432 for T55x7; 448 for E5550
930 // VALUES TAKEN FROM EM4x function: SendForward
931 // START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
932 // WRITE_GAP = 128; (16*8)
933 // WRITE_1 = 256 32*8; (32*8)
935 // These timings work for 4469/4269/4305 (with the 55*8 above)
936 // WRITE_0 = 23*8 , 9*8 SpinDelayUs(23*8);
938 #define T55xx_SAMPLES_SIZE 12000 // 32 x 32 x 10 (32 bit times numofblock (7), times clock skip..)
940 // Write one bit to card
941 void T55xxWriteBit(int bit
)
943 FpgaDownloadAndGo(FPGA_BITSTREAM_LF
);
944 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
945 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC
| FPGA_LF_ADC_READER_FIELD
);
947 SpinDelayUs(WRITE_0
);
949 SpinDelayUs(WRITE_1
);
950 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
951 SpinDelayUs(WRITE_GAP
);
954 // Write one card block in page 0, no lock
955 void T55xxWriteBlock(uint32_t Data
, uint32_t Block
, uint32_t Pwd
, uint8_t PwdMode
)
959 // Set up FPGA, 125kHz
960 // Wait for config.. (192+8190xPOW)x8 == 67ms
961 LFSetupFPGAForADC(0, true);
963 // Now start writting
964 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
965 SpinDelayUs(START_GAP
);
969 T55xxWriteBit(0); //Page 0
972 for (i
= 0x80000000; i
!= 0; i
>>= 1)
973 T55xxWriteBit(Pwd
& i
);
979 for (i
= 0x80000000; i
!= 0; i
>>= 1)
980 T55xxWriteBit(Data
& i
);
983 for (i
= 0x04; i
!= 0; i
>>= 1)
984 T55xxWriteBit(Block
& i
);
986 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
987 // so wait a little more)
988 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
989 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC
| FPGA_LF_ADC_READER_FIELD
);
991 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
994 // Read one card block in page 0
995 void T55xxReadBlock(uint32_t Block
, uint32_t Pwd
, uint8_t PwdMode
)
997 uint8_t *dest
= mifare_get_bigbufptr();
998 uint16_t bufferlength
= T55xx_SAMPLES_SIZE
;
1001 // Clear destination buffer before sending the command 0x80 = average.
1002 memset(dest
, 0x80, bufferlength
);
1004 // Set up FPGA, 125kHz
1005 // Wait for config.. (192+8190xPOW)x8 == 67ms
1006 LFSetupFPGAForADC(0, true);
1008 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
1009 SpinDelayUs(START_GAP
);
1013 T55xxWriteBit(0); //Page 0
1016 for (i
= 0x80000000; i
!= 0; i
>>= 1)
1017 T55xxWriteBit(Pwd
& i
);
1022 for (i
= 0x04; i
!= 0; i
>>= 1)
1023 T55xxWriteBit(Block
& i
);
1025 // Turn field on to read the response
1028 // Now do the acquisition
1031 if (AT91C_BASE_SSC
->SSC_SR
& AT91C_SSC_TXRDY
) {
1032 AT91C_BASE_SSC
->SSC_THR
= 0x43;
1035 if (AT91C_BASE_SSC
->SSC_SR
& AT91C_SSC_RXRDY
) {
1036 dest
[i
] = (uint8_t)AT91C_BASE_SSC
->SSC_RHR
;
1039 if (i
> bufferlength
) break;
1043 cmd_send(CMD_ACK
,0,0,0,0,0);
1044 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
); // field off
1048 // Read card traceability data (page 1)
1049 void T55xxReadTrace(void){
1050 uint8_t *dest
= mifare_get_bigbufptr();
1051 uint16_t bufferlength
= T55xx_SAMPLES_SIZE
;
1054 // Clear destination buffer before sending the command 0x80 = average
1055 memset(dest
, 0x80, bufferlength
);
1057 LFSetupFPGAForADC(0, true);
1059 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
1060 SpinDelayUs(START_GAP
);
1064 T55xxWriteBit(1); //Page 1
1066 // Turn field on to read the response
1069 // Now do the acquisition
1071 if (AT91C_BASE_SSC
->SSC_SR
& AT91C_SSC_TXRDY
) {
1072 AT91C_BASE_SSC
->SSC_THR
= 0x43;
1075 if (AT91C_BASE_SSC
->SSC_SR
& AT91C_SSC_RXRDY
) {
1076 dest
[i
] = (uint8_t)AT91C_BASE_SSC
->SSC_RHR
;
1080 if (i
>= bufferlength
) break;
1084 cmd_send(CMD_ACK
,0,0,0,0,0);
1085 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
); // field off
1089 void TurnReadLFOn(){
1090 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
1091 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC
| FPGA_LF_ADC_READER_FIELD
);
1092 // Give it a bit of time for the resonant antenna to settle.
1097 /*-------------- Cloning routines -----------*/
1098 // Copy HID id to card and setup block 0 config
1099 void CopyHIDtoT55x7(uint32_t hi2
, uint32_t hi
, uint32_t lo
, uint8_t longFMT
)
1101 int data1
=0, data2
=0, data3
=0, data4
=0, data5
=0, data6
=0; //up to six blocks for long format
1105 // Ensure no more than 84 bits supplied
1107 DbpString("Tags can only have 84 bits.");
1110 // Build the 6 data blocks for supplied 84bit ID
1112 data1
= 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1113 for (int i
=0;i
<4;i
++) {
1114 if (hi2
& (1<<(19-i
)))
1115 data1
|= (1<<(((3-i
)*2)+1)); // 1 -> 10
1117 data1
|= (1<<((3-i
)*2)); // 0 -> 01
1121 for (int i
=0;i
<16;i
++) {
1122 if (hi2
& (1<<(15-i
)))
1123 data2
|= (1<<(((15-i
)*2)+1)); // 1 -> 10
1125 data2
|= (1<<((15-i
)*2)); // 0 -> 01
1129 for (int i
=0;i
<16;i
++) {
1130 if (hi
& (1<<(31-i
)))
1131 data3
|= (1<<(((15-i
)*2)+1)); // 1 -> 10
1133 data3
|= (1<<((15-i
)*2)); // 0 -> 01
1137 for (int i
=0;i
<16;i
++) {
1138 if (hi
& (1<<(15-i
)))
1139 data4
|= (1<<(((15-i
)*2)+1)); // 1 -> 10
1141 data4
|= (1<<((15-i
)*2)); // 0 -> 01
1145 for (int i
=0;i
<16;i
++) {
1146 if (lo
& (1<<(31-i
)))
1147 data5
|= (1<<(((15-i
)*2)+1)); // 1 -> 10
1149 data5
|= (1<<((15-i
)*2)); // 0 -> 01
1153 for (int i
=0;i
<16;i
++) {
1154 if (lo
& (1<<(15-i
)))
1155 data6
|= (1<<(((15-i
)*2)+1)); // 1 -> 10
1157 data6
|= (1<<((15-i
)*2)); // 0 -> 01
1161 // Ensure no more than 44 bits supplied
1163 DbpString("Tags can only have 44 bits.");
1167 // Build the 3 data blocks for supplied 44bit ID
1170 data1
= 0x1D000000; // load preamble
1172 for (int i
=0;i
<12;i
++) {
1173 if (hi
& (1<<(11-i
)))
1174 data1
|= (1<<(((11-i
)*2)+1)); // 1 -> 10
1176 data1
|= (1<<((11-i
)*2)); // 0 -> 01
1180 for (int i
=0;i
<16;i
++) {
1181 if (lo
& (1<<(31-i
)))
1182 data2
|= (1<<(((15-i
)*2)+1)); // 1 -> 10
1184 data2
|= (1<<((15-i
)*2)); // 0 -> 01
1188 for (int i
=0;i
<16;i
++) {
1189 if (lo
& (1<<(15-i
)))
1190 data3
|= (1<<(((15-i
)*2)+1)); // 1 -> 10
1192 data3
|= (1<<((15-i
)*2)); // 0 -> 01
1197 // Program the data blocks for supplied ID
1198 // and the block 0 for HID format
1199 T55xxWriteBlock(data1
,1,0,0);
1200 T55xxWriteBlock(data2
,2,0,0);
1201 T55xxWriteBlock(data3
,3,0,0);
1203 if (longFMT
) { // if long format there are 6 blocks
1204 T55xxWriteBlock(data4
,4,0,0);
1205 T55xxWriteBlock(data5
,5,0,0);
1206 T55xxWriteBlock(data6
,6,0,0);
1209 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1210 T55xxWriteBlock(T55x7_BITRATE_RF_50
|
1211 T55x7_MODULATION_FSK2a
|
1212 last_block
<< T55x7_MAXBLOCK_SHIFT
,
1220 void CopyIOtoT55x7(uint32_t hi
, uint32_t lo
, uint8_t longFMT
)
1222 int data1
=0, data2
=0; //up to six blocks for long format
1224 data1
= hi
; // load preamble
1228 // Program the data blocks for supplied ID
1229 // and the block 0 for HID format
1230 T55xxWriteBlock(data1
,1,0,0);
1231 T55xxWriteBlock(data2
,2,0,0);
1234 T55xxWriteBlock(0x00147040,0,0,0);
1240 // Define 9bit header for EM410x tags
1241 #define EM410X_HEADER 0x1FF
1242 #define EM410X_ID_LENGTH 40
1244 void WriteEM410x(uint32_t card
, uint32_t id_hi
, uint32_t id_lo
)
1247 uint64_t id
= EM410X_HEADER
;
1248 uint64_t rev_id
= 0; // reversed ID
1249 int c_parity
[4]; // column parity
1250 int r_parity
= 0; // row parity
1253 // Reverse ID bits given as parameter (for simpler operations)
1254 for (i
= 0; i
< EM410X_ID_LENGTH
; ++i
) {
1256 rev_id
= (rev_id
<< 1) | (id_lo
& 1);
1259 rev_id
= (rev_id
<< 1) | (id_hi
& 1);
1264 for (i
= 0; i
< EM410X_ID_LENGTH
; ++i
) {
1265 id_bit
= rev_id
& 1;
1268 // Don't write row parity bit at start of parsing
1270 id
= (id
<< 1) | r_parity
;
1271 // Start counting parity for new row
1278 // First elements in column?
1280 // Fill out first elements
1281 c_parity
[i
] = id_bit
;
1283 // Count column parity
1284 c_parity
[i
% 4] ^= id_bit
;
1287 id
= (id
<< 1) | id_bit
;
1291 // Insert parity bit of last row
1292 id
= (id
<< 1) | r_parity
;
1294 // Fill out column parity at the end of tag
1295 for (i
= 0; i
< 4; ++i
)
1296 id
= (id
<< 1) | c_parity
[i
];
1301 Dbprintf("Started writing %s tag ...", card
? "T55x7":"T5555");
1305 T55xxWriteBlock((uint32_t)(id
>> 32), 1, 0, 0);
1306 T55xxWriteBlock((uint32_t)id
, 2, 0, 0);
1308 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1310 // Clock rate is stored in bits 8-15 of the card value
1311 clock
= (card
& 0xFF00) >> 8;
1312 Dbprintf("Clock rate: %d", clock
);
1316 clock
= T55x7_BITRATE_RF_32
;
1319 clock
= T55x7_BITRATE_RF_16
;
1322 // A value of 0 is assumed to be 64 for backwards-compatibility
1325 clock
= T55x7_BITRATE_RF_64
;
1328 Dbprintf("Invalid clock rate: %d", clock
);
1332 // Writing configuration for T55x7 tag
1333 T55xxWriteBlock(clock
|
1334 T55x7_MODULATION_MANCHESTER
|
1335 2 << T55x7_MAXBLOCK_SHIFT
,
1339 // Writing configuration for T5555(Q5) tag
1340 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT
|
1341 T5555_MODULATION_MANCHESTER
|
1342 2 << T5555_MAXBLOCK_SHIFT
,
1346 Dbprintf("Tag %s written with 0x%08x%08x\n", card
? "T55x7":"T5555",
1347 (uint32_t)(id
>> 32), (uint32_t)id
);
1350 // Clone Indala 64-bit tag by UID to T55x7
1351 void CopyIndala64toT55x7(int hi
, int lo
)
1353 //Program the 2 data blocks for supplied 64bit UID
1354 // and the block 0 for Indala64 format
1355 T55xxWriteBlock(hi
,1,0,0);
1356 T55xxWriteBlock(lo
,2,0,0);
1357 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1358 T55xxWriteBlock(T55x7_BITRATE_RF_32
|
1359 T55x7_MODULATION_PSK1
|
1360 2 << T55x7_MAXBLOCK_SHIFT
,
1362 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1363 // T5567WriteBlock(0x603E1042,0);
1368 void CopyIndala224toT55x7(int uid1
, int uid2
, int uid3
, int uid4
, int uid5
, int uid6
, int uid7
)
1370 //Program the 7 data blocks for supplied 224bit UID
1371 // and the block 0 for Indala224 format
1372 T55xxWriteBlock(uid1
,1,0,0);
1373 T55xxWriteBlock(uid2
,2,0,0);
1374 T55xxWriteBlock(uid3
,3,0,0);
1375 T55xxWriteBlock(uid4
,4,0,0);
1376 T55xxWriteBlock(uid5
,5,0,0);
1377 T55xxWriteBlock(uid6
,6,0,0);
1378 T55xxWriteBlock(uid7
,7,0,0);
1379 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1380 T55xxWriteBlock(T55x7_BITRATE_RF_32
|
1381 T55x7_MODULATION_PSK1
|
1382 7 << T55x7_MAXBLOCK_SHIFT
,
1384 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1385 // T5567WriteBlock(0x603E10E2,0);
1391 #define abs(x) ( ((x)<0) ? -(x) : (x) )
1392 #define max(x,y) ( x<y ? y:x)
1394 int DemodPCF7931(uint8_t **outBlocks
) {
1395 uint8_t BitStream
[256];
1396 uint8_t Blocks
[8][16];
1397 uint8_t *GraphBuffer
= (uint8_t *)BigBuf
;
1398 int GraphTraceLen
= sizeof(BigBuf
);
1399 int i
, j
, lastval
, bitidx
, half_switch
;
1401 int tolerance
= clock
/ 8;
1402 int pmc
, block_done
;
1403 int lc
, warnings
= 0;
1405 int lmin
=128, lmax
=128;
1408 AcquireRawAdcSamples125k(0);
1415 /* Find first local max/min */
1416 if(GraphBuffer
[1] > GraphBuffer
[0]) {
1417 while(i
< GraphTraceLen
) {
1418 if( !(GraphBuffer
[i
] > GraphBuffer
[i
-1]) && GraphBuffer
[i
] > lmax
)
1425 while(i
< GraphTraceLen
) {
1426 if( !(GraphBuffer
[i
] < GraphBuffer
[i
-1]) && GraphBuffer
[i
] < lmin
)
1438 for (bitidx
= 0; i
< GraphTraceLen
; i
++)
1440 if ( (GraphBuffer
[i
-1] > GraphBuffer
[i
] && dir
== 1 && GraphBuffer
[i
] > lmax
) || (GraphBuffer
[i
-1] < GraphBuffer
[i
] && dir
== 0 && GraphBuffer
[i
] < lmin
))
1445 // Switch depending on lc length:
1446 // Tolerance is 1/8 of clock rate (arbitrary)
1447 if (abs(lc
-clock
/4) < tolerance
) {
1449 if((i
- pmc
) == lc
) { /* 16T0 was previous one */
1451 i
+= (128+127+16+32+33+16)-1;
1459 } else if (abs(lc
-clock
/2) < tolerance
) {
1461 if((i
- pmc
) == lc
) { /* 16T0 was previous one */
1463 i
+= (128+127+16+32+33)-1;
1468 else if(half_switch
== 1) {
1469 BitStream
[bitidx
++] = 0;
1474 } else if (abs(lc
-clock
) < tolerance
) {
1476 BitStream
[bitidx
++] = 1;
1482 Dbprintf("Error: too many detection errors, aborting.");
1487 if(block_done
== 1) {
1489 for(j
=0; j
<16; j
++) {
1490 Blocks
[num_blocks
][j
] = 128*BitStream
[j
*8+7]+
1491 64*BitStream
[j
*8+6]+
1492 32*BitStream
[j
*8+5]+
1493 16*BitStream
[j
*8+4]+
1505 if (GraphBuffer
[i
-1] > GraphBuffer
[i
]) dir
=0;
1511 if(num_blocks
== 4) break;
1513 memcpy(outBlocks
, Blocks
, 16*num_blocks
);
1517 int IsBlock0PCF7931(uint8_t *Block
) {
1518 // Assume RFU means 0 :)
1519 if((memcmp(Block
, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block
+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1521 if((memcmp(Block
+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block
[7] == 0) // PAC disabled, can it *really* happen ?
1526 int IsBlock1PCF7931(uint8_t *Block
) {
1527 // Assume RFU means 0 :)
1528 if(Block
[10] == 0 && Block
[11] == 0 && Block
[12] == 0 && Block
[13] == 0)
1529 if((Block
[14] & 0x7f) <= 9 && Block
[15] <= 9)
1536 void ReadPCF7931() {
1537 uint8_t Blocks
[8][17];
1538 uint8_t tmpBlocks
[4][16];
1539 int i
, j
, ind
, ind2
, n
;
1546 memset(Blocks
, 0, 8*17*sizeof(uint8_t));
1549 memset(tmpBlocks
, 0, 4*16*sizeof(uint8_t));
1550 n
= DemodPCF7931((uint8_t**)tmpBlocks
);
1553 if(error
==10 && num_blocks
== 0) {
1554 Dbprintf("Error, no tag or bad tag");
1557 else if (tries
==20 || error
==10) {
1558 Dbprintf("Error reading the tag");
1559 Dbprintf("Here is the partial content");
1564 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1565 tmpBlocks
[i
][0], tmpBlocks
[i
][1], tmpBlocks
[i
][2], tmpBlocks
[i
][3], tmpBlocks
[i
][4], tmpBlocks
[i
][5], tmpBlocks
[i
][6], tmpBlocks
[i
][7],
1566 tmpBlocks
[i
][8], tmpBlocks
[i
][9], tmpBlocks
[i
][10], tmpBlocks
[i
][11], tmpBlocks
[i
][12], tmpBlocks
[i
][13], tmpBlocks
[i
][14], tmpBlocks
[i
][15]);
1568 for(i
=0; i
<n
; i
++) {
1569 if(IsBlock0PCF7931(tmpBlocks
[i
])) {
1571 if(i
< n
-1 && IsBlock1PCF7931(tmpBlocks
[i
+1])) {
1575 memcpy(Blocks
[0], tmpBlocks
[i
], 16);
1576 Blocks
[0][ALLOC
] = 1;
1577 memcpy(Blocks
[1], tmpBlocks
[i
+1], 16);
1578 Blocks
[1][ALLOC
] = 1;
1579 max_blocks
= max((Blocks
[1][14] & 0x7f), Blocks
[1][15]) + 1;
1581 Dbprintf("(dbg) Max blocks: %d", max_blocks
);
1583 // Handle following blocks
1584 for(j
=i
+2, ind2
=2; j
!=i
; j
++, ind2
++, num_blocks
++) {
1587 memcpy(Blocks
[ind2
], tmpBlocks
[j
], 16);
1588 Blocks
[ind2
][ALLOC
] = 1;
1596 for(i
=0; i
<n
; i
++) { // Look for identical block in known blocks
1597 if(memcmp(tmpBlocks
[i
], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1598 for(j
=0; j
<max_blocks
; j
++) {
1599 if(Blocks
[j
][ALLOC
] == 1 && !memcmp(tmpBlocks
[i
], Blocks
[j
], 16)) {
1600 // Found an identical block
1601 for(ind
=i
-1,ind2
=j
-1; ind
>= 0; ind
--,ind2
--) {
1604 if(!Blocks
[ind2
][ALLOC
]) { // Block ind2 not already found
1605 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1606 memcpy(Blocks
[ind2
], tmpBlocks
[ind
], 16);
1607 Blocks
[ind2
][ALLOC
] = 1;
1609 if(num_blocks
== max_blocks
) goto end
;
1612 for(ind
=i
+1,ind2
=j
+1; ind
< n
; ind
++,ind2
++) {
1613 if(ind2
> max_blocks
)
1615 if(!Blocks
[ind2
][ALLOC
]) { // Block ind2 not already found
1616 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1617 memcpy(Blocks
[ind2
], tmpBlocks
[ind
], 16);
1618 Blocks
[ind2
][ALLOC
] = 1;
1620 if(num_blocks
== max_blocks
) goto end
;
1629 if (BUTTON_PRESS()) return;
1630 } while (num_blocks
!= max_blocks
);
1632 Dbprintf("-----------------------------------------");
1633 Dbprintf("Memory content:");
1634 Dbprintf("-----------------------------------------");
1635 for(i
=0; i
<max_blocks
; i
++) {
1636 if(Blocks
[i
][ALLOC
]==1)
1637 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1638 Blocks
[i
][0], Blocks
[i
][1], Blocks
[i
][2], Blocks
[i
][3], Blocks
[i
][4], Blocks
[i
][5], Blocks
[i
][6], Blocks
[i
][7],
1639 Blocks
[i
][8], Blocks
[i
][9], Blocks
[i
][10], Blocks
[i
][11], Blocks
[i
][12], Blocks
[i
][13], Blocks
[i
][14], Blocks
[i
][15]);
1641 Dbprintf("<missing block %d>", i
);
1643 Dbprintf("-----------------------------------------");
1649 //-----------------------------------
1650 // EM4469 / EM4305 routines
1651 //-----------------------------------
1652 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1653 #define FWD_CMD_WRITE 0xA
1654 #define FWD_CMD_READ 0x9
1655 #define FWD_CMD_DISABLE 0x5
1658 uint8_t forwardLink_data
[64]; //array of forwarded bits
1659 uint8_t * forward_ptr
; //ptr for forward message preparation
1660 uint8_t fwd_bit_sz
; //forwardlink bit counter
1661 uint8_t * fwd_write_ptr
; //forwardlink bit pointer
1663 //====================================================================
1664 // prepares command bits
1666 //====================================================================
1667 //--------------------------------------------------------------------
1668 uint8_t Prepare_Cmd( uint8_t cmd
) {
1669 //--------------------------------------------------------------------
1671 *forward_ptr
++ = 0; //start bit
1672 *forward_ptr
++ = 0; //second pause for 4050 code
1674 *forward_ptr
++ = cmd
;
1676 *forward_ptr
++ = cmd
;
1678 *forward_ptr
++ = cmd
;
1680 *forward_ptr
++ = cmd
;
1682 return 6; //return number of emited bits
1685 //====================================================================
1686 // prepares address bits
1688 //====================================================================
1690 //--------------------------------------------------------------------
1691 uint8_t Prepare_Addr( uint8_t addr
) {
1692 //--------------------------------------------------------------------
1694 register uint8_t line_parity
;
1699 *forward_ptr
++ = addr
;
1700 line_parity
^= addr
;
1704 *forward_ptr
++ = (line_parity
& 1);
1706 return 7; //return number of emited bits
1709 //====================================================================
1710 // prepares data bits intreleaved with parity bits
1712 //====================================================================
1714 //--------------------------------------------------------------------
1715 uint8_t Prepare_Data( uint16_t data_low
, uint16_t data_hi
) {
1716 //--------------------------------------------------------------------
1718 register uint8_t line_parity
;
1719 register uint8_t column_parity
;
1720 register uint8_t i
, j
;
1721 register uint16_t data
;
1726 for(i
=0; i
<4; i
++) {
1728 for(j
=0; j
<8; j
++) {
1729 line_parity
^= data
;
1730 column_parity
^= (data
& 1) << j
;
1731 *forward_ptr
++ = data
;
1734 *forward_ptr
++ = line_parity
;
1739 for(j
=0; j
<8; j
++) {
1740 *forward_ptr
++ = column_parity
;
1741 column_parity
>>= 1;
1745 return 45; //return number of emited bits
1748 //====================================================================
1749 // Forward Link send function
1750 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1751 // fwd_bit_count set with number of bits to be sent
1752 //====================================================================
1753 void SendForward(uint8_t fwd_bit_count
) {
1755 fwd_write_ptr
= forwardLink_data
;
1756 fwd_bit_sz
= fwd_bit_count
;
1761 FpgaDownloadAndGo(FPGA_BITSTREAM_LF
);
1762 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
1763 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC
| FPGA_LF_ADC_READER_FIELD
);
1765 // Give it a bit of time for the resonant antenna to settle.
1766 // And for the tag to fully power up
1769 // force 1st mod pulse (start gap must be longer for 4305)
1770 fwd_bit_sz
--; //prepare next bit modulation
1772 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
); // field off
1773 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1774 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
1775 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC
| FPGA_LF_ADC_READER_FIELD
);//field on
1776 SpinDelayUs(16*8); //16 cycles on (8us each)
1778 // now start writting
1779 while(fwd_bit_sz
-- > 0) { //prepare next bit modulation
1780 if(((*fwd_write_ptr
++) & 1) == 1)
1781 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1783 //These timings work for 4469/4269/4305 (with the 55*8 above)
1784 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
); // field off
1785 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1786 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
1787 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC
| FPGA_LF_ADC_READER_FIELD
);//field on
1788 SpinDelayUs(9*8); //16 cycles on (8us each)
1794 void EM4xLogin(uint32_t Password
) {
1796 uint8_t fwd_bit_count
;
1798 forward_ptr
= forwardLink_data
;
1799 fwd_bit_count
= Prepare_Cmd( FWD_CMD_LOGIN
);
1800 fwd_bit_count
+= Prepare_Data( Password
&0xFFFF, Password
>>16 );
1802 SendForward(fwd_bit_count
);
1804 //Wait for command to complete
1809 void EM4xReadWord(uint8_t Address
, uint32_t Pwd
, uint8_t PwdMode
) {
1811 uint8_t *dest
= mifare_get_bigbufptr();
1812 uint16_t bufferlength
= 12000;
1815 // Clear destination buffer before sending the command 0x80 = average.
1816 memset(dest
, 0x80, bufferlength
);
1818 uint8_t fwd_bit_count
;
1820 //If password mode do login
1821 if (PwdMode
== 1) EM4xLogin(Pwd
);
1823 forward_ptr
= forwardLink_data
;
1824 fwd_bit_count
= Prepare_Cmd( FWD_CMD_READ
);
1825 fwd_bit_count
+= Prepare_Addr( Address
);
1827 // Connect the A/D to the peak-detected low-frequency path.
1828 SetAdcMuxFor(GPIO_MUXSEL_LOPKD
);
1829 // Now set up the SSC to get the ADC samples that are now streaming at us.
1832 SendForward(fwd_bit_count
);
1834 // // Turn field on to read the response
1837 // Now do the acquisition
1840 if (AT91C_BASE_SSC
->SSC_SR
& AT91C_SSC_TXRDY
) {
1841 AT91C_BASE_SSC
->SSC_THR
= 0x43;
1843 if (AT91C_BASE_SSC
->SSC_SR
& AT91C_SSC_RXRDY
) {
1844 dest
[i
] = (uint8_t)AT91C_BASE_SSC
->SSC_RHR
;
1846 if (i
>= bufferlength
) break;
1850 cmd_send(CMD_ACK
,0,0,0,0,0);
1851 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
); // field off
1855 void EM4xWriteWord(uint32_t Data
, uint8_t Address
, uint32_t Pwd
, uint8_t PwdMode
) {
1857 uint8_t fwd_bit_count
;
1859 //If password mode do login
1860 if (PwdMode
== 1) EM4xLogin(Pwd
);
1862 forward_ptr
= forwardLink_data
;
1863 fwd_bit_count
= Prepare_Cmd( FWD_CMD_WRITE
);
1864 fwd_bit_count
+= Prepare_Addr( Address
);
1865 fwd_bit_count
+= Prepare_Data( Data
&0xFFFF, Data
>>16 );
1867 SendForward(fwd_bit_count
);
1869 //Wait for write to complete
1871 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
); // field off