]> cvs.zerfleddert.de Git - proxmark3-svn/blob - armsrc/iso14443b.c
projects / proxmark3-svn / blob
? search:


0ea66a8d7079c65637d5a1e27154e075291dc8d5
[proxmark3-svn] / armsrc / iso14443b.c
1 //-----------------------------------------------------------------------------
2 // Jonathan Westhues, split Nov 2006
3 //
4 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
5 // at your option, any later version. See the LICENSE.txt file for the text of
6 // the license.
7 //-----------------------------------------------------------------------------
8 // Routines to support ISO 14443B. This includes both the reader software and
9 // the `fake tag' modes.
10 //-----------------------------------------------------------------------------
11
12 #include "proxmark3.h"
13 #include "apps.h"
14 #include "util.h"
15 #include "string.h"
16 #include "iso14443crc.h"
17 #include "common.h"
18 #define RECEIVE_SAMPLES_TIMEOUT 600000
19 #define ISO14443B_DMA_BUFFER_SIZE 256
20
21
22 // PCB Block number for APDUs
23 static uint8_t pcb_blocknum = 0;
24
25 //=============================================================================
26 // An ISO 14443 Type B tag. We listen for commands from the reader, using
27 // a UART kind of thing that's implemented in software. When we get a
28 // frame (i.e., a group of bytes between SOF and EOF), we check the CRC.
29 // If it's good, then we can do something appropriate with it, and send
30 // a response.
31 //=============================================================================
32
33 //-----------------------------------------------------------------------------
34 // Code up a string of octets at layer 2 (including CRC, we don't generate
35 // that here) so that they can be transmitted to the reader. Doesn't transmit
36 // them yet, just leaves them ready to send in ToSend[].
37 //-----------------------------------------------------------------------------
38 static void CodeIso14443bAsTag(const uint8_t *cmd, int len)
39 {
40 int i;
41
42 ToSendReset();
43
44 // Transmit a burst of ones, as the initial thing that lets the
45 // reader get phase sync. This (TR1) must be > 80/fs, per spec,
46 // but tag that I've tried (a Paypass) exceeds that by a fair bit,
47 // so I will too.
48 for(i = 0; i < 20; i++) {
49 ToSendStuffBit(1);
50 ToSendStuffBit(1);
51 ToSendStuffBit(1);
52 ToSendStuffBit(1);
53 }
54
55 // Send SOF.
56 for(i = 0; i < 10; i++) {
57 ToSendStuffBit(0);
58 ToSendStuffBit(0);
59 ToSendStuffBit(0);
60 ToSendStuffBit(0);
61 }
62 for(i = 0; i < 2; i++) {
63 ToSendStuffBit(1);
64 ToSendStuffBit(1);
65 ToSendStuffBit(1);
66 ToSendStuffBit(1);
67 }
68
69 for(i = 0; i < len; i++) {
70 int j;
71 uint8_t b = cmd[i];
72
73 // Start bit
74 ToSendStuffBit(0);
75 ToSendStuffBit(0);
76 ToSendStuffBit(0);
77 ToSendStuffBit(0);
78
79 // Data bits
80 for(j = 0; j < 8; j++) {
81 if(b & 1) {
82 ToSendStuffBit(1);
83 ToSendStuffBit(1);
84 ToSendStuffBit(1);
85 ToSendStuffBit(1);
86 } else {
87 ToSendStuffBit(0);
88 ToSendStuffBit(0);
89 ToSendStuffBit(0);
90 ToSendStuffBit(0);
91 }
92 b >>= 1;
93 }
94
95 // Stop bit
96 ToSendStuffBit(1);
97 ToSendStuffBit(1);
98 ToSendStuffBit(1);
99 ToSendStuffBit(1);
100 }
101
102 // Send EOF.
103 for(i = 0; i < 10; i++) {
104 ToSendStuffBit(0);
105 ToSendStuffBit(0);
106 ToSendStuffBit(0);
107 ToSendStuffBit(0);
108 }
109 for(i = 0; i < 2; i++) {
110 ToSendStuffBit(1);
111 ToSendStuffBit(1);
112 ToSendStuffBit(1);
113 ToSendStuffBit(1);
114 }
115
116 // Convert from last byte pos to length
117 ToSendMax++;
118 }
119
120 //-----------------------------------------------------------------------------
121 // The software UART that receives commands from the reader, and its state
122 // variables.
123 //-----------------------------------------------------------------------------
124 static struct {
125 enum {
126 STATE_UNSYNCD,
127 STATE_GOT_FALLING_EDGE_OF_SOF,
128 STATE_AWAITING_START_BIT,
129 STATE_RECEIVING_DATA
130 } state;
131 uint16_t shiftReg;
132 int bitCnt;
133 int byteCnt;
134 int byteCntMax;
135 int posCnt;
136 uint8_t *output;
137 } Uart;
138
139 /* Receive & handle a bit coming from the reader.
140 *
141 * This function is called 4 times per bit (every 2 subcarrier cycles).
142 * Subcarrier frequency fs is 848kHz, 1/fs = 1,18us, i.e. function is called every 2,36us
143 *
144 * LED handling:
145 * LED A -> ON once we have received the SOF and are expecting the rest.
146 * LED A -> OFF once we have received EOF or are in error state or unsynced
147 *
148 * Returns: true if we received a EOF
149 * false if we are still waiting for some more
150 */
151 static RAMFUNC int Handle14443bUartBit(uint8_t bit)
152 {
153 switch(Uart.state) {
154 case STATE_UNSYNCD:
155 if(!bit) {
156 // we went low, so this could be the beginning
157 // of an SOF
158 Uart.state = STATE_GOT_FALLING_EDGE_OF_SOF;
159 Uart.posCnt = 0;
160 Uart.bitCnt = 0;
161 }
162 break;
163
164 case STATE_GOT_FALLING_EDGE_OF_SOF:
165 Uart.posCnt++;
166 if(Uart.posCnt == 2) { // sample every 4 1/fs in the middle of a bit
167 if(bit) {
168 if(Uart.bitCnt > 9) {
169 // we've seen enough consecutive
170 // zeros that it's a valid SOF
171 Uart.posCnt = 0;
172 Uart.byteCnt = 0;
173 Uart.state = STATE_AWAITING_START_BIT;
174 LED_A_ON(); // Indicate we got a valid SOF
175 } else {
176 // didn't stay down long enough
177 // before going high, error
178 Uart.state = STATE_UNSYNCD;
179 }
180 } else {
181 // do nothing, keep waiting
182 }
183 Uart.bitCnt++;
184 }
185 if(Uart.posCnt >= 4) Uart.posCnt = 0;
186 if(Uart.bitCnt > 12) {
187 // Give up if we see too many zeros without
188 // a one, too.
189 LED_A_OFF();
190 Uart.state = STATE_UNSYNCD;
191 }
192 break;
193
194 case STATE_AWAITING_START_BIT:
195 Uart.posCnt++;
196 if(bit) {
197 if(Uart.posCnt > 50/2) { // max 57us between characters = 49 1/fs, max 3 etus after low phase of SOF = 24 1/fs
198 // stayed high for too long between
199 // characters, error
200 Uart.state = STATE_UNSYNCD;
201 }
202 } else {
203 // falling edge, this starts the data byte
204 Uart.posCnt = 0;
205 Uart.bitCnt = 0;
206 Uart.shiftReg = 0;
207 Uart.state = STATE_RECEIVING_DATA;
208 }
209 break;
210
211 case STATE_RECEIVING_DATA:
212 Uart.posCnt++;
213 if(Uart.posCnt == 2) {
214 // time to sample a bit
215 Uart.shiftReg >>= 1;
216 if(bit) {
217 Uart.shiftReg |= 0x200;
218 }
219 Uart.bitCnt++;
220 }
221 if(Uart.posCnt >= 4) {
222 Uart.posCnt = 0;
223 }
224 if(Uart.bitCnt == 10) {
225 if((Uart.shiftReg & 0x200) && !(Uart.shiftReg & 0x001))
226 {
227 // this is a data byte, with correct
228 // start and stop bits
229 Uart.output[Uart.byteCnt] = (Uart.shiftReg >> 1) & 0xff;
230 Uart.byteCnt++;
231
232 if(Uart.byteCnt >= Uart.byteCntMax) {
233 // Buffer overflowed, give up
234 LED_A_OFF();
235 Uart.state = STATE_UNSYNCD;
236 } else {
237 // so get the next byte now
238 Uart.posCnt = 0;
239 Uart.state = STATE_AWAITING_START_BIT;
240 }
241 } else if (Uart.shiftReg == 0x000) {
242 // this is an EOF byte
243 LED_A_OFF(); // Finished receiving
244 Uart.state = STATE_UNSYNCD;
245 if (Uart.byteCnt != 0) {
246 return TRUE;
247 }
248 } else {
249 // this is an error
250 LED_A_OFF();
251 Uart.state = STATE_UNSYNCD;
252 }
253 }
254 break;
255
256 default:
257 LED_A_OFF();
258 Uart.state = STATE_UNSYNCD;
259 break;
260 }
261
262 return FALSE;
263 }
264
265
266 static void UartReset()
267 {
268 Uart.byteCntMax = MAX_FRAME_SIZE;
269 Uart.state = STATE_UNSYNCD;
270 Uart.byteCnt = 0;
271 Uart.bitCnt = 0;
272 Uart.posCnt = 0;
273 memset(Uart.output, 0x00, MAX_FRAME_SIZE);
274 }
275
276
277 static void UartInit(uint8_t *data)
278 {
279 Uart.output = data;
280 UartReset();
281 }
282
283
284 //-----------------------------------------------------------------------------
285 // Receive a command (from the reader to us, where we are the simulated tag),
286 // and store it in the given buffer, up to the given maximum length. Keeps
287 // spinning, waiting for a well-framed command, until either we get one
288 // (returns TRUE) or someone presses the pushbutton on the board (FALSE).
289 //
290 // Assume that we're called with the SSC (to the FPGA) and ADC path set
291 // correctly.
292 //-----------------------------------------------------------------------------
293 static int GetIso14443bCommandFromReader(uint8_t *received, uint16_t *len)
294 {
295 // Set FPGA mode to "simulated ISO 14443B tag", no modulation (listen
296 // only, since we are receiving, not transmitting).
297 // Signal field is off with the appropriate LED
298 LED_D_OFF();
299 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_NO_MODULATION);
300
301 // Now run a `software UART' on the stream of incoming samples.
302 UartInit(received);
303
304 for(;;) {
305 WDT_HIT();
306
307 if(BUTTON_PRESS()) return FALSE;
308
309 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
310 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
311 for(uint8_t mask = 0x80; mask != 0x00; mask >>= 1) {
312 if(Handle14443bUartBit(b & mask)) {
313 *len = Uart.byteCnt;
314 return TRUE;
315 }
316 }
317 }
318 }
319
320 return FALSE;
321 }
322
323 //-----------------------------------------------------------------------------
324 // Main loop of simulated tag: receive commands from reader, decide what
325 // response to send, and send it.
326 //-----------------------------------------------------------------------------
327 void SimulateIso14443bTag(void)
328 {
329 // the only commands we understand is WUPB, AFI=0, Select All, N=1:
330 static const uint8_t cmd1[] = { 0x05, 0x00, 0x08, 0x39, 0x73 }; // WUPB
331 // ... and REQB, AFI=0, Normal Request, N=1:
332 static const uint8_t cmd2[] = { 0x05, 0x00, 0x00, 0x71, 0xFF }; // REQB
333 // ... and HLTB
334 static const uint8_t cmd3[] = { 0x50, 0xff, 0xff, 0xff, 0xff }; // HLTB
335 // ... and ATTRIB
336 static const uint8_t cmd4[] = { 0x1D, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; // ATTRIB
337
338 // ... and we always respond with ATQB, PUPI = 820de174, Application Data = 0x20381922,
339 // supports only 106kBit/s in both directions, max frame size = 32Bytes,
340 // supports ISO14443-4, FWI=8 (77ms), NAD supported, CID not supported:
341 static const uint8_t response1[] = {
342 0x50, 0x82, 0x0d, 0xe1, 0x74, 0x20, 0x38, 0x19, 0x22,
343 0x00, 0x21, 0x85, 0x5e, 0xd7
344 };
345 // response to HLTB and ATTRIB
346 static const uint8_t response2[] = {0x00, 0x78, 0xF0};
347
348 uint8_t parity[MAX_PARITY_SIZE];
349
350 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
351
352 clear_trace();
353 set_tracing(TRUE);
354
355 const uint8_t *resp;
356 uint8_t *respCode;
357 uint16_t respLen, respCodeLen;
358
359 // allocate command receive buffer
360 BigBuf_free();
361 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
362
363 uint16_t len;
364 uint16_t cmdsRecvd = 0;
365
366 // prepare the (only one) tag answer:
367 CodeIso14443bAsTag(response1, sizeof(response1));
368 uint8_t *resp1Code = BigBuf_malloc(ToSendMax);
369 memcpy(resp1Code, ToSend, ToSendMax);
370 uint16_t resp1CodeLen = ToSendMax;
371
372 // prepare the (other) tag answer:
373 CodeIso14443bAsTag(response2, sizeof(response2));
374 uint8_t *resp2Code = BigBuf_malloc(ToSendMax);
375 memcpy(resp2Code, ToSend, ToSendMax);
376 uint16_t resp2CodeLen = ToSendMax;
377
378 // We need to listen to the high-frequency, peak-detected path.
379 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
380 FpgaSetupSsc();
381
382 cmdsRecvd = 0;
383
384 for(;;) {
385
386 if(!GetIso14443bCommandFromReader(receivedCmd, &len)) {
387 Dbprintf("button pressed, received %d commands", cmdsRecvd);
388 break;
389 }
390
391 if (tracing) {
392 LogTrace(receivedCmd, len, 0, 0, parity, TRUE);
393 }
394
395 // Good, look at the command now.
396 if ( (len == sizeof(cmd1) && memcmp(receivedCmd, cmd1, len) == 0)
397 || (len == sizeof(cmd2) && memcmp(receivedCmd, cmd2, len) == 0) ) {
398 resp = response1;
399 respLen = sizeof(response1);
400 respCode = resp1Code;
401 respCodeLen = resp1CodeLen;
402 } else if ( (len == sizeof(cmd3) && receivedCmd[0] == cmd3[0])
403 || (len == sizeof(cmd4) && receivedCmd[0] == cmd4[0]) ) {
404 resp = response2;
405 respLen = sizeof(response2);
406 respCode = resp2Code;
407 respCodeLen = resp2CodeLen;
408 } else {
409 Dbprintf("new cmd from reader: len=%d, cmdsRecvd=%d", len, cmdsRecvd);
410 // And print whether the CRC fails, just for good measure
411 uint8_t b1, b2;
412 if (len >= 3){ // if crc exists
413 ComputeCrc14443(CRC_14443_B, receivedCmd, len-2, &b1, &b2);
414 if(b1 != receivedCmd[len-2] || b2 != receivedCmd[len-1]) {
415 // Not so good, try again.
416 DbpString("+++CRC fail");
417
418 } else {
419 DbpString("CRC passes");
420 }
421 }
422 //get rid of compiler warning
423 respCodeLen = 0;
424 resp = response1;
425 respLen = 0;
426 respCode = resp1Code;
427 //don't crash at new command just wait and see if reader will send other new cmds.
428 //break;
429 }
430
431 cmdsRecvd++;
432
433 if(cmdsRecvd > 0x30) {
434 DbpString("many commands later...");
435 break;
436 }
437
438 if(respCodeLen <= 0) continue;
439
440 // Modulate BPSK
441 // Signal field is off with the appropriate LED
442 LED_D_OFF();
443 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_BPSK);
444 AT91C_BASE_SSC->SSC_THR = 0xff;
445 FpgaSetupSsc();
446
447 uint8_t c;
448 // clear receiving shift register and holding register
449 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
450 c = AT91C_BASE_SSC->SSC_RHR; (void) c;
451 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
452 c = AT91C_BASE_SSC->SSC_RHR; (void) c;
453
454 // Clear TXRDY:
455 AT91C_BASE_SSC->SSC_THR = 0x00;
456
457 // Transmit the response.
458 uint16_t FpgaSendQueueDelay = 0;
459 uint16_t i = 0;
460 for(;i < respCodeLen; ) {
461 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
462 AT91C_BASE_SSC->SSC_THR = respCode[i++];
463 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
464 }
465 if(BUTTON_PRESS()) break;
466 }
467
468 // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN again:
469 uint8_t fpga_queued_bits = FpgaSendQueueDelay >> 3;
470 for (i = 0; i <= fpga_queued_bits/8 + 1; ) {
471 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
472 AT91C_BASE_SSC->SSC_THR = 0x00;
473 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
474 i++;
475 }
476 }
477
478 // trace the response:
479 if (tracing) LogTrace(resp, respLen, 0, 0, parity, FALSE);
480 }
481 FpgaDisableSscDma();
482 }
483
484 //=============================================================================
485 // An ISO 14443 Type B reader. We take layer two commands, code them
486 // appropriately, and then send them to the tag. We then listen for the
487 // tag's response, which we leave in the buffer to be demodulated on the
488 // PC side.
489 //=============================================================================
490
491 static struct {
492 enum {
493 DEMOD_UNSYNCD,
494 DEMOD_PHASE_REF_TRAINING,
495 DEMOD_AWAITING_FALLING_EDGE_OF_SOF,
496 DEMOD_GOT_FALLING_EDGE_OF_SOF,
497 DEMOD_AWAITING_START_BIT,
498 DEMOD_RECEIVING_DATA
499 } state;
500 int bitCount;
501 int posCount;
502 int thisBit;
503 /* this had been used to add RSSI (Received Signal Strength Indication) to traces. Currently not implemented.
504 int metric;
505 int metricN;
506 */
507 uint16_t shiftReg;
508 uint8_t *output;
509 int len;
510 int sumI;
511 int sumQ;
512 } Demod;
513
514 /*
515 * Handles reception of a bit from the tag
516 *
517 * This function is called 2 times per bit (every 4 subcarrier cycles).
518 * Subcarrier frequency fs is 848kHz, 1/fs = 1,18us, i.e. function is called every 4,72us
519 *
520 * LED handling:
521 * LED C -> ON once we have received the SOF and are expecting the rest.
522 * LED C -> OFF once we have received EOF or are unsynced
523 *
524 * Returns: true if we received a EOF
525 * false if we are still waiting for some more
526 *
527 */
528 #define abs(x) ( ((x)<0) ? -(x) : (x) )
529 static RAMFUNC int Handle14443bSamplesDemod(int ci, int cq)
530 {
531 int v = 0;
532 int ai = abs(ci);
533 int aq = abs(cq);
534 int halfci = (ai >> 1);
535 int halfcq = (aq >> 1);
536
537 // The soft decision on the bit uses an estimate of just the
538 // quadrant of the reference angle, not the exact angle.
539 #define MAKE_SOFT_DECISION() { \
540 if(Demod.sumI > 0) { \
541 v = ci; \
542 } else { \
543 v = -ci; \
544 } \
545 if(Demod.sumQ > 0) { \
546 v += cq; \
547 } else { \
548 v -= cq; \
549 } \
550 }
551
552 #define SUBCARRIER_DETECT_THRESHOLD 8
553
554 // Subcarrier amplitude v = sqrt(ci^2 + cq^2), approximated here by max(abs(ci),abs(cq)) + 1/2*min(abs(ci),abs(cq)))
555 #define CHECK_FOR_SUBCARRIER() { \
556 v = MAX(ai, aq) + MIN(halfci, halfcq); \
557 }
558
559
560 switch(Demod.state) {
561 case DEMOD_UNSYNCD:
562 CHECK_FOR_SUBCARRIER();
563 if(v > SUBCARRIER_DETECT_THRESHOLD) { // subcarrier detected
564 Demod.state = DEMOD_PHASE_REF_TRAINING;
565 Demod.sumI = ci;
566 Demod.sumQ = cq;
567 Demod.posCount = 1;
568 }
569 break;
570
571 case DEMOD_PHASE_REF_TRAINING:
572 if(Demod.posCount < 8) {
573 //if(Demod.posCount < 10*2) {
574 CHECK_FOR_SUBCARRIER();
575 if (v > SUBCARRIER_DETECT_THRESHOLD) {
576 // set the reference phase (will code a logic '1') by averaging over 32 1/fs.
577 // note: synchronization time > 80 1/fs
578 Demod.sumI += ci;
579 Demod.sumQ += cq;
580 Demod.posCount++;
581 } else { // subcarrier lost
582 Demod.state = DEMOD_UNSYNCD;
583 }
584 } else {
585 Demod.state = DEMOD_AWAITING_FALLING_EDGE_OF_SOF;
586 }
587 break;
588
589 case DEMOD_AWAITING_FALLING_EDGE_OF_SOF:
590 MAKE_SOFT_DECISION();
591 //Dbprintf("ICE: %d %d %d %d %d", v, Demod.sumI, Demod.sumQ, ci, cq );
592 if(v <= 0) { // logic '0' detected
593 Demod.state = DEMOD_GOT_FALLING_EDGE_OF_SOF;
594 Demod.posCount = 0; // start of SOF sequence
595 } else {
596 if(Demod.posCount > 25*2) { // maximum length of TR1 = 200 1/fs
597 Demod.state = DEMOD_UNSYNCD;
598 }
599 }
600 Demod.posCount++;
601 break;
602
603 case DEMOD_GOT_FALLING_EDGE_OF_SOF:
604 Demod.posCount++;
605 MAKE_SOFT_DECISION();
606 if(v > 0) {
607 if(Demod.posCount < 10*2) { // low phase of SOF too short (< 9 etu). Note: spec is >= 10, but FPGA tends to "smear" edges
608 Demod.state = DEMOD_UNSYNCD;
609 } else {
610 LED_C_ON(); // Got SOF
611 Demod.state = DEMOD_AWAITING_START_BIT;
612 Demod.posCount = 0;
613 Demod.len = 0;
614 /* this had been used to add RSSI (Received Signal Strength Indication) to traces. Currently not implemented.
615 Demod.metricN = 0;
616 Demod.metric = 0;
617 */
618 }
619 } else {
620 if(Demod.posCount > 13*2) { // low phase of SOF too long (> 12 etu)
621 Demod.state = DEMOD_UNSYNCD;
622 LED_C_OFF();
623 }
624 }
625 break;
626
627 case DEMOD_AWAITING_START_BIT:
628 Demod.posCount++;
629 MAKE_SOFT_DECISION();
630 if(v > 0) {
631 if(Demod.posCount > 3*2) { // max 19us between characters = 16 1/fs, max 3 etu after low phase of SOF = 24 1/fs
632 Demod.state = DEMOD_UNSYNCD;
633 LED_C_OFF();
634 }
635 } else { // start bit detected
636 Demod.bitCount = 0;
637 Demod.posCount = 1; // this was the first half
638 Demod.thisBit = v;
639 Demod.shiftReg = 0;
640 Demod.state = DEMOD_RECEIVING_DATA;
641 }
642 break;
643
644 case DEMOD_RECEIVING_DATA:
645 MAKE_SOFT_DECISION();
646 if(Demod.posCount == 0) { // first half of bit
647 Demod.thisBit = v;
648 Demod.posCount = 1;
649 } else { // second half of bit
650 Demod.thisBit += v;
651
652 /* this had been used to add RSSI (Received Signal Strength Indication) to traces. Currently not implemented.
653 if(Demod.thisBit > 0) {
654 Demod.metric += Demod.thisBit;
655 } else {
656 Demod.metric -= Demod.thisBit;
657 }
658 (Demod.metricN)++;
659 */
660
661 Demod.shiftReg >>= 1;
662 if(Demod.thisBit > 0) { // logic '1'
663 Demod.shiftReg |= 0x200;
664 }
665
666 Demod.bitCount++;
667 if(Demod.bitCount == 10) {
668 uint16_t s = Demod.shiftReg;
669 if((s & 0x200) && !(s & 0x001)) { // stop bit == '1', start bit == '0'
670 uint8_t b = (s >> 1);
671 Demod.output[Demod.len] = b;
672 Demod.len++;
673 Demod.state = DEMOD_AWAITING_START_BIT;
674 } else {
675 Demod.state = DEMOD_UNSYNCD;
676 LED_C_OFF();
677 if(s == 0x000) {
678 // This is EOF (start, stop and all data bits == '0'
679 return TRUE;
680 }
681 }
682 }
683 Demod.posCount = 0;
684 }
685 break;
686
687 default:
688 Demod.state = DEMOD_UNSYNCD;
689 LED_C_OFF();
690 break;
691 }
692 return FALSE;
693 }
694
695
696 static void DemodReset()
697 {
698 // Clear out the state of the "UART" that receives from the tag.
699 Demod.len = 0;
700 Demod.state = DEMOD_UNSYNCD;
701 Demod.posCount = 0;
702 Demod.sumI = 0;
703 Demod.sumQ = 0;
704 Demod.bitCount = 0;
705 Demod.thisBit = 0;
706 Demod.shiftReg = 0;
707 memset(Demod.output, 0x00, MAX_FRAME_SIZE);
708 }
709
710
711 static void DemodInit(uint8_t *data)
712 {
713 Demod.output = data;
714 DemodReset();
715 }
716
717
718 /*
719 * Demodulate the samples we received from the tag, also log to tracebuffer
720 * quiet: set to 'TRUE' to disable debug output
721 */
722 static void GetSamplesFor14443bDemod(int n, bool quiet)
723 {
724 int max = 0;
725 bool gotFrame = FALSE;
726 int lastRxCounter, ci, cq, samples = 0;
727
728 // Allocate memory from BigBuf for some buffers
729 // free all previous allocations first
730 BigBuf_free();
731
732 // And put the FPGA in the appropriate mode
733 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ);
734
735 // The response (tag -> reader) that we're receiving.
736 // Set up the demodulator for tag -> reader responses.
737 DemodInit(BigBuf_malloc(MAX_FRAME_SIZE));
738
739 // The DMA buffer, used to stream samples from the FPGA
740 int8_t *dmaBuf = (int8_t*) BigBuf_malloc(ISO14443B_DMA_BUFFER_SIZE);
741
742 // Setup and start DMA.
743 FpgaSetupSscDma((uint8_t*) dmaBuf, ISO14443B_DMA_BUFFER_SIZE);
744
745 int8_t *upTo = dmaBuf;
746 lastRxCounter = ISO14443B_DMA_BUFFER_SIZE;
747
748 // Signal field is ON with the appropriate LED:
749 LED_D_ON();
750 for(;;) {
751 int behindBy = lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR;
752 if(behindBy > max) max = behindBy;
753
754 while(((lastRxCounter-AT91C_BASE_PDC_SSC->PDC_RCR) & (ISO14443B_DMA_BUFFER_SIZE-1)) > 2) {
755 ci = upTo[0];
756 cq = upTo[1];
757 upTo += 2;
758 if(upTo >= dmaBuf + ISO14443B_DMA_BUFFER_SIZE) {
759 upTo = dmaBuf;
760 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo;
761 AT91C_BASE_PDC_SSC->PDC_RNCR = ISO14443B_DMA_BUFFER_SIZE;
762 }
763 lastRxCounter -= 2;
764 if(lastRxCounter <= 0) {
765 lastRxCounter = ISO14443B_DMA_BUFFER_SIZE;
766 }
767
768 samples += 2;
769
770 //
771 gotFrame = Handle14443bSamplesDemod(ci , cq );
772 if ( gotFrame )
773 break;
774 }
775
776 if(samples > n || gotFrame) {
777 break;
778 }
779 }
780
781 AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;
782
783 if (!quiet && Demod.len == 0) {
784 Dbprintf("max behindby = %d, samples = %d, gotFrame = %d, Demod.len = %d, Demod.sumI = %d, Demod.sumQ = %d",
785 max,
786 samples,
787 gotFrame,
788 Demod.len,
789 Demod.sumI,
790 Demod.sumQ
791 );
792 }
793
794 //Tracing
795 if (tracing && Demod.len > 0) {
796 uint8_t parity[MAX_PARITY_SIZE];
797 LogTrace(Demod.output, Demod.len, 0, 0, parity, FALSE);
798 }
799 }
800
801
802 //-----------------------------------------------------------------------------
803 // Transmit the command (to the tag) that was placed in ToSend[].
804 //-----------------------------------------------------------------------------
805 static void TransmitFor14443b(void)
806 {
807 int c;
808
809 FpgaSetupSsc();
810
811 while(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
812 AT91C_BASE_SSC->SSC_THR = 0xff;
813 }
814
815 // Signal field is ON with the appropriate Red LED
816 LED_D_ON();
817 // Signal we are transmitting with the Green LED
818 LED_B_ON();
819 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
820
821 for(c = 0; c < 10;) {
822 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
823 AT91C_BASE_SSC->SSC_THR = 0xff;
824 c++;
825 }
826 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
827 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
828 (void)r;
829 }
830 WDT_HIT();
831 }
832
833 c = 0;
834 for(;;) {
835 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
836 AT91C_BASE_SSC->SSC_THR = ToSend[c];
837 c++;
838 if(c >= ToSendMax) {
839 break;
840 }
841 }
842 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
843 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
844 (void)r;
845 }
846 WDT_HIT();
847 }
848 LED_B_OFF(); // Finished sending
849 }
850
851
852 //-----------------------------------------------------------------------------
853 // Code a layer 2 command (string of octets, including CRC) into ToSend[],
854 // so that it is ready to transmit to the tag using TransmitFor14443b().
855 //-----------------------------------------------------------------------------
856 static void CodeIso14443bAsReader(const uint8_t *cmd, int len)
857 {
858 int i, j;
859 uint8_t b;
860
861 ToSendReset();
862
863 // Establish initial reference level
864 for(i = 0; i < 40; i++) {
865 ToSendStuffBit(1);
866 }
867 // Send SOF
868 for(i = 0; i < 11; i++) {
869 ToSendStuffBit(0);
870 }
871
872 for(i = 0; i < len; i++) {
873 // Stop bits/EGT
874 ToSendStuffBit(1);
875 ToSendStuffBit(1);
876 // Start bit
877 ToSendStuffBit(0);
878 // Data bits
879 b = cmd[i];
880 for(j = 0; j < 8; j++) {
881 if(b & 1) {
882 ToSendStuffBit(1);
883 } else {
884 ToSendStuffBit(0);
885 }
886 b >>= 1;
887 }
888 }
889 // Send EOF
890 ToSendStuffBit(1);
891 for(i = 0; i < 11; i++) {
892 ToSendStuffBit(0);
893 }
894 for(i = 0; i < 8; i++) {
895 ToSendStuffBit(1);
896 }
897
898 // And then a little more, to make sure that the last character makes
899 // it out before we switch to rx mode.
900 for(i = 0; i < 10; i++) {
901 ToSendStuffBit(1);
902 }
903
904 // Convert from last character reference to length
905 ToSendMax++;
906 }
907
908
909 /**
910 Convenience function to encode, transmit and trace iso 14443b comms
911 **/
912 static void CodeAndTransmit14443bAsReader(const uint8_t *cmd, int len)
913 {
914 CodeIso14443bAsReader(cmd, len);
915 TransmitFor14443b();
916 if (tracing) {
917 uint8_t parity[MAX_PARITY_SIZE];
918 LogTrace(cmd,len, 0, 0, parity, TRUE);
919 }
920 }
921
922 /* Sends an APDU to the tag
923 * TODO: check CRC and preamble
924 */
925 int iso14443b_apdu(uint8_t const *message, size_t message_length, uint8_t *response)
926 {
927 uint8_t message_frame[message_length + 4];
928 // PCB
929 message_frame[0] = 0x0A | pcb_blocknum;
930 pcb_blocknum ^= 1;
931 // CID
932 message_frame[1] = 0;
933 // INF
934 memcpy(message_frame + 2, message, message_length);
935 // EDC (CRC)
936 ComputeCrc14443(CRC_14443_B, message_frame, message_length + 2, &message_frame[message_length + 2], &message_frame[message_length + 3]);
937 // send
938 CodeAndTransmit14443bAsReader(message_frame, message_length + 4);
939 // get response
940 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT*100, TRUE);
941 if(Demod.len < 3)
942 {
943 return 0;
944 }
945 // TODO: Check CRC
946 // copy response contents
947 if(response != NULL)
948 {
949 memcpy(response, Demod.output, Demod.len);
950 }
951 return Demod.len;
952 }
953
954 /* Perform the ISO 14443 B Card Selection procedure
955 * Currently does NOT do any collision handling.
956 * It expects 0-1 cards in the device's range.
957 * TODO: Support multiple cards (perform anticollision)
958 * TODO: Verify CRC checksums
959 */
960 int iso14443b_select_card()
961 {
962 // WUPB command (including CRC)
963 // Note: WUPB wakes up all tags, REQB doesn't wake up tags in HALT state
964 static const uint8_t wupb[] = { 0x05, 0x00, 0x08, 0x39, 0x73 };
965 // ATTRIB command (with space for CRC)
966 uint8_t attrib[] = { 0x1D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00};
967
968 // first, wake up the tag
969 CodeAndTransmit14443bAsReader(wupb, sizeof(wupb));
970 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
971 // ATQB too short?
972 if (Demod.len < 14)
973 {
974 return 2;
975 }
976
977 // select the tag
978 // copy the PUPI to ATTRIB
979 memcpy(attrib + 1, Demod.output + 1, 4);
980 /* copy the protocol info from ATQB (Protocol Info -> Protocol_Type) into
981 ATTRIB (Param 3) */
982 attrib[7] = Demod.output[10] & 0x0F;
983 ComputeCrc14443(CRC_14443_B, attrib, 9, attrib + 9, attrib + 10);
984 CodeAndTransmit14443bAsReader(attrib, sizeof(attrib));
985 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
986 // Answer to ATTRIB too short?
987 if(Demod.len < 3)
988 {
989 return 2;
990 }
991 // reset PCB block number
992 pcb_blocknum = 0;
993 return 1;
994 }
995
996 // Set up ISO 14443 Type B communication (similar to iso14443a_setup)
997 void iso14443b_setup() {
998
999 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1000
1001 BigBuf_free();
1002 // Set up the synchronous serial port
1003 FpgaSetupSsc();
1004 // connect Demodulated Signal to ADC:
1005 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1006
1007 // Signal field is on with the appropriate LED
1008 LED_D_ON();
1009 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
1010
1011 //SpinDelay(100);
1012
1013 // Start the timer
1014 //StartCountSspClk();
1015
1016 DemodReset();
1017 UartReset();
1018 }
1019
1020 //-----------------------------------------------------------------------------
1021 // Read a SRI512 ISO 14443B tag.
1022 //
1023 // SRI512 tags are just simple memory tags, here we're looking at making a dump
1024 // of the contents of the memory. No anticollision algorithm is done, we assume
1025 // we have a single tag in the field.
1026 //
1027 // I tried to be systematic and check every answer of the tag, every CRC, etc...
1028 //-----------------------------------------------------------------------------
1029 void ReadSTMemoryIso14443b(uint32_t dwLast)
1030 {
1031 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1032 BigBuf_free();
1033
1034 clear_trace();
1035 set_tracing(TRUE);
1036
1037 uint8_t i = 0x00;
1038
1039 // Make sure that we start from off, since the tags are stateful;
1040 // confusing things will happen if we don't reset them between reads.
1041 LED_D_OFF();
1042 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1043 SpinDelay(200);
1044
1045 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1046 FpgaSetupSsc();
1047
1048 // Now give it time to spin up.
1049 // Signal field is on with the appropriate LED
1050 LED_D_ON();
1051 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ);
1052 SpinDelay(200);
1053
1054 // First command: wake up the tag using the INITIATE command
1055 uint8_t cmd1[] = {0x06, 0x00, 0x97, 0x5b};
1056 CodeAndTransmit14443bAsReader(cmd1, sizeof(cmd1));
1057 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
1058
1059 if (Demod.len == 0) {
1060 DbpString("No response from tag");
1061 return;
1062 } else {
1063 Dbprintf("Randomly generated Chip ID (+ 2 byte CRC): %02x %02x %02x",
1064 Demod.output[0], Demod.output[1], Demod.output[2]);
1065 }
1066
1067 // There is a response, SELECT the uid
1068 DbpString("Now SELECT tag:");
1069 cmd1[0] = 0x0E; // 0x0E is SELECT
1070 cmd1[1] = Demod.output[0];
1071 ComputeCrc14443(CRC_14443_B, cmd1, 2, &cmd1[2], &cmd1[3]);
1072 CodeAndTransmit14443bAsReader(cmd1, sizeof(cmd1));
1073 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
1074 if (Demod.len != 3) {
1075 Dbprintf("Expected 3 bytes from tag, got %d", Demod.len);
1076 return;
1077 }
1078 // Check the CRC of the answer:
1079 ComputeCrc14443(CRC_14443_B, Demod.output, 1 , &cmd1[2], &cmd1[3]);
1080 if(cmd1[2] != Demod.output[1] || cmd1[3] != Demod.output[2]) {
1081 DbpString("CRC Error reading select response.");
1082 return;
1083 }
1084 // Check response from the tag: should be the same UID as the command we just sent:
1085 if (cmd1[1] != Demod.output[0]) {
1086 Dbprintf("Bad response to SELECT from Tag, aborting: %02x %02x", cmd1[1], Demod.output[0]);
1087 return;
1088 }
1089
1090 // Tag is now selected,
1091 // First get the tag's UID:
1092 cmd1[0] = 0x0B;
1093 ComputeCrc14443(CRC_14443_B, cmd1, 1 , &cmd1[1], &cmd1[2]);
1094 CodeAndTransmit14443bAsReader(cmd1, 3); // Only first three bytes for this one
1095 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
1096 if (Demod.len != 10) {
1097 Dbprintf("Expected 10 bytes from tag, got %d", Demod.len);
1098 return;
1099 }
1100 // The check the CRC of the answer (use cmd1 as temporary variable):
1101 ComputeCrc14443(CRC_14443_B, Demod.output, 8, &cmd1[2], &cmd1[3]);
1102 if(cmd1[2] != Demod.output[8] || cmd1[3] != Demod.output[9]) {
1103 Dbprintf("CRC Error reading block! Expected: %04x got: %04x",
1104 (cmd1[2]<<8)+cmd1[3], (Demod.output[8]<<8)+Demod.output[9]);
1105 // Do not return;, let's go on... (we should retry, maybe ?)
1106 }
1107 Dbprintf("Tag UID (64 bits): %08x %08x",
1108 (Demod.output[7]<<24) + (Demod.output[6]<<16) + (Demod.output[5]<<8) + Demod.output[4],
1109 (Demod.output[3]<<24) + (Demod.output[2]<<16) + (Demod.output[1]<<8) + Demod.output[0]);
1110
1111 // Now loop to read all 16 blocks, address from 0 to last block
1112 Dbprintf("Tag memory dump, block 0 to %d", dwLast);
1113 cmd1[0] = 0x08;
1114 i = 0x00;
1115 dwLast++;
1116 for (;;) {
1117 if (i == dwLast) {
1118 DbpString("System area block (0xff):");
1119 i = 0xff;
1120 }
1121 cmd1[1] = i;
1122 ComputeCrc14443(CRC_14443_B, cmd1, 2, &cmd1[2], &cmd1[3]);
1123 CodeAndTransmit14443bAsReader(cmd1, sizeof(cmd1));
1124 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
1125 if (Demod.len != 6) { // Check if we got an answer from the tag
1126 DbpString("Expected 6 bytes from tag, got less...");
1127 return;
1128 }
1129 // The check the CRC of the answer (use cmd1 as temporary variable):
1130 ComputeCrc14443(CRC_14443_B, Demod.output, 4, &cmd1[2], &cmd1[3]);
1131 if(cmd1[2] != Demod.output[4] || cmd1[3] != Demod.output[5]) {
1132 Dbprintf("CRC Error reading block! Expected: %04x got: %04x",
1133 (cmd1[2]<<8)+cmd1[3], (Demod.output[4]<<8)+Demod.output[5]);
1134 // Do not return;, let's go on... (we should retry, maybe ?)
1135 }
1136 // Now print out the memory location:
1137 Dbprintf("Address=%02x, Contents=%08x, CRC=%04x", i,
1138 (Demod.output[3]<<24) + (Demod.output[2]<<16) + (Demod.output[1]<<8) + Demod.output[0],
1139 (Demod.output[4]<<8)+Demod.output[5]);
1140 if (i == 0xff) {
1141 break;
1142 }
1143 i++;
1144 }
1145 }
1146
1147
1148 //=============================================================================
1149 // Finally, the `sniffer' combines elements from both the reader and
1150 // simulated tag, to show both sides of the conversation.
1151 //=============================================================================
1152
1153 //-----------------------------------------------------------------------------
1154 // Record the sequence of commands sent by the reader to the tag, with
1155 // triggering so that we start recording at the point that the tag is moved
1156 // near the reader.
1157 //-----------------------------------------------------------------------------
1158 /*
1159 * Memory usage for this function, (within BigBuf)
1160 * Last Received command (reader->tag) - MAX_FRAME_SIZE
1161 * Last Received command (tag->reader) - MAX_FRAME_SIZE
1162 * DMA Buffer - ISO14443B_DMA_BUFFER_SIZE
1163 * Demodulated samples received - all the rest
1164 */
1165 void RAMFUNC SnoopIso14443b(void)
1166 {
1167 // We won't start recording the frames that we acquire until we trigger;
1168 // a good trigger condition to get started is probably when we see a
1169 // response from the tag.
1170 int triggered = TRUE; // TODO: set and evaluate trigger condition
1171
1172 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1173 BigBuf_free();
1174
1175 clear_trace();
1176 set_tracing(TRUE);
1177
1178 // The DMA buffer, used to stream samples from the FPGA
1179 int8_t *dmaBuf = (int8_t*) BigBuf_malloc(ISO14443B_DMA_BUFFER_SIZE);
1180 int lastRxCounter;
1181 int8_t *upTo;
1182 int ci, cq;
1183 int maxBehindBy = 0;
1184
1185 // Count of samples received so far, so that we can include timing
1186 // information in the trace buffer.
1187 int samples = 0;
1188
1189 DemodInit(BigBuf_malloc(MAX_FRAME_SIZE));
1190 UartInit(BigBuf_malloc(MAX_FRAME_SIZE));
1191
1192 // Print some debug information about the buffer sizes
1193 Dbprintf("Snooping buffers initialized:");
1194 Dbprintf(" Trace: %i bytes", BigBuf_max_traceLen());
1195 Dbprintf(" Reader -> tag: %i bytes", MAX_FRAME_SIZE);
1196 Dbprintf(" tag -> Reader: %i bytes", MAX_FRAME_SIZE);
1197 Dbprintf(" DMA: %i bytes", ISO14443B_DMA_BUFFER_SIZE);
1198
1199 // Signal field is off, no reader signal, no tag signal
1200 LEDsoff();
1201
1202 // And put the FPGA in the appropriate mode
1203 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ | FPGA_HF_READER_RX_XCORR_SNOOP);
1204 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1205
1206 // Setup for the DMA.
1207 FpgaSetupSsc();
1208 upTo = dmaBuf;
1209 lastRxCounter = ISO14443B_DMA_BUFFER_SIZE;
1210 FpgaSetupSscDma((uint8_t*) dmaBuf, ISO14443B_DMA_BUFFER_SIZE);
1211 uint8_t parity[MAX_PARITY_SIZE];
1212
1213 bool TagIsActive = FALSE;
1214 bool ReaderIsActive = FALSE;
1215
1216 // And now we loop, receiving samples.
1217 for(;;) {
1218 int behindBy = (lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR) &
1219 (ISO14443B_DMA_BUFFER_SIZE-1);
1220 if(behindBy > maxBehindBy) {
1221 maxBehindBy = behindBy;
1222 }
1223
1224 if(behindBy < 2) continue;
1225
1226 ci = upTo[0];
1227 cq = upTo[1];
1228 upTo += 2;
1229 lastRxCounter -= 2;
1230 if(upTo >= dmaBuf + ISO14443B_DMA_BUFFER_SIZE) {
1231 upTo = dmaBuf;
1232 lastRxCounter += ISO14443B_DMA_BUFFER_SIZE;
1233 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
1234 AT91C_BASE_PDC_SSC->PDC_RNCR = ISO14443B_DMA_BUFFER_SIZE;
1235 WDT_HIT();
1236 if(behindBy > (9*ISO14443B_DMA_BUFFER_SIZE/10)) { // TODO: understand whether we can increase/decrease as we want or not?
1237 Dbprintf("blew circular buffer! behindBy=%d", behindBy);
1238 break;
1239 }
1240 if(!tracing) {
1241 DbpString("Reached trace limit");
1242 break;
1243 }
1244 if(BUTTON_PRESS()) {
1245 DbpString("cancelled");
1246 break;
1247 }
1248 }
1249
1250 samples += 2;
1251
1252 if (!TagIsActive) { // no need to try decoding reader data if the tag is sending
1253 if(Handle14443bUartBit(ci & 0x01)) {
1254 if(triggered && tracing) {
1255 LogTrace(Uart.output, Uart.byteCnt, samples, samples, parity, TRUE);
1256 }
1257 /* And ready to receive another command. */
1258 UartReset();
1259 /* And also reset the demod code, which might have been */
1260 /* false-triggered by the commands from the reader. */
1261 DemodReset();
1262 }
1263 if(Handle14443bUartBit(cq & 0x01)) {
1264 if(triggered && tracing) {
1265 LogTrace(Uart.output, Uart.byteCnt, samples, samples, parity, TRUE);
1266 }
1267 /* And ready to receive another command. */
1268 UartReset();
1269 /* And also reset the demod code, which might have been */
1270 /* false-triggered by the commands from the reader. */
1271 DemodReset();
1272 }
1273 ReaderIsActive = (Uart.state > STATE_GOT_FALLING_EDGE_OF_SOF);
1274 }
1275
1276 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
1277 // is this | 0x01 the error? & 0xfe in https://github.com/Proxmark/proxmark3/issues/103
1278 if(Handle14443bSamplesDemod(ci & 0xfe, cq & 0xfe)) {
1279
1280 //Use samples as a time measurement
1281 if(tracing)
1282 {
1283 //uint8_t parity[MAX_PARITY_SIZE];
1284 LogTrace(Demod.output, Demod.len, samples, samples, parity, FALSE);
1285 }
1286 triggered = TRUE;
1287
1288 // And ready to receive another response.
1289 DemodReset();
1290 }
1291 TagIsActive = (Demod.state > DEMOD_GOT_FALLING_EDGE_OF_SOF);
1292 }
1293
1294 }
1295
1296 FpgaDisableSscDma();
1297 LEDsoff();
1298 AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;
1299 DbpString("Snoop statistics:");
1300 Dbprintf(" Max behind by: %i", maxBehindBy);
1301 Dbprintf(" Uart State: %x", Uart.state);
1302 Dbprintf(" Uart ByteCnt: %i", Uart.byteCnt);
1303 Dbprintf(" Uart ByteCntMax: %i", Uart.byteCntMax);
1304 Dbprintf(" Trace length: %i", BigBuf_get_traceLen());
1305 }
1306
1307
1308 /*
1309 * Send raw command to tag ISO14443B
1310 * @Input
1311 * datalen len of buffer data
1312 * recv bool when true wait for data from tag and send to client
1313 * powerfield bool leave the field on when true
1314 * data buffer with byte to send
1315 *
1316 * @Output
1317 * none
1318 *
1319 */
1320 void SendRawCommand14443B(uint32_t datalen, uint32_t recv, uint8_t powerfield, uint8_t data[])
1321 {
1322 iso14443b_setup();
1323
1324 if ( datalen == 0 && recv == 0 && powerfield == 0){
1325
1326 } else {
1327 set_tracing(TRUE);
1328 CodeAndTransmit14443bAsReader(data, datalen);
1329 }
1330
1331 if(recv) {
1332 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, FALSE);
1333 uint16_t iLen = MIN(Demod.len, USB_CMD_DATA_SIZE);
1334 cmd_send(CMD_ACK, iLen, 0, 0, Demod.output, iLen);
1335 }
1336
1337 if(!powerfield) {
1338 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1339 FpgaDisableSscDma();
1340 LED_D_OFF();
1341 }
1342 }
1343
Proxmark3 GIT tracking
Impressum, Datenschutz