cvs.zerfleddert.de Git - proxmark3-svn/blob - fpga/hi_read_rx_xcorr.v

   1 //-----------------------------------------------------------------------------
   2 //
   3 // Jonathan Westhues, April 2006
   4 //-----------------------------------------------------------------------------
   5
   6 module hi_read_rx_xcorr(
   7     pck0, ck_1356meg, ck_1356megb,
   8     pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
   9     adc_d, adc_clk,
  10     ssp_frame, ssp_din, ssp_dout, ssp_clk,
  11     cross_hi, cross_lo,
  12     dbg,
  13     xcorr_is_848, snoop
  14 );
  15     input pck0, ck_1356meg, ck_1356megb;
  16     output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
  17     input [7:0] adc_d;
  18     output adc_clk;
  19     input ssp_dout;
  20     output ssp_frame, ssp_din, ssp_clk;
  21     input cross_hi, cross_lo;
  22     output dbg;
  23     input xcorr_is_848, snoop;
  24
  25 // Carrier is steady on through this, unless we're snooping.
  26 assign pwr_hi = ck_1356megb & (~snoop);
  27 assign pwr_oe1 = 1'b0;
  28 assign pwr_oe2 = 1'b0;
  29 assign pwr_oe3 = 1'b0;
  30 assign pwr_oe4 = 1'b0;
  31
  32 reg ssp_clk;
  33 reg ssp_frame;
  34
  35 reg fc_div_2;
  36 always @(posedge ck_1356meg)
  37     fc_div_2 = ~fc_div_2;
  38
  39 reg adc_clk;
  40
  41 always @(xcorr_is_848 or fc_div_2 or ck_1356meg)
  42     if(xcorr_is_848)
  43         // The subcarrier frequency is fc/16; we will sample at fc, so that
  44         // means the subcarrier is 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 ...
  45         adc_clk <= ck_1356meg;
  46     else
  47         // The subcarrier frequency is fc/32; we will sample at fc/2, and
  48         // the subcarrier will look identical.
  49         adc_clk <= fc_div_2;
  50
  51 // When we're a reader, we just need to do the BPSK demod; but when we're an
  52 // eavesdropper, we also need to pick out the commands sent by the reader,
  53 // using AM. Do this the same way that we do it for the simulated tag.
  54 reg after_hysteresis, after_hysteresis_prev;
  55 reg [11:0] has_been_low_for;
  56 always @(negedge adc_clk)
  57 begin
  58     if(& adc_d[7:0]) after_hysteresis <= 1'b1;
  59     else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;
  60
  61     if(after_hysteresis)
  62     begin
  63         has_been_low_for <= 7'b0;
  64     end
  65     else
  66     begin
  67         if(has_been_low_for == 12'd4095)
  68         begin
  69             has_been_low_for <= 12'd0;
  70             after_hysteresis <= 1'b1;
  71         end
  72         else
  73             has_been_low_for <= has_been_low_for + 1;
  74     end
  75 end
  76
  77 // Let us report a correlation every 4 subcarrier cycles, or 4*16 samples,
  78 // so we need a 6-bit counter.
  79 reg [5:0] corr_i_cnt;
  80 reg [5:0] corr_q_cnt;
  81 // And a couple of registers in which to accumulate the correlations.
  82 reg signed [15:0] corr_i_accum;
  83 reg signed [15:0] corr_q_accum;
  84 reg signed [7:0] corr_i_out;
  85 reg signed [7:0] corr_q_out;
  86
  87 // ADC data appears on the rising edge, so sample it on the falling edge
  88 always @(negedge adc_clk)
  89 begin
  90     // These are the correlators: we correlate against in-phase and quadrature
  91     // versions of our reference signal, and keep the (signed) result to
  92     // send out later over the SSP.
  93     if(corr_i_cnt == 7'd63)
  94     begin
  95         if(snoop)
  96         begin
  97             corr_i_out <= {corr_i_accum[12:6], after_hysteresis_prev};
  98             corr_q_out <= {corr_q_accum[12:6], after_hysteresis};
  99         end
 100         else
 101         begin
 102             // Only correlations need to be delivered.
 103             corr_i_out <= corr_i_accum[13:6];
 104             corr_q_out <= corr_q_accum[13:6];
 105         end
 106
 107         corr_i_accum <= adc_d;
 108         corr_q_accum <= adc_d;
 109         corr_q_cnt <= 4;
 110         corr_i_cnt <= 0;
 111     end
 112     else
 113     begin
 114         if(corr_i_cnt[3])
 115             corr_i_accum <= corr_i_accum - adc_d;
 116         else
 117             corr_i_accum <= corr_i_accum + adc_d;
 118
 119         if(corr_q_cnt[3])
 120             corr_q_accum <= corr_q_accum - adc_d;
 121         else
 122             corr_q_accum <= corr_q_accum + adc_d;
 123
 124         corr_i_cnt <= corr_i_cnt + 1;
 125         corr_q_cnt <= corr_q_cnt + 1;
 126     end
 127
 128     // The logic in hi_simulate.v reports 4 samples per bit. We report two
 129     // (I, Q) pairs per bit, so we should do 2 samples per pair.
 130     if(corr_i_cnt == 6'd31)
 131         after_hysteresis_prev <= after_hysteresis;
 132
 133     // Then the result from last time is serialized and send out to the ARM.
 134     // We get one report each cycle, and each report is 16 bits, so the
 135     // ssp_clk should be the adc_clk divided by 64/16 = 4.
 136
 137     if(corr_i_cnt[1:0] == 2'b10)
 138         ssp_clk <= 1'b0;
 139
 140     if(corr_i_cnt[1:0] == 2'b00)
 141     begin
 142         ssp_clk <= 1'b1;
 143         // Don't shift if we just loaded new data, obviously.
 144         if(corr_i_cnt != 7'd0)
 145         begin
 146             corr_i_out[7:0] <= {corr_i_out[6:0], corr_q_out[7]};
 147             corr_q_out[7:1] <= corr_q_out[6:0];
 148         end
 149     end
 150
 151     if(corr_i_cnt[5:2] == 4'b000 || corr_i_cnt[5:2] == 4'b1000)
 152         ssp_frame = 1'b1;
 153     else
 154         ssp_frame = 1'b0;
 155
 156 end
 157
 158 assign ssp_din = corr_i_out[7];
 159
 160 assign dbg = corr_i_cnt[3];
 161
 162 // Unused.
 163 assign pwr_lo = 1'b0;
 164
 165 endmodule