cvs.zerfleddert.de Git - proxmark3-svn/blob - fpga/lo_edge_detect.v

   1 //-----------------------------------------------------------------------------
   2 // The way that we connect things in low-frequency simulation mode. In this
   3 // case just pass everything through to the ARM, which can bit-bang this
   4 // (because it is so slow).
   5 //
   6 // Jonathan Westhues, April 2006
   7 // iZsh <izsh at fail0verflow.com>, June 2014
   8 //-----------------------------------------------------------------------------
   9
  10 module lo_edge_detect(
  11         input pck0, input [7:0] pck_cnt, input pck_divclk,
  12         output pwr_lo, output pwr_hi,
  13         output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
  14         input [7:0] adc_d, output adc_clk,
  15         output ssp_frame, input ssp_dout, output ssp_clk,
  16         input cross_lo,
  17         output dbg,
  18         input lf_field
  19 );
  20
  21 wire tag_modulation = ssp_dout & !lf_field;
  22 wire reader_modulation = !ssp_dout & lf_field & pck_divclk;
  23
  24 // No logic, straight through.
  25 assign pwr_oe1 = 1'b0; // not used in LF mode
  26 assign pwr_oe2 = tag_modulation;
  27 assign pwr_oe3 = tag_modulation;
  28 assign pwr_oe4 = tag_modulation;
  29 assign ssp_clk = cross_lo;
  30 assign pwr_lo = reader_modulation;
  31 assign pwr_hi = 1'b0;
  32 assign dbg = ssp_frame;
  33
  34 assign adc_clk = ~pck_divclk;
  35
  36 // Toggle the output with hysteresis
  37 //  Set to high if the ADC value is above 200
  38 //  Set to low if the ADC value is below 64
  39 reg is_high;
  40 reg is_low;
  41 reg output_state;
  42
  43 always @(posedge pck0)
  44 begin
  45         if((pck_cnt == 8'd7) && !pck_divclk) begin
  46                 is_high = (adc_d >= 8'd190);
  47                 is_low = (adc_d <= 8'd70);
  48         end
  49 end
  50
  51 always @(posedge is_high or posedge is_low)
  52 begin
  53         if(is_high)
  54                 output_state <= 1'd1;
  55         else if(is_low)
  56                 output_state <= 1'd0;
  57 end
  58
  59 assign ssp_frame = output_state;
  60
  61 endmodule
  62