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1 //-----------------------------------------------------------------------------
2 // (c) 2009 Henryk Plötz <henryk@ploetzli.ch>
3 //
4 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
5 // at your option, any later version. See the LICENSE.txt file for the text of
6 // the license.
7 //-----------------------------------------------------------------------------
8 // LEGIC RF simulation code
9 //-----------------------------------------------------------------------------
10
11 #include "legicrf.h"
12
13 static struct legic_frame {
14 int bits;
15 uint32_t data;
16 } current_frame;
17
18 static enum {
19 STATE_DISCON,
20 STATE_IV,
21 STATE_CON,
22 } legic_state;
23
24 static crc_t legic_crc;
25 static int legic_read_count;
26 static uint32_t legic_prng_bc;
27 static uint32_t legic_prng_iv;
28
29 static int legic_phase_drift;
30 static int legic_frame_drift;
31 static int legic_reqresp_drift;
32
33 AT91PS_TC timer;
34 AT91PS_TC prng_timer;
35
36 /*
37 static void setup_timer(void) {
38 // Set up Timer 1 to use for measuring time between pulses. Since we're bit-banging
39 // this it won't be terribly accurate but should be good enough.
40 //
41 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
42 timer = AT91C_BASE_TC1;
43 timer->TC_CCR = AT91C_TC_CLKDIS;
44 timer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK;
45 timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
46
47 //
48 // Set up Timer 2 to use for measuring time between frames in
49 // tag simulation mode. Runs 4x faster as Timer 1
50 //
51 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC2);
52 prng_timer = AT91C_BASE_TC2;
53 prng_timer->TC_CCR = AT91C_TC_CLKDIS;
54 prng_timer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV2_CLOCK;
55 prng_timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
56 }
57
58 AT91C_BASE_PMC->PMC_PCER |= (0x1 << 12) | (0x1 << 13) | (0x1 << 14);
59 AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
60
61 // fast clock
62 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable
63 AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz)/32 -- tick=1.5mks
64 AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR |
65 AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;
66 AT91C_BASE_TC0->TC_RA = 1;
67 AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000
68
69 */
70
71 // At TIMER_CLOCK3 (MCK/32)
72 //#define RWD_TIME_1 150 /* RWD_TIME_PAUSE off, 80us on = 100us */
73 //#define RWD_TIME_0 90 /* RWD_TIME_PAUSE off, 40us on = 60us */
74 //#define RWD_TIME_PAUSE 30 /* 20us */
75
76 // testing calculating in ticks instead of (us) microseconds.
77 #define RWD_TIME_1 120 // READER_TIME_PAUSE 20us off, 80us on = 100us 80 * 1.5 == 120ticks
78 #define RWD_TIME_0 60 // READER_TIME_PAUSE 20us off, 40us on = 60us 40 * 1.5 == 60ticks
79 #define RWD_TIME_PAUSE 30 // 20us == 20 * 1.5 == 30ticks */
80 #define TAG_BIT_PERIOD 150 // 100us == 100 * 1.5 == 150ticks
81 #define TAG_FRAME_WAIT 495 // 330us from READER frame end to TAG frame start. 330 * 1.5 == 495
82
83 #define RWD_TIME_FUZZ 20 // rather generous 13us, since the peak detector + hysteresis fuzz quite a bit
84
85 #define SIM_DIVISOR 586 /* prng_time/SIM_DIVISOR count prng needs to be forwared */
86 #define SIM_SHIFT 900 /* prng_time+SIM_SHIFT shift of delayed start */
87
88 #define OFFSET_LOG 1024
89
90 #define FUZZ_EQUAL(value, target, fuzz) ((value) > ((target)-(fuzz)) && (value) < ((target)+(fuzz)))
91
92 #ifndef SHORT_COIL
93 //#define LOW(x) AT91C_BASE_PIOA->PIO_CODR = (x)
94 # define SHORT_COIL LOW(GPIO_SSC_DOUT);
95 #endif
96 #ifndef OPEN_COIL
97 //#define HIGH(x) AT91C_BASE_PIOA->PIO_SODR = (x)
98 # define OPEN_COIL HIGH(GPIO_SSC_DOUT);
99 #endif
100
101 uint32_t sendFrameStop = 0;
102
103 // Pause pulse, off in 20us / 30ticks,
104 // ONE / ZERO bit pulse,
105 // one == 80us / 120ticks
106 // zero == 40us / 60ticks
107 #ifndef COIL_PULSE
108 # define COIL_PULSE(x) { \
109 SHORT_COIL; \
110 Wait(RWD_TIME_PAUSE); \
111 OPEN_COIL; \
112 Wait((x)); \
113 }
114 #endif
115 #ifndef GET_TICKS
116 # define GET_TICKS AT91C_BASE_TC0->TC_CV
117 #endif
118
119 // ToDo: define a meaningful maximum size for auth_table. The bigger this is, the lower will be the available memory for traces.
120 // Historically it used to be FREE_BUFFER_SIZE, which was 2744.
121 #define LEGIC_CARD_MEMSIZE 1024
122 static uint8_t* cardmem;
123
124 static void Wait(uint32_t time){
125 if ( time == 0 ) return;
126 time += GET_TICKS;
127 while (GET_TICKS < time);
128 }
129 // Starts Clock and waits until its reset
130 static void Reset(AT91PS_TC clock){
131 clock->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
132 while(clock->TC_CV > 1) ;
133 }
134
135 // Starts Clock and waits until its reset
136 static void ResetClock(void){
137 Reset(timer);
138 }
139
140 static void frame_append_bit(struct legic_frame * const f, int bit) {
141 // Overflow, won't happen
142 if (f->bits >= 31) return;
143
144 f->data |= (bit << f->bits);
145 f->bits++;
146 }
147
148 static void frame_clean(struct legic_frame * const f) {
149 f->data = 0;
150 f->bits = 0;
151 }
152
153 // Prng works when waiting in 99.1us cycles.
154 // and while sending/receiving in bit frames (100, 60)
155 /*static void CalibratePrng( uint32_t time){
156 // Calculate Cycles based on timer 100us
157 uint32_t i = (time - sendFrameStop) / 100 ;
158
159 // substract cycles of finished frames
160 int k = i - legic_prng_count()+1;
161
162 // substract current frame length, rewind to beginning
163 if ( k > 0 )
164 legic_prng_forward(k);
165 }
166 */
167
168 /* Generate Keystream */
169 static uint32_t get_key_stream(int skip, int count)
170 {
171 uint32_t key = 0;
172 int i;
173
174 // Use int to enlarge timer tc to 32bit
175 legic_prng_bc += prng_timer->TC_CV;
176
177 // reset the prng timer.
178 Reset(prng_timer);
179
180 /* If skip == -1, forward prng time based */
181 if(skip == -1) {
182 i = (legic_prng_bc + SIM_SHIFT)/SIM_DIVISOR; /* Calculate Cycles based on timer */
183 i -= legic_prng_count(); /* substract cycles of finished frames */
184 i -= count; /* substract current frame length, rewind to beginning */
185 legic_prng_forward(i);
186 } else {
187 legic_prng_forward(skip);
188 }
189
190 i = (count == 6) ? -1 : legic_read_count;
191
192 /* Write Time Data into LOG */
193 // uint8_t *BigBuf = BigBuf_get_addr();
194 // BigBuf[OFFSET_LOG+128+i] = legic_prng_count();
195 // BigBuf[OFFSET_LOG+256+i*4] = (legic_prng_bc >> 0) & 0xff;
196 // BigBuf[OFFSET_LOG+256+i*4+1] = (legic_prng_bc >> 8) & 0xff;
197 // BigBuf[OFFSET_LOG+256+i*4+2] = (legic_prng_bc >>16) & 0xff;
198 // BigBuf[OFFSET_LOG+256+i*4+3] = (legic_prng_bc >>24) & 0xff;
199 // BigBuf[OFFSET_LOG+384+i] = count;
200
201 /* Generate KeyStream */
202 for(i=0; i<count; i++) {
203 key |= legic_prng_get_bit() << i;
204 legic_prng_forward(1);
205 }
206 return key;
207 }
208
209 /* Send a frame in tag mode, the FPGA must have been set up by
210 * LegicRfSimulate
211 */
212 static void frame_send_tag(uint16_t response, uint8_t bits, uint8_t crypt) {
213 /* Bitbang the response */
214 LOW(GPIO_SSC_DOUT);
215 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
216 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
217
218 /* Use time to crypt frame */
219 if(crypt) {
220 legic_prng_forward(2); /* TAG_FRAME_WAIT -> shift by 2 */
221 response ^= legic_prng_get_bits(bits);
222 }
223
224 /* Wait for the frame start */
225 Wait( TAG_FRAME_WAIT );
226
227 uint8_t bit = 0;
228 for(int i = 0; i < bits; i++) {
229
230 bit = response & 1;
231 response >>= 1;
232
233 if (bit)
234 HIGH(GPIO_SSC_DOUT);
235 else
236 LOW(GPIO_SSC_DOUT);
237
238 Wait(100);
239 }
240 LOW(GPIO_SSC_DOUT);
241 }
242
243 /* Send a frame in reader mode, the FPGA must have been set up by
244 * LegicRfReader
245 */
246 static void frame_sendAsReader(uint32_t data, uint8_t bits){
247
248 uint32_t starttime = GET_TICKS, send = 0;
249 uint16_t mask = 1;
250 uint8_t prng1 = legic_prng_count() ;
251
252 // xor lsfr onto data.
253 send = data ^ legic_prng_get_bits(bits);
254
255 for (; mask < BITMASK(bits); mask <<= 1) {
256 if (send & mask) {
257 COIL_PULSE(RWD_TIME_1);
258 } else {
259 COIL_PULSE(RWD_TIME_0);
260 }
261 }
262
263 // Final pause to mark the end of the frame
264 COIL_PULSE(0);
265
266 sendFrameStop = GET_TICKS;
267 uint8_t cmdbytes[] = {
268 BYTEx(data, 0),
269 BYTEx(data, 1),
270 bits,
271 prng1,
272 legic_prng_count()
273 };
274 LogTrace(cmdbytes, sizeof(cmdbytes), starttime, sendFrameStop, NULL, TRUE);
275 }
276
277 /* Receive a frame from the card in reader emulation mode, the FPGA and
278 * timer must have been set up by LegicRfReader and frame_sendAsReader.
279 *
280 * The LEGIC RF protocol from card to reader does not include explicit
281 * frame start/stop information or length information. The reader must
282 * know beforehand how many bits it wants to receive. (Notably: a card
283 * sending a stream of 0-bits is indistinguishable from no card present.)
284 *
285 * Receive methodology: There is a fancy correlator in hi_read_rx_xcorr, but
286 * I'm not smart enough to use it. Instead I have patched hi_read_tx to output
287 * the ADC signal with hysteresis on SSP_DIN. Bit-bang that signal and look
288 * for edges. Count the edges in each bit interval. If they are approximately
289 * 0 this was a 0-bit, if they are approximately equal to the number of edges
290 * expected for a 212kHz subcarrier, this was a 1-bit. For timing we use the
291 * timer that's still running from frame_sendAsReader in order to get a synchronization
292 * with the frame that we just sent.
293 *
294 * FIXME: Because we're relying on the hysteresis to just do the right thing
295 * the range is severely reduced (and you'll probably also need a good antenna).
296 * So this should be fixed some time in the future for a proper receiver.
297 */
298 static void frame_receiveAsReader(struct legic_frame * const f, uint8_t bits) {
299
300 frame_clean(f);
301
302 uint8_t i = 0, edges = 0;
303 uint16_t lsfr = 0;
304 uint32_t the_bit = 1, next_bit_at = 0, data;
305 int old_level = 0, level = 0;
306
307 if(bits > 32) bits = 32;
308
309 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
310 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
311
312 // calibrate the prng.
313 legic_prng_forward(2);
314
315 // precompute the cipher
316 uint8_t prng_before = legic_prng_count() ;
317
318 lsfr = legic_prng_get_bits(bits);
319
320 data = lsfr;
321
322 //FIXED time between sending frame and now listening frame. 330us
323 Wait( TAG_FRAME_WAIT - ( GET_TICKS - sendFrameStop ) );
324 //Wait( TAG_FRAME_WAIT );
325
326 uint32_t starttime = GET_TICKS;
327
328 next_bit_at = GET_TICKS + TAG_BIT_PERIOD;
329
330 for( i = 0; i < bits; i++) {
331 edges = 0;
332 while ( GET_TICKS < next_bit_at) {
333
334 level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
335
336 if (level != old_level)
337 ++edges;
338
339 old_level = level;
340 }
341 next_bit_at += TAG_BIT_PERIOD;
342
343 // We expect 42 edges == ONE
344 if(edges > 20 && edges < 64)
345 data ^= the_bit;
346
347 the_bit <<= 1;
348 }
349
350 // output
351 f->data = data;
352 f->bits = bits;
353
354 // log
355 sendFrameStop = GET_TICKS;
356
357 uint8_t cmdbytes[] = {
358 BYTEx(data,0),
359 BYTEx(data,1),
360 bits,
361 BYTEx(lsfr,0),
362 BYTEx(lsfr,1),
363 BYTEx(data, 0) ^ BYTEx(lsfr,0),
364 BYTEx(data, 1) ^ BYTEx(lsfr,1),
365 prng_before,
366 legic_prng_count()
367 };
368 LogTrace(cmdbytes, sizeof(cmdbytes), starttime, sendFrameStop, NULL, FALSE);
369 }
370
371 // Setup pm3 as a Legic Reader
372 static uint32_t setup_phase_reader(uint8_t iv) {
373
374 // Switch on carrier and let the tag charge for 1ms
375 HIGH(GPIO_SSC_DOUT);
376 SpinDelay(300);
377
378 ResetUSClock();
379
380 // no keystream yet
381 legic_prng_init(0);
382
383 // send IV handshake
384 frame_sendAsReader(iv, 7);
385
386 // Now both tag and reader has same IV. Prng can start.
387 legic_prng_init(iv);
388
389 frame_receiveAsReader(&current_frame, 6);
390
391 // fixed delay before sending ack.
392 Wait(360); // 240us = 360tick
393 legic_prng_forward(2); //240us / 100 == 2.4 iterations
394
395 // Send obsfuscated acknowledgment frame.
396 // 0x19 = 0x18 MIM22, 0x01 LSB READCMD
397 // 0x39 = 0x38 MIM256, MIM1024 0x01 LSB READCMD
398 switch ( current_frame.data ) {
399 case 0x0D: frame_sendAsReader(0x19, 6); break;
400 case 0x1D:
401 case 0x3D: frame_sendAsReader(0x39, 6); break;
402 default: break;
403 }
404 return current_frame.data;
405
406 // fixed delay after setup phase.
407 Wait(375); // 260us == 375 ticks
408 legic_prng_forward(2);// 260us / 100 == 2.6 iterations
409 }
410
411 static void LegicCommonInit(void) {
412 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
413 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX);
414 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
415 FpgaSetupSsc();
416
417 /* Bitbang the transmitter */
418 LOW(GPIO_SSC_DOUT);
419 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
420 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
421
422 // reserve a cardmem, meaning we can use the tracelog function in bigbuff easier.
423 cardmem = BigBuf_malloc(LEGIC_CARD_MEMSIZE);
424 memset(cardmem, 0x00, LEGIC_CARD_MEMSIZE);
425
426 clear_trace();
427 set_tracing(TRUE);
428 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
429
430 StartCountUS();
431 }
432
433 // Switch off carrier, make sure tag is reset
434 static void switch_off_tag_rwd(void) {
435 LOW(GPIO_SSC_DOUT);
436 SpinDelay(10);
437 WDT_HIT();
438 }
439
440 // calculate crc4 for a legic READ command
441 // 5,8,10 address size.
442 static uint32_t legic4Crc(uint8_t legicCmd, uint16_t byte_index, uint8_t value, uint8_t cmd_sz) {
443 crc_clear(&legic_crc);
444 //uint32_t temp = (value << cmd_sz) | (byte_index << 1) | legicCmd;
445 //crc_update(&legic_crc, temp, cmd_sz + 8 );
446 crc_update(&legic_crc, 1, 1); /* CMD_READ */
447 crc_update(&legic_crc, byte_index, cmd_sz-1);
448 crc_update(&legic_crc, value, 8);
449 return crc_finish(&legic_crc);
450 }
451
452 int legic_read_byte(int byte_index, int cmd_sz) {
453
454 uint8_t byte = 0, crc = 0, calcCrc = 0;
455 uint32_t cmd = (byte_index << 1) | LEGIC_READ;
456
457 frame_sendAsReader(cmd, cmd_sz);
458 frame_receiveAsReader(&current_frame, 12);
459
460 byte = BYTEx(current_frame.data, 0);
461 calcCrc = legic4Crc(LEGIC_READ, byte_index, byte, cmd_sz);
462 crc = BYTEx(current_frame.data, 1);
463
464 if( calcCrc != crc ) {
465 Dbprintf("!!! crc mismatch: expected %x but got %x !!!", calcCrc, crc);
466 return -1;
467 }
468
469 Wait(690); // 460us == 690ticks
470 legic_prng_forward(4); // 460 / 100 = 4.6 iterations
471
472 return byte;
473 }
474
475 /*
476 * - assemble a write_cmd_frame with crc and send it
477 * - wait until the tag sends back an ACK ('1' bit unencrypted)
478 * - forward the prng based on the timing
479 */
480 //int legic_write_byte(int byte, int addr, int addr_sz, int PrngCorrection) {
481 int legic_write_byte(uint8_t byte, uint16_t addr, uint8_t addr_sz) {
482
483 //do not write UID, CRC at offset 0-4.
484 if (addr <= 4) return 0;
485
486 // crc
487 crc_clear(&legic_crc);
488 crc_update(&legic_crc, 0, 1); /* CMD_WRITE */
489 crc_update(&legic_crc, addr, addr_sz);
490 crc_update(&legic_crc, byte, 8);
491 uint32_t crc = crc_finish(&legic_crc);
492
493 uint32_t crc2 = legic4Crc(LEGIC_WRITE, addr, byte, addr_sz+1);
494 if ( crc != crc2 )
495 Dbprintf("crc is missmatch");
496
497 // send write command
498 uint32_t cmd = ((crc <<(addr_sz+1+8)) //CRC
499 |(byte <<(addr_sz+1)) //Data
500 |(addr <<1) //Address
501 | LEGIC_WRITE); //CMD = Write
502
503 uint32_t cmd_sz = addr_sz+1+8+4; //crc+data+cmd
504
505 legic_prng_forward(2); /* we wait anyways */
506
507 Wait(TAG_FRAME_WAIT);
508
509 frame_sendAsReader(cmd, cmd_sz);
510
511 // wllm-rbnt doesnt have these
512 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
513 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
514
515 // wait for ack
516 int t, old_level = 0, edges = 0;
517 int next_bit_at = 0;
518
519 Wait(TAG_FRAME_WAIT);
520
521 for( t = 0; t < 80; ++t) {
522 edges = 0;
523 next_bit_at += TAG_BIT_PERIOD;
524 while(timer->TC_CV < next_bit_at) {
525 int level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
526 if(level != old_level)
527 edges++;
528
529 old_level = level;
530 }
531 if(edges > 20 && edges < 60) { /* expected are 42 edges */
532 int t = timer->TC_CV;
533 int c = t / TAG_BIT_PERIOD;
534
535 ResetClock();
536 legic_prng_forward(c);
537 return 0;
538 }
539 }
540
541 ResetClock();
542 return -1;
543 }
544
545 int LegicRfReader(int offset, int bytes, int iv) {
546
547 uint16_t byte_index = 0;
548 uint8_t cmd_sz = 0;
549 int card_sz = 0;
550 uint8_t isOK = 1;
551
552 if ( MF_DBGLEVEL >= 2)
553 Dbprintf("setting up legic card, IV = 0x%02x", iv);
554
555 LegicCommonInit();
556
557 uint32_t tag_type = setup_phase_reader(iv);
558
559 //we lose to mutch time with dprintf
560 switch_off_tag_rwd();
561
562 switch(tag_type) {
563 case 0x0d:
564 if ( MF_DBGLEVEL >= 2) DbpString("MIM22 card found, reading card");
565 cmd_sz = 6;
566 card_sz = 22;
567 break;
568 case 0x1d:
569 if ( MF_DBGLEVEL >= 2) DbpString("MIM256 card found, reading card");
570 cmd_sz = 9;
571 card_sz = 256;
572 break;
573 case 0x3d:
574 if ( MF_DBGLEVEL >= 2) DbpString("MIM1024 card found, reading card");
575 cmd_sz = 11;
576 card_sz = 1024;
577 break;
578 default:
579 if ( MF_DBGLEVEL >= 1) Dbprintf("Unknown card format: %x", tag_type);
580 isOK = 0;
581 goto OUT;
582 break;
583 }
584 if (bytes == -1)
585 bytes = card_sz;
586
587 if (bytes + offset >= card_sz)
588 bytes = card_sz - offset;
589
590 // Start setup and read bytes.
591 setup_phase_reader(iv);
592
593 LED_B_ON();
594 while (byte_index < bytes) {
595 int r = legic_read_byte(byte_index + offset, cmd_sz);
596
597 if (r == -1 || BUTTON_PRESS()) {
598 if ( MF_DBGLEVEL >= 2) DbpString("operation aborted");
599 isOK = 0;
600 goto OUT;
601 }
602 cardmem[++byte_index] = r;
603 //byte_index++;
604 WDT_HIT();
605 }
606
607 OUT:
608 switch_off_tag_rwd();
609 LEDsoff();
610 uint8_t len = (bytes & 0x3FF);
611 cmd_send(CMD_ACK,isOK,len,0,cardmem,len);
612 return 0;
613 }
614
615 /*int _LegicRfWriter(int offset, int bytes, int addr_sz, uint8_t *BigBuf, int RoundBruteforceValue) {
616 int byte_index=0;
617
618 LED_B_ON();
619 setup_phase_reader(iv);
620 //legic_prng_forward(2);
621 while(byte_index < bytes) {
622 int r;
623
624 //check if the DCF should be changed
625 if ( (offset == 0x05) && (bytes == 0x02) ) {
626 //write DCF in reverse order (addr 0x06 before 0x05)
627 r = legic_write_byte(BigBuf[(0x06-byte_index)], (0x06-byte_index), addr_sz, RoundBruteforceValue);
628 //legic_prng_forward(1);
629 if(r == 0) {
630 byte_index++;
631 r = legic_write_byte(BigBuf[(0x06-byte_index)], (0x06-byte_index), addr_sz, RoundBruteforceValue);
632 }
633 //legic_prng_forward(1);
634 }
635 else {
636 r = legic_write_byte(BigBuf[byte_index+offset], byte_index+offset, addr_sz, RoundBruteforceValue);
637 }
638 if((r != 0) || BUTTON_PRESS()) {
639 Dbprintf("operation aborted @ 0x%03.3x", byte_index);
640 switch_off_tag_rwd();
641 LED_B_OFF();
642 LED_C_OFF();
643 return -1;
644 }
645
646 WDT_HIT();
647 byte_index++;
648 if(byte_index & 0x10) LED_C_ON(); else LED_C_OFF();
649 }
650 LED_B_OFF();
651 LED_C_OFF();
652 DbpString("write successful");
653 return 0;
654 }*/
655
656 void LegicRfWriter(int offset, int bytes, int iv) {
657
658 int byte_index = 0, addr_sz = 0;
659
660 LegicCommonInit();
661
662 if ( MF_DBGLEVEL >= 2) DbpString("setting up legic card");
663
664 uint32_t tag_type = setup_phase_reader(iv);
665
666 switch_off_tag_rwd();
667
668 switch(tag_type) {
669 case 0x0d:
670 if(offset+bytes > 22) {
671 Dbprintf("Error: can not write to 0x%03.3x on MIM22", offset + bytes);
672 return;
673 }
674 addr_sz = 5;
675 if ( MF_DBGLEVEL >= 2) Dbprintf("MIM22 card found, writing 0x%02.2x - 0x%02.2x ...", offset, offset + bytes);
676 break;
677 case 0x1d:
678 if(offset+bytes > 0x100) {
679 Dbprintf("Error: can not write to 0x%03.3x on MIM256", offset + bytes);
680 return;
681 }
682 addr_sz = 8;
683 if ( MF_DBGLEVEL >= 2) Dbprintf("MIM256 card found, writing 0x%02.2x - 0x%02.2x ...", offset, offset + bytes);
684 break;
685 case 0x3d:
686 if(offset+bytes > 0x400) {
687 Dbprintf("Error: can not write to 0x%03.3x on MIM1024", offset + bytes);
688 return;
689 }
690 addr_sz = 10;
691 if ( MF_DBGLEVEL >= 2) Dbprintf("MIM1024 card found, writing 0x%03.3x - 0x%03.3x ...", offset, offset + bytes);
692 break;
693 default:
694 Dbprintf("No or unknown card found, aborting");
695 return;
696 }
697
698 LED_B_ON();
699 setup_phase_reader(iv);
700 int r = 0;
701 while(byte_index < bytes) {
702
703 //check if the DCF should be changed
704 if ( ((byte_index+offset) == 0x05) && (bytes >= 0x02) ) {
705 //write DCF in reverse order (addr 0x06 before 0x05)
706 r = legic_write_byte(cardmem[(0x06-byte_index)], (0x06-byte_index), addr_sz);
707
708 // write second byte on success...
709 if(r == 0) {
710 byte_index++;
711 r = legic_write_byte(cardmem[(0x06-byte_index)], (0x06-byte_index), addr_sz);
712 }
713 }
714 else {
715 r = legic_write_byte(cardmem[byte_index+offset], byte_index+offset, addr_sz);
716 }
717
718 if ((r != 0) || BUTTON_PRESS()) {
719 Dbprintf("operation aborted @ 0x%03.3x", byte_index);
720 switch_off_tag_rwd();
721 LEDsoff();
722 return;
723 }
724
725 WDT_HIT();
726 byte_index++;
727 }
728 LEDsoff();
729 if ( MF_DBGLEVEL >= 1) DbpString("write successful");
730 }
731
732 void LegicRfRawWriter(int address, int byte, int iv) {
733
734 int byte_index = 0, addr_sz = 0;
735
736 LegicCommonInit();
737
738 if ( MF_DBGLEVEL >= 2) DbpString("setting up legic card");
739
740 uint32_t tag_type = setup_phase_reader(iv);
741
742 switch_off_tag_rwd();
743
744 switch(tag_type) {
745 case 0x0d:
746 if(address > 22) {
747 Dbprintf("Error: can not write to 0x%03.3x on MIM22", address);
748 return;
749 }
750 addr_sz = 5;
751 if ( MF_DBGLEVEL >= 2) Dbprintf("MIM22 card found, writing at addr 0x%02.2x - value 0x%02.2x ...", address, byte);
752 break;
753 case 0x1d:
754 if(address > 0x100) {
755 Dbprintf("Error: can not write to 0x%03.3x on MIM256", address);
756 return;
757 }
758 addr_sz = 8;
759 if ( MF_DBGLEVEL >= 2) Dbprintf("MIM256 card found, writing at addr 0x%02.2x - value 0x%02.2x ...", address, byte);
760 break;
761 case 0x3d:
762 if(address > 0x400) {
763 Dbprintf("Error: can not write to 0x%03.3x on MIM1024", address);
764 return;
765 }
766 addr_sz = 10;
767 if ( MF_DBGLEVEL >= 2) Dbprintf("MIM1024 card found, writing at addr 0x%03.3x - value 0x%03.3x ...", address, byte);
768 break;
769 default:
770 Dbprintf("No or unknown card found, aborting");
771 return;
772 }
773
774 Dbprintf("integer value: %d address: %d addr_sz: %d", byte, address, addr_sz);
775 LED_B_ON();
776
777 setup_phase_reader(iv);
778
779 int r = legic_write_byte(byte, address, addr_sz);
780
781 if((r != 0) || BUTTON_PRESS()) {
782 Dbprintf("operation aborted @ 0x%03.3x (%1d)", byte_index, r);
783 switch_off_tag_rwd();
784 LEDsoff();
785 return;
786 }
787
788 LEDsoff();
789 if ( MF_DBGLEVEL >= 1) DbpString("write successful");
790 }
791
792 /* Handle (whether to respond) a frame in tag mode
793 * Only called when simulating a tag.
794 */
795 static void frame_handle_tag(struct legic_frame const * const f)
796 {
797 uint8_t *BigBuf = BigBuf_get_addr();
798
799 /* First Part of Handshake (IV) */
800 if(f->bits == 7) {
801
802 LED_C_ON();
803
804 // Reset prng timer
805 Reset(prng_timer);
806
807 legic_prng_init(f->data);
808 frame_send_tag(0x3d, 6, 1); /* 0x3d^0x26 = 0x1B */
809 legic_state = STATE_IV;
810 legic_read_count = 0;
811 legic_prng_bc = 0;
812 legic_prng_iv = f->data;
813
814
815 ResetClock();
816 Wait(280);
817 return;
818 }
819
820 /* 0x19==??? */
821 if(legic_state == STATE_IV) {
822 int local_key = get_key_stream(3, 6);
823 int xored = 0x39 ^ local_key;
824 if((f->bits == 6) && (f->data == xored)) {
825 legic_state = STATE_CON;
826
827 ResetClock();
828 Wait(200);
829 return;
830
831 } else {
832 legic_state = STATE_DISCON;
833 LED_C_OFF();
834 Dbprintf("iv: %02x frame: %02x key: %02x xored: %02x", legic_prng_iv, f->data, local_key, xored);
835 return;
836 }
837 }
838
839 /* Read */
840 if(f->bits == 11) {
841 if(legic_state == STATE_CON) {
842 int key = get_key_stream(2, 11); //legic_phase_drift, 11);
843 int addr = f->data ^ key; addr = addr >> 1;
844 int data = BigBuf[addr];
845 int hash = legic4Crc(LEGIC_READ, addr, data, 11) << 8;
846 BigBuf[OFFSET_LOG+legic_read_count] = (uint8_t)addr;
847 legic_read_count++;
848
849 //Dbprintf("Data:%03.3x, key:%03.3x, addr: %03.3x, read_c:%u", f->data, key, addr, read_c);
850 legic_prng_forward(legic_reqresp_drift);
851
852 frame_send_tag(hash | data, 12, 1);
853
854 ResetClock();
855 legic_prng_forward(2);
856 Wait(180);
857 return;
858 }
859 }
860
861 /* Write */
862 if(f->bits == 23) {
863 int key = get_key_stream(-1, 23); //legic_frame_drift, 23);
864 int addr = f->data ^ key; addr = addr >> 1; addr = addr & 0x3ff;
865 int data = f->data ^ key; data = data >> 11; data = data & 0xff;
866
867 /* write command */
868 legic_state = STATE_DISCON;
869 LED_C_OFF();
870 Dbprintf("write - addr: %x, data: %x", addr, data);
871 return;
872 }
873
874 if(legic_state != STATE_DISCON) {
875 Dbprintf("Unexpected: sz:%u, Data:%03.3x, State:%u, Count:%u", f->bits, f->data, legic_state, legic_read_count);
876 int i;
877 Dbprintf("IV: %03.3x", legic_prng_iv);
878 for(i = 0; i<legic_read_count; i++) {
879 Dbprintf("Read Nb: %u, Addr: %u", i, BigBuf[OFFSET_LOG+i]);
880 }
881
882 for(i = -1; i<legic_read_count; i++) {
883 uint32_t t;
884 t = BigBuf[OFFSET_LOG+256+i*4];
885 t |= BigBuf[OFFSET_LOG+256+i*4+1] << 8;
886 t |= BigBuf[OFFSET_LOG+256+i*4+2] <<16;
887 t |= BigBuf[OFFSET_LOG+256+i*4+3] <<24;
888
889 Dbprintf("Cycles: %u, Frame Length: %u, Time: %u",
890 BigBuf[OFFSET_LOG+128+i],
891 BigBuf[OFFSET_LOG+384+i],
892 t);
893 }
894 }
895 legic_state = STATE_DISCON;
896 legic_read_count = 0;
897 SpinDelay(10);
898 LED_C_OFF();
899 return;
900 }
901
902 /* Read bit by bit untill full frame is received
903 * Call to process frame end answer
904 */
905 static void emit(int bit) {
906
907 switch (bit) {
908 case 1:
909 frame_append_bit(&current_frame, 1);
910 break;
911 case 0:
912 frame_append_bit(&current_frame, 0);
913 break;
914 default:
915 if(current_frame.bits <= 4) {
916 frame_clean(&current_frame);
917 } else {
918 frame_handle_tag(&current_frame);
919 frame_clean(&current_frame);
920 }
921 WDT_HIT();
922 break;
923 }
924 }
925
926 void LegicRfSimulate(int phase, int frame, int reqresp)
927 {
928 /* ADC path high-frequency peak detector, FPGA in high-frequency simulator mode,
929 * modulation mode set to 212kHz subcarrier. We are getting the incoming raw
930 * envelope waveform on DIN and should send our response on DOUT.
931 *
932 * The LEGIC RF protocol is pulse-pause-encoding from reader to card, so we'll
933 * measure the time between two rising edges on DIN, and no encoding on the
934 * subcarrier from card to reader, so we'll just shift out our verbatim data
935 * on DOUT, 1 bit is 100us. The time from reader to card frame is still unclear,
936 * seems to be 300us-ish.
937 */
938
939 legic_phase_drift = phase;
940 legic_frame_drift = frame;
941 legic_reqresp_drift = reqresp;
942
943 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
944 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
945 FpgaSetupSsc();
946 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_212K);
947
948 /* Bitbang the receiver */
949 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
950 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
951
952 //setup_timer();
953 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
954
955 int old_level = 0;
956 int active = 0;
957 legic_state = STATE_DISCON;
958
959 LED_B_ON();
960 DbpString("Starting Legic emulator, press button to end");
961
962 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
963 int level = !!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
964 int time = timer->TC_CV;
965
966 if(level != old_level) {
967 if(level == 1) {
968 timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
969
970 if (FUZZ_EQUAL(time, RWD_TIME_1, RWD_TIME_FUZZ)) {
971 /* 1 bit */
972 emit(1);
973 active = 1;
974 LED_A_ON();
975 } else if (FUZZ_EQUAL(time, RWD_TIME_0, RWD_TIME_FUZZ)) {
976 /* 0 bit */
977 emit(0);
978 active = 1;
979 LED_A_ON();
980 } else if (active) {
981 /* invalid */
982 emit(-1);
983 active = 0;
984 LED_A_OFF();
985 }
986 }
987 }
988
989 /* Frame end */
990 if(time >= (RWD_TIME_1+RWD_TIME_FUZZ) && active) {
991 emit(-1);
992 active = 0;
993 LED_A_OFF();
994 }
995
996 if(time >= (20*RWD_TIME_1) && (timer->TC_SR & AT91C_TC_CLKSTA)) {
997 timer->TC_CCR = AT91C_TC_CLKDIS;
998 }
999
1000 old_level = level;
1001 WDT_HIT();
1002 }
1003 if ( MF_DBGLEVEL >= 1) DbpString("Stopped");
1004 LEDsoff();
1005 }
1006
1007 //-----------------------------------------------------------------------------
1008 //-----------------------------------------------------------------------------
1009
1010
1011 //-----------------------------------------------------------------------------
1012 // Code up a string of octets at layer 2 (including CRC, we don't generate
1013 // that here) so that they can be transmitted to the reader. Doesn't transmit
1014 // them yet, just leaves them ready to send in ToSend[].
1015 //-----------------------------------------------------------------------------
1016 // static void CodeLegicAsTag(const uint8_t *cmd, int len)
1017 // {
1018 // int i;
1019
1020 // ToSendReset();
1021
1022 // // Transmit a burst of ones, as the initial thing that lets the
1023 // // reader get phase sync. This (TR1) must be > 80/fs, per spec,
1024 // // but tag that I've tried (a Paypass) exceeds that by a fair bit,
1025 // // so I will too.
1026 // for(i = 0; i < 20; i++) {
1027 // ToSendStuffBit(1);
1028 // ToSendStuffBit(1);
1029 // ToSendStuffBit(1);
1030 // ToSendStuffBit(1);
1031 // }
1032
1033 // // Send SOF.
1034 // for(i = 0; i < 10; i++) {
1035 // ToSendStuffBit(0);
1036 // ToSendStuffBit(0);
1037 // ToSendStuffBit(0);
1038 // ToSendStuffBit(0);
1039 // }
1040 // for(i = 0; i < 2; i++) {
1041 // ToSendStuffBit(1);
1042 // ToSendStuffBit(1);
1043 // ToSendStuffBit(1);
1044 // ToSendStuffBit(1);
1045 // }
1046
1047 // for(i = 0; i < len; i++) {
1048 // int j;
1049 // uint8_t b = cmd[i];
1050
1051 // // Start bit
1052 // ToSendStuffBit(0);
1053 // ToSendStuffBit(0);
1054 // ToSendStuffBit(0);
1055 // ToSendStuffBit(0);
1056
1057 // // Data bits
1058 // for(j = 0; j < 8; j++) {
1059 // if(b & 1) {
1060 // ToSendStuffBit(1);
1061 // ToSendStuffBit(1);
1062 // ToSendStuffBit(1);
1063 // ToSendStuffBit(1);
1064 // } else {
1065 // ToSendStuffBit(0);
1066 // ToSendStuffBit(0);
1067 // ToSendStuffBit(0);
1068 // ToSendStuffBit(0);
1069 // }
1070 // b >>= 1;
1071 // }
1072
1073 // // Stop bit
1074 // ToSendStuffBit(1);
1075 // ToSendStuffBit(1);
1076 // ToSendStuffBit(1);
1077 // ToSendStuffBit(1);
1078 // }
1079
1080 // // Send EOF.
1081 // for(i = 0; i < 10; i++) {
1082 // ToSendStuffBit(0);
1083 // ToSendStuffBit(0);
1084 // ToSendStuffBit(0);
1085 // ToSendStuffBit(0);
1086 // }
1087 // for(i = 0; i < 2; i++) {
1088 // ToSendStuffBit(1);
1089 // ToSendStuffBit(1);
1090 // ToSendStuffBit(1);
1091 // ToSendStuffBit(1);
1092 // }
1093
1094 // // Convert from last byte pos to length
1095 // ToSendMax++;
1096 // }
1097
1098 //-----------------------------------------------------------------------------
1099 // The software UART that receives commands from the reader, and its state
1100 // variables.
1101 //-----------------------------------------------------------------------------
1102 static struct {
1103 enum {
1104 STATE_UNSYNCD,
1105 STATE_GOT_FALLING_EDGE_OF_SOF,
1106 STATE_AWAITING_START_BIT,
1107 STATE_RECEIVING_DATA
1108 } state;
1109 uint16_t shiftReg;
1110 int bitCnt;
1111 int byteCnt;
1112 int byteCntMax;
1113 int posCnt;
1114 uint8_t *output;
1115 } Uart;
1116
1117 /* Receive & handle a bit coming from the reader.
1118 *
1119 * This function is called 4 times per bit (every 2 subcarrier cycles).
1120 * Subcarrier frequency fs is 212kHz, 1/fs = 4,72us, i.e. function is called every 9,44us
1121 *
1122 * LED handling:
1123 * LED A -> ON once we have received the SOF and are expecting the rest.
1124 * LED A -> OFF once we have received EOF or are in error state or unsynced
1125 *
1126 * Returns: true if we received a EOF
1127 * false if we are still waiting for some more
1128 */
1129 // static RAMFUNC int HandleLegicUartBit(uint8_t bit)
1130 // {
1131 // switch(Uart.state) {
1132 // case STATE_UNSYNCD:
1133 // if(!bit) {
1134 // // we went low, so this could be the beginning of an SOF
1135 // Uart.state = STATE_GOT_FALLING_EDGE_OF_SOF;
1136 // Uart.posCnt = 0;
1137 // Uart.bitCnt = 0;
1138 // }
1139 // break;
1140
1141 // case STATE_GOT_FALLING_EDGE_OF_SOF:
1142 // Uart.posCnt++;
1143 // if(Uart.posCnt == 2) { // sample every 4 1/fs in the middle of a bit
1144 // if(bit) {
1145 // if(Uart.bitCnt > 9) {
1146 // // we've seen enough consecutive
1147 // // zeros that it's a valid SOF
1148 // Uart.posCnt = 0;
1149 // Uart.byteCnt = 0;
1150 // Uart.state = STATE_AWAITING_START_BIT;
1151 // LED_A_ON(); // Indicate we got a valid SOF
1152 // } else {
1153 // // didn't stay down long enough
1154 // // before going high, error
1155 // Uart.state = STATE_UNSYNCD;
1156 // }
1157 // } else {
1158 // // do nothing, keep waiting
1159 // }
1160 // Uart.bitCnt++;
1161 // }
1162 // if(Uart.posCnt >= 4) Uart.posCnt = 0;
1163 // if(Uart.bitCnt > 12) {
1164 // // Give up if we see too many zeros without
1165 // // a one, too.
1166 // LED_A_OFF();
1167 // Uart.state = STATE_UNSYNCD;
1168 // }
1169 // break;
1170
1171 // case STATE_AWAITING_START_BIT:
1172 // Uart.posCnt++;
1173 // if(bit) {
1174 // if(Uart.posCnt > 50/2) { // max 57us between characters = 49 1/fs, max 3 etus after low phase of SOF = 24 1/fs
1175 // // stayed high for too long between
1176 // // characters, error
1177 // Uart.state = STATE_UNSYNCD;
1178 // }
1179 // } else {
1180 // // falling edge, this starts the data byte
1181 // Uart.posCnt = 0;
1182 // Uart.bitCnt = 0;
1183 // Uart.shiftReg = 0;
1184 // Uart.state = STATE_RECEIVING_DATA;
1185 // }
1186 // break;
1187
1188 // case STATE_RECEIVING_DATA:
1189 // Uart.posCnt++;
1190 // if(Uart.posCnt == 2) {
1191 // // time to sample a bit
1192 // Uart.shiftReg >>= 1;
1193 // if(bit) {
1194 // Uart.shiftReg |= 0x200;
1195 // }
1196 // Uart.bitCnt++;
1197 // }
1198 // if(Uart.posCnt >= 4) {
1199 // Uart.posCnt = 0;
1200 // }
1201 // if(Uart.bitCnt == 10) {
1202 // if((Uart.shiftReg & 0x200) && !(Uart.shiftReg & 0x001))
1203 // {
1204 // // this is a data byte, with correct
1205 // // start and stop bits
1206 // Uart.output[Uart.byteCnt] = (Uart.shiftReg >> 1) & 0xff;
1207 // Uart.byteCnt++;
1208
1209 // if(Uart.byteCnt >= Uart.byteCntMax) {
1210 // // Buffer overflowed, give up
1211 // LED_A_OFF();
1212 // Uart.state = STATE_UNSYNCD;
1213 // } else {
1214 // // so get the next byte now
1215 // Uart.posCnt = 0;
1216 // Uart.state = STATE_AWAITING_START_BIT;
1217 // }
1218 // } else if (Uart.shiftReg == 0x000) {
1219 // // this is an EOF byte
1220 // LED_A_OFF(); // Finished receiving
1221 // Uart.state = STATE_UNSYNCD;
1222 // if (Uart.byteCnt != 0) {
1223 // return TRUE;
1224 // }
1225 // } else {
1226 // // this is an error
1227 // LED_A_OFF();
1228 // Uart.state = STATE_UNSYNCD;
1229 // }
1230 // }
1231 // break;
1232
1233 // default:
1234 // LED_A_OFF();
1235 // Uart.state = STATE_UNSYNCD;
1236 // break;
1237 // }
1238
1239 // return FALSE;
1240 // }
1241
1242
1243 static void UartReset() {
1244 Uart.byteCntMax = 3;
1245 Uart.state = STATE_UNSYNCD;
1246 Uart.byteCnt = 0;
1247 Uart.bitCnt = 0;
1248 Uart.posCnt = 0;
1249 memset(Uart.output, 0x00, 3);
1250 }
1251
1252 // static void UartInit(uint8_t *data) {
1253 // Uart.output = data;
1254 // UartReset();
1255 // }
1256
1257 //=============================================================================
1258 // An LEGIC reader. We take layer two commands, code them
1259 // appropriately, and then send them to the tag. We then listen for the
1260 // tag's response, which we leave in the buffer to be demodulated on the
1261 // PC side.
1262 //=============================================================================
1263
1264 static struct {
1265 enum {
1266 DEMOD_UNSYNCD,
1267 DEMOD_PHASE_REF_TRAINING,
1268 DEMOD_AWAITING_FALLING_EDGE_OF_SOF,
1269 DEMOD_GOT_FALLING_EDGE_OF_SOF,
1270 DEMOD_AWAITING_START_BIT,
1271 DEMOD_RECEIVING_DATA
1272 } state;
1273 int bitCount;
1274 int posCount;
1275 int thisBit;
1276 uint16_t shiftReg;
1277 uint8_t *output;
1278 int len;
1279 int sumI;
1280 int sumQ;
1281 } Demod;
1282
1283 /*
1284 * Handles reception of a bit from the tag
1285 *
1286 * This function is called 2 times per bit (every 4 subcarrier cycles).
1287 * Subcarrier frequency fs is 212kHz, 1/fs = 4,72us, i.e. function is called every 9,44us
1288 *
1289 * LED handling:
1290 * LED C -> ON once we have received the SOF and are expecting the rest.
1291 * LED C -> OFF once we have received EOF or are unsynced
1292 *
1293 * Returns: true if we received a EOF
1294 * false if we are still waiting for some more
1295 *
1296 */
1297
1298 #ifndef SUBCARRIER_DETECT_THRESHOLD
1299 # define SUBCARRIER_DETECT_THRESHOLD 8
1300 #endif
1301
1302 // Subcarrier amplitude v = sqrt(ci^2 + cq^2), approximated here by max(abs(ci),abs(cq)) + 1/2*min(abs(ci),abs(cq)))
1303 #ifndef CHECK_FOR_SUBCARRIER
1304 # define CHECK_FOR_SUBCARRIER() { v = MAX(ai, aq) + MIN(halfci, halfcq); }
1305 #endif
1306
1307 // The soft decision on the bit uses an estimate of just the
1308 // quadrant of the reference angle, not the exact angle.
1309 // Subcarrier amplitude v = sqrt(ci^2 + cq^2), approximated here by max(abs(ci),abs(cq)) + 1/2*min(abs(ci),abs(cq)))
1310 #define MAKE_SOFT_DECISION() { \
1311 if(Demod.sumI > 0) \
1312 v = ci; \
1313 else \
1314 v = -ci; \
1315 \
1316 if(Demod.sumQ > 0) \
1317 v += cq; \
1318 else \
1319 v -= cq; \
1320 \
1321 }
1322
1323 static RAMFUNC int HandleLegicSamplesDemod(int ci, int cq)
1324 {
1325 int v = 0;
1326 int ai = ABS(ci);
1327 int aq = ABS(cq);
1328 int halfci = (ai >> 1);
1329 int halfcq = (aq >> 1);
1330
1331 switch(Demod.state) {
1332 case DEMOD_UNSYNCD:
1333
1334 CHECK_FOR_SUBCARRIER()
1335
1336 if(v > SUBCARRIER_DETECT_THRESHOLD) { // subcarrier detected
1337 Demod.state = DEMOD_PHASE_REF_TRAINING;
1338 Demod.sumI = ci;
1339 Demod.sumQ = cq;
1340 Demod.posCount = 1;
1341 }
1342 break;
1343
1344 case DEMOD_PHASE_REF_TRAINING:
1345 if(Demod.posCount < 8) {
1346
1347 CHECK_FOR_SUBCARRIER()
1348
1349 if (v > SUBCARRIER_DETECT_THRESHOLD) {
1350 // set the reference phase (will code a logic '1') by averaging over 32 1/fs.
1351 // note: synchronization time > 80 1/fs
1352 Demod.sumI += ci;
1353 Demod.sumQ += cq;
1354 ++Demod.posCount;
1355 } else {
1356 // subcarrier lost
1357 Demod.state = DEMOD_UNSYNCD;
1358 }
1359 } else {
1360 Demod.state = DEMOD_AWAITING_FALLING_EDGE_OF_SOF;
1361 }
1362 break;
1363
1364 case DEMOD_AWAITING_FALLING_EDGE_OF_SOF:
1365
1366 MAKE_SOFT_DECISION()
1367
1368 //Dbprintf("ICE: %d %d %d %d %d", v, Demod.sumI, Demod.sumQ, ci, cq );
1369 // logic '0' detected
1370 if (v <= 0) {
1371
1372 Demod.state = DEMOD_GOT_FALLING_EDGE_OF_SOF;
1373
1374 // start of SOF sequence
1375 Demod.posCount = 0;
1376 } else {
1377 // maximum length of TR1 = 200 1/fs
1378 if(Demod.posCount > 25*2) Demod.state = DEMOD_UNSYNCD;
1379 }
1380 ++Demod.posCount;
1381 break;
1382
1383 case DEMOD_GOT_FALLING_EDGE_OF_SOF:
1384 ++Demod.posCount;
1385
1386 MAKE_SOFT_DECISION()
1387
1388 if(v > 0) {
1389 // low phase of SOF too short (< 9 etu). Note: spec is >= 10, but FPGA tends to "smear" edges
1390 if(Demod.posCount < 10*2) {
1391 Demod.state = DEMOD_UNSYNCD;
1392 } else {
1393 LED_C_ON(); // Got SOF
1394 Demod.state = DEMOD_AWAITING_START_BIT;
1395 Demod.posCount = 0;
1396 Demod.len = 0;
1397 }
1398 } else {
1399 // low phase of SOF too long (> 12 etu)
1400 if(Demod.posCount > 13*2) {
1401 Demod.state = DEMOD_UNSYNCD;
1402 LED_C_OFF();
1403 }
1404 }
1405 break;
1406
1407 case DEMOD_AWAITING_START_BIT:
1408 ++Demod.posCount;
1409
1410 MAKE_SOFT_DECISION()
1411
1412 if(v > 0) {
1413 // max 19us between characters = 16 1/fs, max 3 etu after low phase of SOF = 24 1/fs
1414 if(Demod.posCount > 3*2) {
1415 Demod.state = DEMOD_UNSYNCD;
1416 LED_C_OFF();
1417 }
1418 } else {
1419 // start bit detected
1420 Demod.bitCount = 0;
1421 Demod.posCount = 1; // this was the first half
1422 Demod.thisBit = v;
1423 Demod.shiftReg = 0;
1424 Demod.state = DEMOD_RECEIVING_DATA;
1425 }
1426 break;
1427
1428 case DEMOD_RECEIVING_DATA:
1429
1430 MAKE_SOFT_DECISION()
1431
1432 if(Demod.posCount == 0) {
1433 // first half of bit
1434 Demod.thisBit = v;
1435 Demod.posCount = 1;
1436 } else {
1437 // second half of bit
1438 Demod.thisBit += v;
1439 Demod.shiftReg >>= 1;
1440 // logic '1'
1441 if(Demod.thisBit > 0)
1442 Demod.shiftReg |= 0x200;
1443
1444 ++Demod.bitCount;
1445
1446 if(Demod.bitCount == 10) {
1447
1448 uint16_t s = Demod.shiftReg;
1449
1450 if((s & 0x200) && !(s & 0x001)) {
1451 // stop bit == '1', start bit == '0'
1452 uint8_t b = (s >> 1);
1453 Demod.output[Demod.len] = b;
1454 ++Demod.len;
1455 Demod.state = DEMOD_AWAITING_START_BIT;
1456 } else {
1457 Demod.state = DEMOD_UNSYNCD;
1458 LED_C_OFF();
1459
1460 if(s == 0x000) {
1461 // This is EOF (start, stop and all data bits == '0'
1462 return TRUE;
1463 }
1464 }
1465 }
1466 Demod.posCount = 0;
1467 }
1468 break;
1469
1470 default:
1471 Demod.state = DEMOD_UNSYNCD;
1472 LED_C_OFF();
1473 break;
1474 }
1475 return FALSE;
1476 }
1477
1478 // Clear out the state of the "UART" that receives from the tag.
1479 static void DemodReset() {
1480 Demod.len = 0;
1481 Demod.state = DEMOD_UNSYNCD;
1482 Demod.posCount = 0;
1483 Demod.sumI = 0;
1484 Demod.sumQ = 0;
1485 Demod.bitCount = 0;
1486 Demod.thisBit = 0;
1487 Demod.shiftReg = 0;
1488 memset(Demod.output, 0x00, 3);
1489 }
1490
1491 static void DemodInit(uint8_t *data) {
1492 Demod.output = data;
1493 DemodReset();
1494 }
1495
1496 /*
1497 * Demodulate the samples we received from the tag, also log to tracebuffer
1498 * quiet: set to 'TRUE' to disable debug output
1499 */
1500 #define LEGIC_DMA_BUFFER_SIZE 256
1501 static void GetSamplesForLegicDemod(int n, bool quiet)
1502 {
1503 int max = 0;
1504 bool gotFrame = FALSE;
1505 int lastRxCounter = LEGIC_DMA_BUFFER_SIZE;
1506 int ci, cq, samples = 0;
1507
1508 BigBuf_free();
1509
1510 // And put the FPGA in the appropriate mode
1511 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_QUARTER_FREQ);
1512
1513 // The response (tag -> reader) that we're receiving.
1514 // Set up the demodulator for tag -> reader responses.
1515 DemodInit(BigBuf_malloc(MAX_FRAME_SIZE));
1516
1517 // The DMA buffer, used to stream samples from the FPGA
1518 int8_t *dmaBuf = (int8_t*) BigBuf_malloc(LEGIC_DMA_BUFFER_SIZE);
1519 int8_t *upTo = dmaBuf;
1520
1521 // Setup and start DMA.
1522 if ( !FpgaSetupSscDma((uint8_t*) dmaBuf, LEGIC_DMA_BUFFER_SIZE) ){
1523 if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting");
1524 return;
1525 }
1526
1527 // Signal field is ON with the appropriate LED:
1528 LED_D_ON();
1529 for(;;) {
1530 int behindBy = lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR;
1531 if(behindBy > max) max = behindBy;
1532
1533 while(((lastRxCounter-AT91C_BASE_PDC_SSC->PDC_RCR) & (LEGIC_DMA_BUFFER_SIZE-1)) > 2) {
1534 ci = upTo[0];
1535 cq = upTo[1];
1536 upTo += 2;
1537 if(upTo >= dmaBuf + LEGIC_DMA_BUFFER_SIZE) {
1538 upTo = dmaBuf;
1539 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo;
1540 AT91C_BASE_PDC_SSC->PDC_RNCR = LEGIC_DMA_BUFFER_SIZE;
1541 }
1542 lastRxCounter -= 2;
1543 if(lastRxCounter <= 0)
1544 lastRxCounter = LEGIC_DMA_BUFFER_SIZE;
1545
1546 samples += 2;
1547
1548 gotFrame = HandleLegicSamplesDemod(ci , cq );
1549 if ( gotFrame )
1550 break;
1551 }
1552
1553 if(samples > n || gotFrame)
1554 break;
1555 }
1556
1557 FpgaDisableSscDma();
1558
1559 if (!quiet && Demod.len == 0) {
1560 Dbprintf("max behindby = %d, samples = %d, gotFrame = %d, Demod.len = %d, Demod.sumI = %d, Demod.sumQ = %d",
1561 max,
1562 samples,
1563 gotFrame,
1564 Demod.len,
1565 Demod.sumI,
1566 Demod.sumQ
1567 );
1568 }
1569
1570 //Tracing
1571 if (Demod.len > 0) {
1572 uint8_t parity[MAX_PARITY_SIZE] = {0x00};
1573 LogTrace(Demod.output, Demod.len, 0, 0, parity, FALSE);
1574 }
1575 }
1576 //-----------------------------------------------------------------------------
1577 // Transmit the command (to the tag) that was placed in ToSend[].
1578 //-----------------------------------------------------------------------------
1579 static void TransmitForLegic(void)
1580 {
1581 int c;
1582
1583 FpgaSetupSsc();
1584
1585 while(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY))
1586 AT91C_BASE_SSC->SSC_THR = 0xff;
1587
1588 // Signal field is ON with the appropriate Red LED
1589 LED_D_ON();
1590
1591 // Signal we are transmitting with the Green LED
1592 LED_B_ON();
1593 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
1594
1595 for(c = 0; c < 10;) {
1596 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1597 AT91C_BASE_SSC->SSC_THR = 0xff;
1598 c++;
1599 }
1600 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1601 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
1602 (void)r;
1603 }
1604 WDT_HIT();
1605 }
1606
1607 c = 0;
1608 for(;;) {
1609 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1610 AT91C_BASE_SSC->SSC_THR = ToSend[c];
1611 legic_prng_forward(1); // forward the lfsr
1612 c++;
1613 if(c >= ToSendMax) {
1614 break;
1615 }
1616 }
1617 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1618 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
1619 (void)r;
1620 }
1621 WDT_HIT();
1622 }
1623 LED_B_OFF();
1624 }
1625
1626
1627 //-----------------------------------------------------------------------------
1628 // Code a layer 2 command (string of octets, including CRC) into ToSend[],
1629 // so that it is ready to transmit to the tag using TransmitForLegic().
1630 //-----------------------------------------------------------------------------
1631 static void CodeLegicBitsAsReader(const uint8_t *cmd, uint8_t cmdlen, int bits)
1632 {
1633 int i, j;
1634 uint8_t b;
1635
1636 ToSendReset();
1637
1638 // Send SOF
1639 for(i = 0; i < 7; i++)
1640 ToSendStuffBit(1);
1641
1642
1643 for(i = 0; i < cmdlen; i++) {
1644 // Start bit
1645 ToSendStuffBit(0);
1646
1647 // Data bits
1648 b = cmd[i];
1649 for(j = 0; j < bits; j++) {
1650 if(b & 1) {
1651 ToSendStuffBit(1);
1652 } else {
1653 ToSendStuffBit(0);
1654 }
1655 b >>= 1;
1656 }
1657 }
1658
1659 // Convert from last character reference to length
1660 ++ToSendMax;
1661 }
1662
1663 /**
1664 Convenience function to encode, transmit and trace Legic comms
1665 **/
1666 static void CodeAndTransmitLegicAsReader(const uint8_t *cmd, uint8_t cmdlen, int bits)
1667 {
1668 CodeLegicBitsAsReader(cmd, cmdlen, bits);
1669 TransmitForLegic();
1670 if (tracing) {
1671 uint8_t parity[1] = {0x00};
1672 LogTrace(cmd, cmdlen, 0, 0, parity, TRUE);
1673 }
1674 }
1675
1676 int ice_legic_select_card()
1677 {
1678 //int cmd_size=0, card_size=0;
1679 uint8_t wakeup[] = { 0x7F };
1680 uint8_t getid[] = {0x19};
1681
1682 //legic_prng_init(SESSION_IV);
1683
1684 // first, wake up the tag, 7bits
1685 CodeAndTransmitLegicAsReader(wakeup, sizeof(wakeup), 7);
1686
1687 GetSamplesForLegicDemod(1000, TRUE);
1688
1689 //frame_receiveAsReader(&current_frame, 6, 1);
1690
1691 legic_prng_forward(1); /* we wait anyways */
1692
1693 //while(timer->TC_CV < 387) ; /* ~ 258us */
1694 //frame_sendAsReader(0x19, 6);
1695 CodeAndTransmitLegicAsReader(getid, sizeof(getid), 8);
1696 GetSamplesForLegicDemod(1000, TRUE);
1697
1698 //if (Demod.len < 14) return 2;
1699 Dbprintf("CARD TYPE: %02x LEN: %d", Demod.output[0], Demod.len);
1700
1701 switch(Demod.output[0]) {
1702 case 0x1d:
1703 DbpString("MIM 256 card found");
1704 // cmd_size = 9;
1705 // card_size = 256;
1706 break;
1707 case 0x3d:
1708 DbpString("MIM 1024 card found");
1709 // cmd_size = 11;
1710 // card_size = 1024;
1711 break;
1712 default:
1713 return -1;
1714 }
1715
1716 // if(bytes == -1)
1717 // bytes = card_size;
1718
1719 // if(bytes + offset >= card_size)
1720 // bytes = card_size - offset;
1721
1722 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1723 set_tracing(FALSE);
1724 return 1;
1725 }
1726
1727 // Set up LEGIC communication
1728 void ice_legic_setup() {
1729
1730 // standard things.
1731 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1732 BigBuf_free(); BigBuf_Clear_ext(false);
1733 clear_trace();
1734 set_tracing(TRUE);
1735 DemodReset();
1736 UartReset();
1737
1738 // Set up the synchronous serial port
1739 FpgaSetupSsc();
1740
1741 // connect Demodulated Signal to ADC:
1742 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1743
1744 // Signal field is on with the appropriate LED
1745 LED_D_ON();
1746 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
1747 SpinDelay(20);
1748 // Start the timer
1749 //StartCountSspClk();
1750
1751 // initalize CRC
1752 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
1753
1754 // initalize prng
1755 legic_prng_init(0);
1756 }
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