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1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Hitag2 emulation (preliminary test version)
7 //
8 // (c) 2009 Henryk Plötz <henryk@ploetzli.ch>
9 //-----------------------------------------------------------------------------
10 // Hitag2 complete rewrite of the code
11 // - Fixed modulation/encoding issues
12 // - Rewrote code for transponder emulation
13 // - Added snooping of transponder communication
14 // - Added reader functionality
15 //
16 // (c) 2012 Roel Verdult
17 //-----------------------------------------------------------------------------
18
19 #include "proxmark3.h"
20 #include "apps.h"
21 #include "util.h"
22 #include "hitag2.h"
23 #include "string.h"
24 #include "BigBuf.h"
25
26 static bool bQuiet;
27 static bool bCrypto;
28 static bool bAuthenticating;
29 static bool bPwd;
30 static bool bSuccessful;
31
32 struct hitag2_tag {
33 uint32_t uid;
34 enum {
35 TAG_STATE_RESET = 0x01, // Just powered up, awaiting GetSnr
36 TAG_STATE_ACTIVATING = 0x02 , // In activation phase (password mode), sent UID, awaiting reader password
37 TAG_STATE_ACTIVATED = 0x03, // Activation complete, awaiting read/write commands
38 TAG_STATE_WRITING = 0x04, // In write command, awaiting sector contents to be written
39 } state;
40 unsigned int active_sector;
41 byte_t crypto_active;
42 uint64_t cs;
43 byte_t sectors[12][4];
44 };
45
46 static struct hitag2_tag tag = {
47 .state = TAG_STATE_RESET,
48 .sectors = { // Password mode: | Crypto mode:
49 [0] = { 0x02, 0x4e, 0x02, 0x20}, // UID | UID
50 [1] = { 0x4d, 0x49, 0x4b, 0x52}, // Password RWD | 32 bit LSB key
51 [2] = { 0x20, 0xf0, 0x4f, 0x4e}, // Reserved | 16 bit MSB key, 16 bit reserved
52 [3] = { 0x0e, 0xaa, 0x48, 0x54}, // Configuration, password TAG | Configuration, password TAG
53 [4] = { 0x46, 0x5f, 0x4f, 0x4b}, // Data: F_OK
54 [5] = { 0x55, 0x55, 0x55, 0x55}, // Data: UUUU
55 [6] = { 0xaa, 0xaa, 0xaa, 0xaa}, // Data: ....
56 [7] = { 0x55, 0x55, 0x55, 0x55}, // Data: UUUU
57 [8] = { 0x00, 0x00, 0x00, 0x00}, // RSK Low
58 [9] = { 0x00, 0x00, 0x00, 0x00}, // RSK High
59 [10] = { 0x00, 0x00, 0x00, 0x00}, // RCF
60 [11] = { 0x00, 0x00, 0x00, 0x00}, // SYNC
61 },
62 };
63
64 // ToDo: define a meaningful maximum size for auth_table. The bigger this is, the lower will be the available memory for traces.
65 // Historically it used to be FREE_BUFFER_SIZE, which was 2744.
66 #define AUTH_TABLE_LENGTH 2744
67 static byte_t* auth_table;
68 static size_t auth_table_pos = 0;
69 static size_t auth_table_len = AUTH_TABLE_LENGTH;
70
71 static byte_t password[4];
72 static byte_t NrAr[8];
73 static byte_t key[8];
74 static uint64_t cipher_state;
75
76 /* Following is a modified version of cryptolib.com/ciphers/hitag2/ */
77 // Software optimized 48-bit Philips/NXP Mifare Hitag2 PCF7936/46/47/52 stream cipher algorithm by I.C. Wiener 2006-2007.
78 // For educational purposes only.
79 // No warranties or guarantees of any kind.
80 // This code is released into the public domain by its author.
81
82 // Basic macros:
83
84 #define u8 uint8_t
85 #define u32 uint32_t
86 #define u64 uint64_t
87 #define rev8(x) ((((x)>>7)&1)+((((x)>>6)&1)<<1)+((((x)>>5)&1)<<2)+((((x)>>4)&1)<<3)+((((x)>>3)&1)<<4)+((((x)>>2)&1)<<5)+((((x)>>1)&1)<<6)+(((x)&1)<<7))
88 #define rev16(x) (rev8 (x)+(rev8 (x>> 8)<< 8))
89 #define rev32(x) (rev16(x)+(rev16(x>>16)<<16))
90 #define rev64(x) (rev32(x)+(rev32(x>>32)<<32))
91 #define bit(x,n) (((x)>>(n))&1)
92 #define bit32(x,n) ((((x)[(n)>>5])>>((n)))&1)
93 #define inv32(x,i,n) ((x)[(i)>>5]^=((u32)(n))<<((i)&31))
94 #define rotl64(x, n) ((((u64)(x))<<((n)&63))+(((u64)(x))>>((0-(n))&63)))
95
96 // Single bit Hitag2 functions:
97 #define i4(x,a,b,c,d) ((u32)((((x)>>(a))&1)+(((x)>>(b))&1)*2+(((x)>>(c))&1)*4+(((x)>>(d))&1)*8))
98
99 static const u32 ht2_f4a = 0x2C79; // 0010 1100 0111 1001
100 static const u32 ht2_f4b = 0x6671; // 0110 0110 0111 0001
101 static const u32 ht2_f5c = 0x7907287B; // 0111 1001 0000 0111 0010 1000 0111 1011
102
103 static u32 _f20 (const u64 x)
104 {
105 u32 i5;
106
107 i5 = ((ht2_f4a >> i4 (x, 1, 2, 4, 5)) & 1)* 1
108 + ((ht2_f4b >> i4 (x, 7,11,13,14)) & 1)* 2
109 + ((ht2_f4b >> i4 (x,16,20,22,25)) & 1)* 4
110 + ((ht2_f4b >> i4 (x,27,28,30,32)) & 1)* 8
111 + ((ht2_f4a >> i4 (x,33,42,43,45)) & 1)*16;
112
113 return (ht2_f5c >> i5) & 1;
114 }
115
116 static u64 _hitag2_init (const u64 key, const u32 serial, const u32 IV)
117 {
118 u32 i;
119 u64 x = ((key & 0xFFFF) << 32) + serial;
120
121 for (i = 0; i < 32; i++)
122 {
123 x >>= 1;
124 x += (u64) (_f20 (x) ^ (((IV >> i) ^ (key >> (i+16))) & 1)) << 47;
125 }
126 return x;
127 }
128
129 static u64 _hitag2_round (u64 *state)
130 {
131 u64 x = *state;
132
133 x = (x >> 1) +
134 ((((x >> 0) ^ (x >> 2) ^ (x >> 3) ^ (x >> 6)
135 ^ (x >> 7) ^ (x >> 8) ^ (x >> 16) ^ (x >> 22)
136 ^ (x >> 23) ^ (x >> 26) ^ (x >> 30) ^ (x >> 41)
137 ^ (x >> 42) ^ (x >> 43) ^ (x >> 46) ^ (x >> 47)) & 1) << 47);
138
139 *state = x;
140 return _f20 (x);
141 }
142
143 // "MIKRON" = O N M I K R
144 // Key = 4F 4E 4D 49 4B 52 - Secret 48-bit key
145 // Serial = 49 43 57 69 - Serial number of the tag, transmitted in clear
146 // Random = 65 6E 45 72 - Random IV, transmitted in clear
147 //~28~DC~80~31 = D7 23 7F CE - Authenticator value = inverted first 4 bytes of the keystream
148
149 // The code below must print out "D7 23 7F CE 8C D0 37 A9 57 49 C1 E6 48 00 8A B6".
150 // The inverse of the first 4 bytes is sent to the tag to authenticate.
151 // The rest is encrypted by XORing it with the subsequent keystream.
152
153 static u32 _hitag2_byte (u64 * x)
154 {
155 u32 i, c;
156
157 for (i = 0, c = 0; i < 8; i++) c += (u32) _hitag2_round (x) << (i^7);
158 return c;
159 }
160
161 static int hitag2_reset(void) {
162 tag.state = TAG_STATE_RESET;
163 tag.crypto_active = 0;
164 return 0;
165 }
166
167 static int hitag2_init(void) {
168 hitag2_reset();
169 return 0;
170 }
171
172 static void hitag2_cipher_reset(struct hitag2_tag *tag, const byte_t *iv)
173 {
174 uint64_t key = ((uint64_t)tag->sectors[2][2]) |
175 ((uint64_t)tag->sectors[2][3] << 8) |
176 ((uint64_t)tag->sectors[1][0] << 16) |
177 ((uint64_t)tag->sectors[1][1] << 24) |
178 ((uint64_t)tag->sectors[1][2] << 32) |
179 ((uint64_t)tag->sectors[1][3] << 40);
180 uint32_t uid = ((uint32_t)tag->sectors[0][0]) |
181 ((uint32_t)tag->sectors[0][1] << 8) |
182 ((uint32_t)tag->sectors[0][2] << 16) |
183 ((uint32_t)tag->sectors[0][3] << 24);
184 uint32_t iv_ = (((uint32_t)(iv[0]))) |
185 (((uint32_t)(iv[1])) << 8) |
186 (((uint32_t)(iv[2])) << 16) |
187 (((uint32_t)(iv[3])) << 24);
188 tag->cs = _hitag2_init(rev64(key), rev32(uid), rev32(iv_));
189 }
190
191 static int hitag2_cipher_authenticate(uint64_t* cs, const byte_t *authenticator_is)
192 {
193 byte_t authenticator_should[4];
194 authenticator_should[0] = ~_hitag2_byte(cs);
195 authenticator_should[1] = ~_hitag2_byte(cs);
196 authenticator_should[2] = ~_hitag2_byte(cs);
197 authenticator_should[3] = ~_hitag2_byte(cs);
198 return (memcmp(authenticator_should, authenticator_is, 4) == 0);
199 }
200
201 static int hitag2_cipher_transcrypt(uint64_t* cs, byte_t *data, unsigned int bytes, unsigned int bits)
202 {
203 int i;
204 for(i=0; i<bytes; i++) data[i] ^= _hitag2_byte(cs);
205 for(i=0; i<bits; i++) data[bytes] ^= _hitag2_round(cs) << (7-i);
206 return 0;
207 }
208
209 // Sam7s has several timers, we will use the source TIMER_CLOCK1 (aka AT91C_TC_CLKS_TIMER_DIV1_CLOCK)
210 // TIMER_CLOCK1 = MCK/2, MCK is running at 48 MHz, Timer is running at 48/2 = 24 MHz
211 // Hitag units (T0) have duration of 8 microseconds (us), which is 1/125000 per second (carrier)
212 // T0 = TIMER_CLOCK1 / 125000 = 192
213 #define T0 192
214
215 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
216 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
217
218 #define HITAG_FRAME_LEN 20
219 #define HITAG_T_STOP 36 /* T_EOF should be > 36 */
220 #define HITAG_T_LOW 8 /* T_LOW should be 4..10 */
221 #define HITAG_T_0_MIN 15 /* T[0] should be 18..22 */
222 #define HITAG_T_1_MIN 25 /* T[1] should be 26..30 */
223 //#define HITAG_T_EOF 40 /* T_EOF should be > 36 */
224 #define HITAG_T_EOF 80 /* T_EOF should be > 36 */
225 #define HITAG_T_WAIT_1 200 /* T_wresp should be 199..206 */
226 #define HITAG_T_WAIT_2 90 /* T_wresp should be 199..206 */
227 #define HITAG_T_WAIT_MAX 300 /* bit more than HITAG_T_WAIT_1 + HITAG_T_WAIT_2 */
228
229 #define HITAG_T_TAG_ONE_HALF_PERIOD 10
230 #define HITAG_T_TAG_TWO_HALF_PERIOD 25
231 #define HITAG_T_TAG_THREE_HALF_PERIOD 41
232 #define HITAG_T_TAG_FOUR_HALF_PERIOD 57
233
234 #define HITAG_T_TAG_HALF_PERIOD 16
235 #define HITAG_T_TAG_FULL_PERIOD 32
236
237 #define HITAG_T_TAG_CAPTURE_ONE_HALF 13
238 #define HITAG_T_TAG_CAPTURE_TWO_HALF 25
239 #define HITAG_T_TAG_CAPTURE_THREE_HALF 41
240 #define HITAG_T_TAG_CAPTURE_FOUR_HALF 57
241
242
243 static void hitag_send_bit(int bit) {
244 LED_A_ON();
245 // Reset clock for the next bit
246 AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;
247
248 // Fixed modulation, earlier proxmark version used inverted signal
249 if(bit == 0) {
250 // Manchester: Unloaded, then loaded |__--|
251 LOW(GPIO_SSC_DOUT);
252 while(AT91C_BASE_TC0->TC_CV < T0*HITAG_T_TAG_HALF_PERIOD);
253 HIGH(GPIO_SSC_DOUT);
254 while(AT91C_BASE_TC0->TC_CV < T0*HITAG_T_TAG_FULL_PERIOD);
255 } else {
256 // Manchester: Loaded, then unloaded |--__|
257 HIGH(GPIO_SSC_DOUT);
258 while(AT91C_BASE_TC0->TC_CV < T0*HITAG_T_TAG_HALF_PERIOD);
259 LOW(GPIO_SSC_DOUT);
260 while(AT91C_BASE_TC0->TC_CV < T0*HITAG_T_TAG_FULL_PERIOD);
261 }
262 LED_A_OFF();
263 }
264
265 static void hitag_send_frame(const byte_t* frame, size_t frame_len)
266 {
267 // Send start of frame
268 for(size_t i=0; i<5; i++) {
269 hitag_send_bit(1);
270 }
271
272 // Send the content of the frame
273 for(size_t i=0; i<frame_len; i++) {
274 hitag_send_bit((frame[i/8] >> (7-(i%8)))&1);
275 }
276
277 // Drop the modulation
278 LOW(GPIO_SSC_DOUT);
279 }
280
281
282 static void hitag2_handle_reader_command(byte_t* rx, const size_t rxlen, byte_t* tx, size_t* txlen)
283 {
284 byte_t rx_air[HITAG_FRAME_LEN];
285
286 // Copy the (original) received frame how it is send over the air
287 memcpy(rx_air,rx,nbytes(rxlen));
288
289 if(tag.crypto_active) {
290 hitag2_cipher_transcrypt(&(tag.cs),rx,rxlen/8,rxlen%8);
291 }
292
293 // Reset the transmission frame length
294 *txlen = 0;
295
296 // Try to find out which command was send by selecting on length (in bits)
297 switch (rxlen) {
298 // Received 11000 from the reader, request for UID, send UID
299 case 05: {
300 // Always send over the air in the clear plaintext mode
301 if(rx_air[0] != 0xC0) {
302 // Unknown frame ?
303 return;
304 }
305 *txlen = 32;
306 memcpy(tx,tag.sectors[0],4);
307 tag.crypto_active = 0;
308 }
309 break;
310
311 // Read/Write command: ..xx x..y yy with yyy == ~xxx, xxx is sector number
312 case 10: {
313 unsigned int sector = (~( ((rx[0]<<2)&0x04) | ((rx[1]>>6)&0x03) ) & 0x07);
314 // Verify complement of sector index
315 if(sector != ((rx[0]>>3)&0x07)) {
316 //DbpString("Transmission error (read/write)");
317 return;
318 }
319
320 switch (rx[0] & 0xC6) {
321 // Read command: 11xx x00y
322 case 0xC0:
323 memcpy(tx,tag.sectors[sector],4);
324 *txlen = 32;
325 break;
326
327 // Inverted Read command: 01xx x10y
328 case 0x44:
329 for (size_t i=0; i<4; i++) {
330 tx[i] = tag.sectors[sector][i] ^ 0xff;
331 }
332 *txlen = 32;
333 break;
334
335 // Write command: 10xx x01y
336 case 0x82:
337 // Prepare write, acknowledge by repeating command
338 memcpy(tx,rx,nbytes(rxlen));
339 *txlen = rxlen;
340 tag.active_sector = sector;
341 tag.state=TAG_STATE_WRITING;
342 break;
343
344 // Unknown command
345 default:
346 Dbprintf("Uknown command: %02x %02x",rx[0],rx[1]);
347 return;
348 break;
349 }
350 }
351 break;
352
353 // Writing data or Reader password
354 case 32: {
355 if(tag.state == TAG_STATE_WRITING) {
356 // These are the sector contents to be written. We don't have to do anything else.
357 memcpy(tag.sectors[tag.active_sector],rx,nbytes(rxlen));
358 tag.state=TAG_STATE_RESET;
359 return;
360 } else {
361 // Received RWD password, respond with configuration and our password
362 if(memcmp(rx,tag.sectors[1],4) != 0) {
363 DbpString("Reader password is wrong");
364 return;
365 }
366 *txlen = 32;
367 memcpy(tx,tag.sectors[3],4);
368 }
369 }
370 break;
371
372 // Received RWD authentication challenge and respnse
373 case 64: {
374 // Store the authentication attempt
375 if (auth_table_len < (AUTH_TABLE_LENGTH-8)) {
376 memcpy(auth_table+auth_table_len,rx,8);
377 auth_table_len += 8;
378 }
379
380 // Reset the cipher state
381 hitag2_cipher_reset(&tag,rx);
382 // Check if the authentication was correct
383 if(!hitag2_cipher_authenticate(&(tag.cs),rx+4)) {
384 // The reader failed to authenticate, do nothing
385 Dbprintf("auth: %02x%02x%02x%02x%02x%02x%02x%02x Failed!",rx[0],rx[1],rx[2],rx[3],rx[4],rx[5],rx[6],rx[7]);
386 return;
387 }
388 // Succesful, but commented out reporting back to the Host, this may delay to much.
389 // Dbprintf("auth: %02x%02x%02x%02x%02x%02x%02x%02x OK!",rx[0],rx[1],rx[2],rx[3],rx[4],rx[5],rx[6],rx[7]);
390
391 // Activate encryption algorithm for all further communication
392 tag.crypto_active = 1;
393
394 // Use the tag password as response
395 memcpy(tx,tag.sectors[3],4);
396 *txlen = 32;
397 }
398 break;
399 }
400
401 // LogTraceHitag(rx,rxlen,0,0,false);
402 // LogTraceHitag(tx,*txlen,0,0,true);
403
404 if(tag.crypto_active) {
405 hitag2_cipher_transcrypt(&(tag.cs), tx, *txlen/8, *txlen%8);
406 }
407 }
408
409 static void hitag_reader_send_bit(int bit) {
410 LED_A_ON();
411 // Reset clock for the next bit
412 AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;
413
414 // Binary puls length modulation (BPLM) is used to encode the data stream
415 // This means that a transmission of a one takes longer than that of a zero
416
417 // Enable modulation, which means, drop the field
418 HIGH(GPIO_SSC_DOUT);
419
420 // Wait for 4-10 times the carrier period
421 while(AT91C_BASE_TC0->TC_CV < T0*6);
422 // SpinDelayUs(8*8);
423
424 // Disable modulation, just activates the field again
425 LOW(GPIO_SSC_DOUT);
426
427 if(bit == 0) {
428 // Zero bit: |_-|
429 while(AT91C_BASE_TC0->TC_CV < T0*22);
430
431 } else {
432 // One bit: |_--|
433 while(AT91C_BASE_TC0->TC_CV < T0*28);
434 }
435 LED_A_OFF();
436 }
437
438
439 static void hitag_reader_send_frame(const byte_t* frame, size_t frame_len)
440 {
441 // Send the content of the frame
442 for(size_t i=0; i<frame_len; i++) {
443 hitag_reader_send_bit((frame[i/8] >> (7-(i%8)))&1);
444 }
445 // Send EOF
446 AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;
447 // Enable modulation, which means, drop the field
448 HIGH(GPIO_SSC_DOUT);
449 // Wait for 4-10 times the carrier period
450 while(AT91C_BASE_TC0->TC_CV < T0*6);
451 // Disable modulation, just activates the field again
452 LOW(GPIO_SSC_DOUT);
453 }
454
455 size_t blocknr;
456
457 static bool hitag2_password(byte_t* rx, const size_t rxlen, byte_t* tx, size_t* txlen) {
458 // Reset the transmission frame length
459 *txlen = 0;
460
461 // Try to find out which command was send by selecting on length (in bits)
462 switch (rxlen) {
463 // No answer, try to resurrect
464 case 0: {
465 // Stop if there is no answer (after sending password)
466 if (bPwd) {
467 DbpString("Password failed!");
468 return false;
469 }
470 *txlen = 5;
471 memcpy(tx,"\xc0",nbytes(*txlen));
472 } break;
473
474 // Received UID, tag password
475 case 32: {
476 if (!bPwd) {
477 *txlen = 32;
478 memcpy(tx,password,4);
479 bPwd = true;
480 memcpy(tag.sectors[blocknr],rx,4);
481 blocknr++;
482 } else {
483
484 if(blocknr == 1){
485 //store password in block1, the TAG answers with Block3, but we need the password in memory
486 memcpy(tag.sectors[blocknr],tx,4);
487 } else {
488 memcpy(tag.sectors[blocknr],rx,4);
489 }
490
491 blocknr++;
492 if (blocknr > 7) {
493 DbpString("Read succesful!");
494 bSuccessful = true;
495 return false;
496 }
497 *txlen = 10;
498 tx[0] = 0xc0 | (blocknr << 3) | ((blocknr^7) >> 2);
499 tx[1] = ((blocknr^7) << 6);
500 }
501 } break;
502
503 // Unexpected response
504 default: {
505 Dbprintf("Uknown frame length: %d",rxlen);
506 return false;
507 } break;
508 }
509 return true;
510 }
511
512 static bool hitag2_crypto(byte_t* rx, const size_t rxlen, byte_t* tx, size_t* txlen) {
513 // Reset the transmission frame length
514 *txlen = 0;
515
516 if(bCrypto) {
517 hitag2_cipher_transcrypt(&cipher_state,rx,rxlen/8,rxlen%8);
518 }
519
520 // Try to find out which command was send by selecting on length (in bits)
521 switch (rxlen) {
522 // No answer, try to resurrect
523 case 0: {
524 // Stop if there is no answer while we are in crypto mode (after sending NrAr)
525 if (bCrypto) {
526 // Failed during authentication
527 if (bAuthenticating) {
528 DbpString("Authentication failed!");
529 return false;
530 } else {
531 // Failed reading a block, could be (read/write) locked, skip block and re-authenticate
532 if (blocknr == 1) {
533 // Write the low part of the key in memory
534 memcpy(tag.sectors[1],key+2,4);
535 } else if (blocknr == 2) {
536 // Write the high part of the key in memory
537 tag.sectors[2][0] = 0x00;
538 tag.sectors[2][1] = 0x00;
539 tag.sectors[2][2] = key[0];
540 tag.sectors[2][3] = key[1];
541 } else {
542 // Just put zero's in the memory (of the unreadable block)
543 memset(tag.sectors[blocknr],0x00,4);
544 }
545 blocknr++;
546 bCrypto = false;
547 }
548 } else {
549 *txlen = 5;
550 memcpy(tx,"\xc0",nbytes(*txlen));
551 }
552 } break;
553
554 // Received UID, crypto tag answer
555 case 32: {
556 if (!bCrypto) {
557 uint64_t ui64key = key[0] | ((uint64_t)key[1]) << 8 | ((uint64_t)key[2]) << 16 | ((uint64_t)key[3]) << 24 | ((uint64_t)key[4]) << 32 | ((uint64_t)key[5]) << 40;
558 uint32_t ui32uid = rx[0] | ((uint32_t)rx[1]) << 8 | ((uint32_t)rx[2]) << 16 | ((uint32_t)rx[3]) << 24;
559 cipher_state = _hitag2_init(rev64(ui64key), rev32(ui32uid), 0);
560 memset(tx,0x00,4);
561 memset(tx+4,0xff,4);
562 hitag2_cipher_transcrypt(&cipher_state,tx+4,4,0);
563 *txlen = 64;
564 bCrypto = true;
565 bAuthenticating = true;
566 } else {
567 // Check if we received answer tag (at)
568 if (bAuthenticating) {
569 bAuthenticating = false;
570 } else {
571 // Store the received block
572 memcpy(tag.sectors[blocknr],rx,4);
573 blocknr++;
574 }
575 if (blocknr > 7) {
576 DbpString("Read succesful!");
577 bSuccessful = true;
578 return false;
579 }
580 *txlen = 10;
581 tx[0] = 0xc0 | (blocknr << 3) | ((blocknr^7) >> 2);
582 tx[1] = ((blocknr^7) << 6);
583 }
584 } break;
585
586 // Unexpected response
587 default: {
588 Dbprintf("Uknown frame length: %d",rxlen);
589 return false;
590 } break;
591 }
592
593
594 if(bCrypto) {
595 // We have to return now to avoid double encryption
596 if (!bAuthenticating) {
597 hitag2_cipher_transcrypt(&cipher_state, tx, *txlen/8, *txlen%8);
598 }
599 }
600
601 return true;
602 }
603
604
605 static bool hitag2_authenticate(byte_t* rx, const size_t rxlen, byte_t* tx, size_t* txlen) {
606 // Reset the transmission frame length
607 *txlen = 0;
608
609 // Try to find out which command was send by selecting on length (in bits)
610 switch (rxlen) {
611 // No answer, try to resurrect
612 case 0: {
613 // Stop if there is no answer while we are in crypto mode (after sending NrAr)
614 if (bCrypto) {
615 DbpString("Authentication failed!");
616 return false;
617 }
618 *txlen = 5;
619 memcpy(tx,"\xc0",nbytes(*txlen));
620 } break;
621
622 // Received UID, crypto tag answer
623 case 32: {
624 if (!bCrypto) {
625 *txlen = 64;
626 memcpy(tx,NrAr,8);
627 bCrypto = true;
628 } else {
629 DbpString("Authentication succesful!");
630 return true;
631 }
632 } break;
633
634 // Unexpected response
635 default: {
636 Dbprintf("Uknown frame length: %d",rxlen);
637 return false;
638 } break;
639 }
640
641 return true;
642 }
643
644
645 static bool hitag2_test_auth_attempts(byte_t* rx, const size_t rxlen, byte_t* tx, size_t* txlen) {
646
647 // Reset the transmission frame length
648 *txlen = 0;
649
650 // Try to find out which command was send by selecting on length (in bits)
651 switch (rxlen) {
652 // No answer, try to resurrect
653 case 0: {
654 // Stop if there is no answer while we are in crypto mode (after sending NrAr)
655 if (bCrypto) {
656 Dbprintf("auth: %02x%02x%02x%02x%02x%02x%02x%02x Failed, removed entry!",NrAr[0],NrAr[1],NrAr[2],NrAr[3],NrAr[4],NrAr[5],NrAr[6],NrAr[7]);
657
658 // Removing failed entry from authentiations table
659 memcpy(auth_table+auth_table_pos,auth_table+auth_table_pos+8,8);
660 auth_table_len -= 8;
661
662 // Return if we reached the end of the authentications table
663 bCrypto = false;
664 if (auth_table_pos == auth_table_len) {
665 return false;
666 }
667
668 // Copy the next authentication attempt in row (at the same position, b/c we removed last failed entry)
669 memcpy(NrAr,auth_table+auth_table_pos,8);
670 }
671 *txlen = 5;
672 memcpy(tx,"\xc0",nbytes(*txlen));
673 } break;
674
675 // Received UID, crypto tag answer, or read block response
676 case 32: {
677 if (!bCrypto) {
678 *txlen = 64;
679 memcpy(tx,NrAr,8);
680 bCrypto = true;
681 } else {
682 Dbprintf("auth: %02x%02x%02x%02x%02x%02x%02x%02x OK",NrAr[0],NrAr[1],NrAr[2],NrAr[3],NrAr[4],NrAr[5],NrAr[6],NrAr[7]);
683 bCrypto = false;
684 if ((auth_table_pos+8) == auth_table_len) {
685 return false;
686 }
687 auth_table_pos += 8;
688 memcpy(NrAr,auth_table+auth_table_pos,8);
689 }
690 } break;
691
692 default: {
693 Dbprintf("Uknown frame length: %d",rxlen);
694 return false;
695 } break;
696 }
697
698 return true;
699 }
700
701
702 void SnoopHitag(uint32_t type) {
703 int frame_count;
704 int response;
705 int overflow;
706 bool rising_edge;
707 bool reader_frame;
708 int lastbit;
709 bool bSkip;
710 int tag_sof;
711 byte_t rx[HITAG_FRAME_LEN];
712 size_t rxlen=0;
713
714 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
715
716 // free eventually allocated BigBuf memory
717 BigBuf_free(); BigBuf_Clear_ext(false);
718
719 // Clean up trace and prepare it for storing frames
720 clear_trace();
721 set_tracing(TRUE);
722
723 auth_table_len = 0;
724 auth_table_pos = 0;
725
726 auth_table = (byte_t *)BigBuf_malloc(AUTH_TABLE_LENGTH);
727 memset(auth_table, 0x00, AUTH_TABLE_LENGTH);
728
729 DbpString("Starting Hitag2 snoop");
730 LED_D_ON();
731
732 // Set up eavesdropping mode, frequency divisor which will drive the FPGA
733 // and analog mux selection.
734 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_TOGGLE_MODE);
735 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
736 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
737 RELAY_OFF();
738
739 // Configure output pin that is connected to the FPGA (for modulating)
740 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
741 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
742
743 // Disable modulation, we are going to eavesdrop, not modulate ;)
744 LOW(GPIO_SSC_DOUT);
745
746 // Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the reader frames
747 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
748 AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME;
749
750 // Disable timer during configuration
751 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
752
753 // Capture mode, defaul timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
754 // external trigger rising edge, load RA on rising edge of TIOA.
755 uint32_t t1_channel_mode = AT91C_TC_CLKS_TIMER_DIV1_CLOCK | AT91C_TC_ETRGEDG_BOTH | AT91C_TC_ABETRG | AT91C_TC_LDRA_BOTH;
756 AT91C_BASE_TC1->TC_CMR = t1_channel_mode;
757
758 // Enable and reset counter
759 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
760
761 // Reset the received frame, frame count and timing info
762 memset(rx,0x00,sizeof(rx));
763 frame_count = 0;
764 response = 0;
765 overflow = 0;
766 reader_frame = false;
767 lastbit = 1;
768 bSkip = true;
769 tag_sof = 4;
770
771 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
772 // Watchdog hit
773 WDT_HIT();
774
775 // Receive frame, watch for at most T0*EOF periods
776 while (AT91C_BASE_TC1->TC_CV < T0*HITAG_T_EOF) {
777 // Check if rising edge in modulation is detected
778 if(AT91C_BASE_TC1->TC_SR & AT91C_TC_LDRAS) {
779 // Retrieve the new timing values
780 int ra = (AT91C_BASE_TC1->TC_RA/T0);
781
782 // Find out if we are dealing with a rising or falling edge
783 rising_edge = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME) > 0;
784
785 // Shorter periods will only happen with reader frames
786 if (!reader_frame && rising_edge && ra < HITAG_T_TAG_CAPTURE_ONE_HALF) {
787 // Switch from tag to reader capture
788 LED_C_OFF();
789 reader_frame = true;
790 memset(rx,0x00,sizeof(rx));
791 rxlen = 0;
792 }
793
794 // Only handle if reader frame and rising edge, or tag frame and falling edge
795 if (reader_frame != rising_edge) {
796 overflow += ra;
797 continue;
798 }
799
800 // Add the buffered timing values of earlier captured edges which were skipped
801 ra += overflow;
802 overflow = 0;
803
804 if (reader_frame) {
805 LED_B_ON();
806 // Capture reader frame
807 if(ra >= HITAG_T_STOP) {
808 if (rxlen != 0) {
809 //DbpString("wierd0?");
810 }
811 // Capture the T0 periods that have passed since last communication or field drop (reset)
812 response = (ra - HITAG_T_LOW);
813 } else if(ra >= HITAG_T_1_MIN ) {
814 // '1' bit
815 rx[rxlen / 8] |= 1 << (7-(rxlen%8));
816 rxlen++;
817 } else if(ra >= HITAG_T_0_MIN) {
818 // '0' bit
819 rx[rxlen / 8] |= 0 << (7-(rxlen%8));
820 rxlen++;
821 } else {
822 // Ignore wierd value, is to small to mean anything
823 }
824 } else {
825 LED_C_ON();
826 // Capture tag frame (manchester decoding using only falling edges)
827 if(ra >= HITAG_T_EOF) {
828 if (rxlen != 0) {
829 //DbpString("wierd1?");
830 }
831 // Capture the T0 periods that have passed since last communication or field drop (reset)
832 // We always recieve a 'one' first, which has the falling edge after a half period |-_|
833 response = ra-HITAG_T_TAG_HALF_PERIOD;
834 } else if(ra >= HITAG_T_TAG_CAPTURE_FOUR_HALF) {
835 // Manchester coding example |-_|_-|-_| (101)
836 rx[rxlen / 8] |= 0 << (7-(rxlen%8));
837 rxlen++;
838 rx[rxlen / 8] |= 1 << (7-(rxlen%8));
839 rxlen++;
840 } else if(ra >= HITAG_T_TAG_CAPTURE_THREE_HALF) {
841 // Manchester coding example |_-|...|_-|-_| (0...01)
842 rx[rxlen / 8] |= 0 << (7-(rxlen%8));
843 rxlen++;
844 // We have to skip this half period at start and add the 'one' the second time
845 if (!bSkip) {
846 rx[rxlen / 8] |= 1 << (7-(rxlen%8));
847 rxlen++;
848 }
849 lastbit = !lastbit;
850 bSkip = !bSkip;
851 } else if(ra >= HITAG_T_TAG_CAPTURE_TWO_HALF) {
852 // Manchester coding example |_-|_-| (00) or |-_|-_| (11)
853 if (tag_sof) {
854 // Ignore bits that are transmitted during SOF
855 tag_sof--;
856 } else {
857 // bit is same as last bit
858 rx[rxlen / 8] |= lastbit << (7-(rxlen%8));
859 rxlen++;
860 }
861 } else {
862 // Ignore wierd value, is to small to mean anything
863 }
864 }
865 }
866 }
867
868 // Check if frame was captured
869 if(rxlen > 0) {
870 frame_count++;
871 if (!LogTraceHitag(rx,rxlen,response,0,reader_frame)) {
872 DbpString("Trace full");
873 break;
874 }
875
876 // Check if we recognize a valid authentication attempt
877 if (nbytes(rxlen) == 8) {
878 // Store the authentication attempt
879 if (auth_table_len < (AUTH_TABLE_LENGTH-8)) {
880 memcpy(auth_table+auth_table_len,rx,8);
881 auth_table_len += 8;
882 }
883 }
884
885 // Reset the received frame and response timing info
886 memset(rx,0x00,sizeof(rx));
887 response = 0;
888 reader_frame = false;
889 lastbit = 1;
890 bSkip = true;
891 tag_sof = 4;
892 overflow = 0;
893
894 LED_B_OFF();
895 LED_C_OFF();
896 } else {
897 // Save the timer overflow, will be 0 when frame was received
898 overflow += (AT91C_BASE_TC1->TC_CV/T0);
899 }
900 // Reset the frame length
901 rxlen = 0;
902 // Reset the timer to restart while-loop that receives frames
903 AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG;
904 }
905 LED_A_ON();
906 LED_B_OFF();
907 LED_C_OFF();
908 LED_D_OFF();
909 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
910 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
911 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
912 LED_A_OFF();
913 set_tracing(TRUE);
914 // Dbprintf("frame received: %d",frame_count);
915 // Dbprintf("Authentication Attempts: %d",(auth_table_len/8));
916 // DbpString("All done");
917 }
918
919 void SimulateHitagTag(bool tag_mem_supplied, byte_t* data) {
920 int frame_count;
921 int response;
922 int overflow;
923 byte_t rx[HITAG_FRAME_LEN];
924 size_t rxlen=0;
925 byte_t tx[HITAG_FRAME_LEN];
926 size_t txlen=0;
927 bool bQuitTraceFull = false;
928 bQuiet = false;
929
930 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
931
932 // free eventually allocated BigBuf memory
933 BigBuf_free(); BigBuf_Clear_ext(false);
934
935 // Clean up trace and prepare it for storing frames
936 clear_trace();
937 set_tracing(TRUE);
938
939 auth_table_len = 0;
940 auth_table_pos = 0;
941 byte_t* auth_table;
942
943 auth_table = (byte_t *)BigBuf_malloc(AUTH_TABLE_LENGTH);
944 memset(auth_table, 0x00, AUTH_TABLE_LENGTH);
945
946 DbpString("Starting Hitag2 simulation");
947 LED_D_ON();
948 hitag2_init();
949
950 if (tag_mem_supplied) {
951 DbpString("Loading hitag2 memory...");
952 memcpy((byte_t*)tag.sectors,data,48);
953 }
954
955 uint32_t block = 0;
956 for (size_t i=0; i<12; i++) {
957 for (size_t j=0; j<4; j++) {
958 block <<= 8;
959 block |= tag.sectors[i][j];
960 }
961 Dbprintf("| %d | %08x |",i,block);
962 }
963
964 // Set up simulator mode, frequency divisor which will drive the FPGA
965 // and analog mux selection.
966 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD);
967 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
968 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
969 RELAY_OFF();
970
971 // Configure output pin that is connected to the FPGA (for modulating)
972 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
973 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
974
975 // Disable modulation at default, which means release resistance
976 LOW(GPIO_SSC_DOUT);
977
978 // Enable Peripheral Clock for TIMER_CLOCK0, used to measure exact timing before answering
979 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0);
980
981 // Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the reader frames
982 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
983 AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME;
984
985 // Disable timer during configuration
986 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
987
988 // Capture mode, default timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
989 // external trigger rising edge, load RA on rising edge of TIOA.
990 AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK | AT91C_TC_ETRGEDG_RISING | AT91C_TC_ABETRG | AT91C_TC_LDRA_RISING;
991
992 // Reset the received frame, frame count and timing info
993 memset(rx,0x00,sizeof(rx));
994 frame_count = 0;
995 response = 0;
996 overflow = 0;
997
998 // Enable and reset counter
999 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
1000
1001 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
1002 // Watchdog hit
1003 WDT_HIT();
1004
1005 // Receive frame, watch for at most T0*EOF periods
1006 while (AT91C_BASE_TC1->TC_CV < T0*HITAG_T_EOF) {
1007 // Check if rising edge in modulation is detected
1008 if(AT91C_BASE_TC1->TC_SR & AT91C_TC_LDRAS) {
1009 // Retrieve the new timing values
1010 int ra = (AT91C_BASE_TC1->TC_RA/T0) + overflow;
1011 overflow = 0;
1012
1013 // Reset timer every frame, we have to capture the last edge for timing
1014 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
1015
1016 LED_B_ON();
1017
1018 // Capture reader frame
1019 if(ra >= HITAG_T_STOP) {
1020 if (rxlen != 0) {
1021 //DbpString("wierd0?");
1022 }
1023 // Capture the T0 periods that have passed since last communication or field drop (reset)
1024 response = (ra - HITAG_T_LOW);
1025 } else if(ra >= HITAG_T_1_MIN ) {
1026 // '1' bit
1027 rx[rxlen / 8] |= 1 << (7-(rxlen%8));
1028 rxlen++;
1029 } else if(ra >= HITAG_T_0_MIN) {
1030 // '0' bit
1031 rx[rxlen / 8] |= 0 << (7-(rxlen%8));
1032 rxlen++;
1033 } else {
1034 // Ignore wierd value, is to small to mean anything
1035 }
1036 }
1037 }
1038
1039 // Check if frame was captured
1040 if(rxlen > 4) {
1041 frame_count++;
1042 if (!bQuiet) {
1043 if (!LogTraceHitag(rx,rxlen,response,0,true)) {
1044 DbpString("Trace full");
1045 if (bQuitTraceFull) {
1046 break;
1047 } else {
1048 bQuiet = true;
1049 }
1050 }
1051 }
1052
1053 // Disable timer 1 with external trigger to avoid triggers during our own modulation
1054 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
1055
1056 // Process the incoming frame (rx) and prepare the outgoing frame (tx)
1057 hitag2_handle_reader_command(rx,rxlen,tx,&txlen);
1058
1059 // Wait for HITAG_T_WAIT_1 carrier periods after the last reader bit,
1060 // not that since the clock counts since the rising edge, but T_Wait1 is
1061 // with respect to the falling edge, we need to wait actually (T_Wait1 - T_Low)
1062 // periods. The gap time T_Low varies (4..10). All timer values are in
1063 // terms of T0 units
1064 while(AT91C_BASE_TC0->TC_CV < T0*(HITAG_T_WAIT_1-HITAG_T_LOW));
1065
1066 // Send and store the tag answer (if there is any)
1067 if (txlen) {
1068 // Transmit the tag frame
1069 hitag_send_frame(tx,txlen);
1070 // Store the frame in the trace
1071 if (!bQuiet) {
1072 if (!LogTraceHitag(tx,txlen,0,0,false)) {
1073 DbpString("Trace full");
1074 if (bQuitTraceFull) {
1075 break;
1076 } else {
1077 bQuiet = true;
1078 }
1079 }
1080 }
1081 }
1082
1083 // Reset the received frame and response timing info
1084 memset(rx,0x00,sizeof(rx));
1085 response = 0;
1086
1087 // Enable and reset external trigger in timer for capturing future frames
1088 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
1089 LED_B_OFF();
1090 }
1091 // Reset the frame length
1092 rxlen = 0;
1093 // Save the timer overflow, will be 0 when frame was received
1094 overflow += (AT91C_BASE_TC1->TC_CV/T0);
1095 // Reset the timer to restart while-loop that receives frames
1096 AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG;
1097 }
1098 LED_B_OFF();
1099 LED_D_OFF();
1100 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
1101 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
1102 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1103
1104 DbpString("Sim Stopped");
1105 set_tracing(TRUE);
1106 }
1107
1108 void ReaderHitag(hitag_function htf, hitag_data* htd) {
1109 int frame_count;
1110 int response;
1111 byte_t rx[HITAG_FRAME_LEN];
1112 size_t rxlen=0;
1113 byte_t txbuf[HITAG_FRAME_LEN];
1114 byte_t* tx = txbuf;
1115 size_t txlen=0;
1116 int lastbit;
1117 bool bSkip;
1118 int reset_sof;
1119 int tag_sof;
1120 int t_wait = HITAG_T_WAIT_MAX;
1121 bool bStop;
1122 bool bQuitTraceFull = false;
1123
1124 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1125 // Reset the return status
1126 bSuccessful = false;
1127
1128 // Clean up trace and prepare it for storing frames
1129 clear_trace();
1130 set_tracing(TRUE);
1131
1132 DbpString("Starting Hitag reader family");
1133
1134 // Check configuration
1135 switch(htf) {
1136 case RHT2F_PASSWORD: {
1137 Dbprintf("List identifier in password mode");
1138 memcpy(password,htd->pwd.password,4);
1139 blocknr = 0;
1140 bQuitTraceFull = false;
1141 bQuiet = false;
1142 bPwd = false;
1143 } break;
1144
1145 case RHT2F_AUTHENTICATE: {
1146 DbpString("Authenticating using nr,ar pair:");
1147 memcpy(NrAr,htd->auth.NrAr,8);
1148 Dbhexdump(8,NrAr,false);
1149 bQuiet = false;
1150 bCrypto = false;
1151 bAuthenticating = false;
1152 bQuitTraceFull = true;
1153 } break;
1154
1155 case RHT2F_CRYPTO: {
1156 DbpString("Authenticating using key:");
1157 memcpy(key,htd->crypto.key,6); //HACK; 4 or 6?? I read both in the code.
1158 Dbhexdump(6,key,false);
1159 blocknr = 0;
1160 bQuiet = false;
1161 bCrypto = false;
1162 bAuthenticating = false;
1163 bQuitTraceFull = true;
1164 } break;
1165
1166 case RHT2F_TEST_AUTH_ATTEMPTS: {
1167 Dbprintf("Testing %d authentication attempts",(auth_table_len/8));
1168 auth_table_pos = 0;
1169 memcpy(NrAr, auth_table, 8);
1170 bQuitTraceFull = false;
1171 bQuiet = false;
1172 bCrypto = false;
1173 } break;
1174
1175 default: {
1176 Dbprintf("Error, unknown function: %d",htf);
1177 set_tracing(FALSE);
1178 return;
1179 } break;
1180 }
1181
1182 LED_D_ON();
1183 hitag2_init();
1184
1185 // Configure output and enable pin that is connected to the FPGA (for modulating)
1186 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
1187 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
1188
1189 // Set fpga in edge detect with reader field, we can modulate as reader now
1190 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD);
1191
1192 // Set Frequency divisor which will drive the FPGA and analog mux selection
1193 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1194 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1195 RELAY_OFF();
1196
1197 // Disable modulation at default, which means enable the field
1198 LOW(GPIO_SSC_DOUT);
1199
1200 // Give it a bit of time for the resonant antenna to settle.
1201 SpinDelay(30);
1202
1203 // Enable Peripheral Clock for TIMER_CLOCK0, used to measure exact timing before answering
1204 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0);
1205
1206 // Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the tag frames
1207 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
1208 AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME;
1209
1210 // Disable timer during configuration
1211 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
1212
1213 // Capture mode, defaul timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
1214 // external trigger rising edge, load RA on falling edge of TIOA.
1215 AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK | AT91C_TC_ETRGEDG_FALLING | AT91C_TC_ABETRG | AT91C_TC_LDRA_FALLING;
1216
1217 // Enable and reset counters
1218 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
1219 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
1220
1221 // Reset the received frame, frame count and timing info
1222 frame_count = 0;
1223 response = 0;
1224 lastbit = 1;
1225 bStop = false;
1226
1227 // Tag specific configuration settings (sof, timings, etc.)
1228 if (htf < 10){
1229 // hitagS settings
1230 reset_sof = 1;
1231 t_wait = 200;
1232 DbpString("Configured for hitagS reader");
1233 } else if (htf < 20) {
1234 // hitag1 settings
1235 reset_sof = 1;
1236 t_wait = 200;
1237 DbpString("Configured for hitag1 reader");
1238 } else if (htf < 30) {
1239 // hitag2 settings
1240 reset_sof = 4;
1241 t_wait = HITAG_T_WAIT_2;
1242 DbpString("Configured for hitag2 reader");
1243 } else {
1244 Dbprintf("Error, unknown hitag reader type: %d",htf);
1245 set_tracing(FALSE);
1246 return;
1247 }
1248
1249 while(!bStop && !BUTTON_PRESS()) {
1250 // Watchdog hit
1251 WDT_HIT();
1252
1253 // Check if frame was captured and store it
1254 if(rxlen > 0) {
1255 frame_count++;
1256 if (!bQuiet) {
1257 if (!LogTraceHitag(rx,rxlen,response,0,false)) {
1258 DbpString("Trace full");
1259 if (bQuitTraceFull) {
1260 break;
1261 } else {
1262 bQuiet = true;
1263 }
1264 }
1265 }
1266 }
1267
1268 // By default reset the transmission buffer
1269 tx = txbuf;
1270 switch(htf) {
1271 case RHT2F_PASSWORD: {
1272 bStop = !hitag2_password(rx,rxlen,tx,&txlen);
1273 } break;
1274 case RHT2F_AUTHENTICATE: {
1275 bStop = !hitag2_authenticate(rx,rxlen,tx,&txlen);
1276 } break;
1277 case RHT2F_CRYPTO: {
1278 bStop = !hitag2_crypto(rx,rxlen,tx,&txlen);
1279 } break;
1280 case RHT2F_TEST_AUTH_ATTEMPTS: {
1281 bStop = !hitag2_test_auth_attempts(rx,rxlen,tx,&txlen);
1282 } break;
1283 default: {
1284 Dbprintf("Error, unknown function: %d",htf);
1285 set_tracing(FALSE);
1286 return;
1287 } break;
1288 }
1289
1290 // Send and store the reader command
1291 // Disable timer 1 with external trigger to avoid triggers during our own modulation
1292 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
1293
1294 // Wait for HITAG_T_WAIT_2 carrier periods after the last tag bit before transmitting,
1295 // Since the clock counts since the last falling edge, a 'one' means that the
1296 // falling edge occured halfway the period. with respect to this falling edge,
1297 // we need to wait (T_Wait2 + half_tag_period) when the last was a 'one'.
1298 // All timer values are in terms of T0 units
1299 while(AT91C_BASE_TC0->TC_CV < T0*(t_wait+(HITAG_T_TAG_HALF_PERIOD*lastbit)));
1300
1301 // Transmit the reader frame
1302 hitag_reader_send_frame(tx,txlen);
1303
1304 // Enable and reset external trigger in timer for capturing future frames
1305 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
1306
1307 // Add transmitted frame to total count
1308 if(txlen > 0) {
1309 frame_count++;
1310 if (!bQuiet) {
1311 // Store the frame in the trace
1312 if (!LogTraceHitag(tx,txlen,HITAG_T_WAIT_2,0,true)) {
1313 if (bQuitTraceFull) {
1314 break;
1315 } else {
1316 bQuiet = true;
1317 }
1318 }
1319 }
1320 }
1321
1322 // Reset values for receiving frames
1323 memset(rx,0x00,sizeof(rx));
1324 rxlen = 0;
1325 lastbit = 1;
1326 bSkip = true;
1327 tag_sof = reset_sof;
1328 response = 0;
1329
1330 // Receive frame, watch for at most T0*EOF periods
1331 while (AT91C_BASE_TC1->TC_CV < T0*HITAG_T_WAIT_MAX) {
1332 // Check if falling edge in tag modulation is detected
1333 if(AT91C_BASE_TC1->TC_SR & AT91C_TC_LDRAS) {
1334 // Retrieve the new timing values
1335 int ra = (AT91C_BASE_TC1->TC_RA/T0);
1336
1337 // Reset timer every frame, we have to capture the last edge for timing
1338 AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;
1339
1340 LED_B_ON();
1341
1342 // Capture tag frame (manchester decoding using only falling edges)
1343 if(ra >= HITAG_T_EOF) {
1344 if (rxlen != 0) {
1345 //DbpString("wierd1?");
1346 }
1347 // Capture the T0 periods that have passed since last communication or field drop (reset)
1348 // We always recieve a 'one' first, which has the falling edge after a half period |-_|
1349 response = ra-HITAG_T_TAG_HALF_PERIOD;
1350 } else if(ra >= HITAG_T_TAG_CAPTURE_FOUR_HALF) {
1351 // Manchester coding example |-_|_-|-_| (101)
1352 rx[rxlen / 8] |= 0 << (7-(rxlen%8));
1353 rxlen++;
1354 rx[rxlen / 8] |= 1 << (7-(rxlen%8));
1355 rxlen++;
1356 } else if(ra >= HITAG_T_TAG_CAPTURE_THREE_HALF) {
1357 // Manchester coding example |_-|...|_-|-_| (0...01)
1358 rx[rxlen / 8] |= 0 << (7-(rxlen%8));
1359 rxlen++;
1360 // We have to skip this half period at start and add the 'one' the second time
1361 if (!bSkip) {
1362 rx[rxlen / 8] |= 1 << (7-(rxlen%8));
1363 rxlen++;
1364 }
1365 lastbit = !lastbit;
1366 bSkip = !bSkip;
1367 } else if(ra >= HITAG_T_TAG_CAPTURE_TWO_HALF) {
1368 // Manchester coding example |_-|_-| (00) or |-_|-_| (11)
1369 if (tag_sof) {
1370 // Ignore bits that are transmitted during SOF
1371 tag_sof--;
1372 } else {
1373 // bit is same as last bit
1374 rx[rxlen / 8] |= lastbit << (7-(rxlen%8));
1375 rxlen++;
1376 }
1377 } else {
1378 // Ignore wierd value, is to small to mean anything
1379 }
1380 }
1381
1382 // We can break this loop if we received the last bit from a frame
1383 if (AT91C_BASE_TC1->TC_CV > T0*HITAG_T_EOF) {
1384 if (rxlen>0) break;
1385 }
1386 }
1387 }
1388 LED_B_OFF();
1389 LED_D_OFF();
1390 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
1391 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
1392 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1393 Dbprintf("DONE: frame received: %d",frame_count);
1394 cmd_send(CMD_ACK,bSuccessful,0,0,(byte_t*)tag.sectors,48);
1395 set_tracing(FALSE);
1396 }
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