1 //-----------------------------------------------------------------------------
2 // (c) 2009 Henryk Plötz <henryk@ploetzli.ch>
4 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
5 // at your option, any later version. See the LICENSE.txt file for the text of
7 //-----------------------------------------------------------------------------
8 // LEGIC RF simulation code
9 //-----------------------------------------------------------------------------
13 static struct legic_frame
{
24 static crc_t legic_crc
;
25 static int legic_read_count
;
26 static uint32_t legic_prng_bc
;
27 static uint32_t legic_prng_iv
;
29 static int legic_phase_drift
;
30 static int legic_frame_drift
;
31 static int legic_reqresp_drift
;
38 static void setup_timer(void) {
39 /* Set up Timer 1 to use for measuring time between pulses. Since we're bit-banging
40 * this it won't be terribly accurate but should be good enough.
42 AT91C_BASE_PMC
->PMC_PCER
= (1 << AT91C_ID_TC1
);
43 timer
= AT91C_BASE_TC1
;
44 timer
->TC_CCR
= AT91C_TC_CLKDIS
;
45 timer
->TC_CMR
= AT91C_TC_CLKS_TIMER_DIV3_CLOCK
;
46 timer
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
49 * Set up Timer 2 to use for measuring time between frames in
50 * tag simulation mode. Runs 4x faster as Timer 1
52 AT91C_BASE_PMC
->PMC_PCER
= (1 << AT91C_ID_TC2
);
53 prng_timer
= AT91C_BASE_TC2
;
54 prng_timer
->TC_CCR
= AT91C_TC_CLKDIS
;
55 prng_timer
->TC_CMR
= AT91C_TC_CLKS_TIMER_DIV2_CLOCK
;
56 prng_timer
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
59 /* At TIMER_CLOCK3 (MCK/32) */
60 #define RWD_TIME_1 150 /* RWD_TIME_PAUSE off, 80us on = 100us */
61 #define RWD_TIME_0 90 /* RWD_TIME_PAUSE off, 40us on = 60us */
62 #define RWD_TIME_PAUSE 30 /* 20us */
63 #define RWD_TIME_FUZZ 20 /* rather generous 13us, since the peak detector + hysteresis fuzz quite a bit */
64 #define TAG_TIME_BIT 150 /* 100us for every bit */
65 #define TAG_TIME_WAIT 490 /* time from RWD frame end to tag frame start, experimentally determined */
67 #define SIM_DIVISOR 586 /* prng_time/SIM_DIVISOR count prng needs to be forwared */
68 #define SIM_SHIFT 900 /* prng_time+SIM_SHIFT shift of delayed start */
70 #define SESSION_IV 0x55
71 #define OFFSET_LOG 1024
73 #define FUZZ_EQUAL(value, target, fuzz) ((value) > ((target)-(fuzz)) && (value) < ((target)+(fuzz)))
75 // ~ 258us + 100us*delay
76 #define WAIT_387 WAIT(387)
77 #define WAIT(delay) while(timer->TC_CV < (delay) );
80 // ToDo: define a meaningful maximum size for auth_table. The bigger this is, the lower will be the available memory for traces.
81 // Historically it used to be FREE_BUFFER_SIZE, which was 2744.
82 #define LEGIC_CARD_MEMSIZE 1024
83 static uint8_t* cardmem
;
88 // 32 bits timestamp (little endian)
89 // 16 bits duration (little endian)
90 // 16 bits data length (little endian, Highest Bit used as readerToTag flag)
92 // x Bytes parity (one byte per 8 bytes data)
95 /* Generate Keystream */
96 static uint32_t get_key_stream(int skip
, int count
)
101 // Use int to enlarge timer tc to 32bit
102 legic_prng_bc
+= prng_timer
->TC_CV
;
104 // reset the prng timer.
105 prng_timer
->TC_CCR
= AT91C_TC_SWTRG
;
106 while(prng_timer
->TC_CV
> 1) ;
108 /* If skip == -1, forward prng time based */
110 i
= (legic_prng_bc
+ SIM_SHIFT
)/SIM_DIVISOR
; /* Calculate Cycles based on timer */
111 i
-= legic_prng_count(); /* substract cycles of finished frames */
112 i
-= count
; /* substract current frame length, rewind to beginning */
113 legic_prng_forward(i
);
115 legic_prng_forward(skip
);
118 i
= (count
== 6) ? -1 : legic_read_count
;
120 /* Write Time Data into LOG */
121 // uint8_t *BigBuf = BigBuf_get_addr();
122 // BigBuf[OFFSET_LOG+128+i] = legic_prng_count();
123 // BigBuf[OFFSET_LOG+256+i*4] = (legic_prng_bc >> 0) & 0xff;
124 // BigBuf[OFFSET_LOG+256+i*4+1] = (legic_prng_bc >> 8) & 0xff;
125 // BigBuf[OFFSET_LOG+256+i*4+2] = (legic_prng_bc >>16) & 0xff;
126 // BigBuf[OFFSET_LOG+256+i*4+3] = (legic_prng_bc >>24) & 0xff;
127 // BigBuf[OFFSET_LOG+384+i] = count;
129 /* Generate KeyStream */
130 for(i
=0; i
<count
; i
++) {
131 key
|= legic_prng_get_bit() << i
;
132 legic_prng_forward(1);
137 /* Send a frame in tag mode, the FPGA must have been set up by
140 static void frame_send_tag(uint16_t response
, int bits
, int crypt
)
142 /* Bitbang the response */
143 AT91C_BASE_PIOA
->PIO_CODR
= GPIO_SSC_DOUT
;
144 AT91C_BASE_PIOA
->PIO_OER
= GPIO_SSC_DOUT
;
145 AT91C_BASE_PIOA
->PIO_PER
= GPIO_SSC_DOUT
;
147 /* Use time to crypt frame */
149 legic_prng_forward(2); /* TAG_TIME_WAIT -> shift by 2 */
151 for(int i
= 0; i
< bits
; i
++) {
152 key
|= legic_prng_get_bit() << i
;
153 legic_prng_forward(1);
155 response
= response
^ key
;
158 /* Wait for the frame start */
159 //while(timer->TC_CV < (TAG_TIME_WAIT - 30)) ;
160 WAIT( TAG_TIME_WAIT
- 30)
163 for(int i
= 0; i
< bits
; i
++) {
164 int nextbit
= timer
->TC_CV
+ TAG_TIME_BIT
;
169 AT91C_BASE_PIOA
->PIO_SODR
= GPIO_SSC_DOUT
;
171 AT91C_BASE_PIOA
->PIO_CODR
= GPIO_SSC_DOUT
;
173 //while(timer->TC_CV < nextbit) ;
176 AT91C_BASE_PIOA
->PIO_CODR
= GPIO_SSC_DOUT
;
179 // Starts Clock and waits until its reset
180 static void ResetClock(void){
181 timer
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
182 while(timer
->TC_CV
> 1) ;
185 /* Send a frame in reader mode, the FPGA must have been set up by
188 static void frame_send_rwd(uint32_t data
, int bits
){
191 int starttime
= 0, pause_end
= 0, bit
= 0, bit_end
= 0;
193 for(int i
= 0; i
<bits
; i
++) {
195 starttime
= timer
->TC_CV
;
196 pause_end
= starttime
+ RWD_TIME_PAUSE
;
200 if(bit
^ legic_prng_get_bit())
201 bit_end
= starttime
+ RWD_TIME_1
;
203 bit_end
= starttime
+ RWD_TIME_0
;
206 /* RWD_TIME_PAUSE time off, then some time on, so that the complete bit time is
207 * RWD_TIME_x, where x is the bit to be transmitted */
208 AT91C_BASE_PIOA
->PIO_CODR
= GPIO_SSC_DOUT
;
212 AT91C_BASE_PIOA
->PIO_SODR
= GPIO_SSC_DOUT
;
214 legic_prng_forward(1); /* bit duration is longest. use this time to forward the lfsr */
219 /* One final pause to mark the end of the frame */
220 pause_end
= timer
->TC_CV
+ RWD_TIME_PAUSE
;
222 AT91C_BASE_PIOA
->PIO_CODR
= GPIO_SSC_DOUT
;
226 AT91C_BASE_PIOA
->PIO_SODR
= GPIO_SSC_DOUT
;
228 /* Reset the timer, to measure time until the start of the tag frame */
232 /* Receive a frame from the card in reader emulation mode, the FPGA and
233 * timer must have been set up by LegicRfReader and frame_send_rwd.
235 * The LEGIC RF protocol from card to reader does not include explicit
236 * frame start/stop information or length information. The reader must
237 * know beforehand how many bits it wants to receive. (Notably: a card
238 * sending a stream of 0-bits is indistinguishable from no card present.)
240 * Receive methodology: There is a fancy correlator in hi_read_rx_xcorr, but
241 * I'm not smart enough to use it. Instead I have patched hi_read_tx to output
242 * the ADC signal with hysteresis on SSP_DIN. Bit-bang that signal and look
243 * for edges. Count the edges in each bit interval. If they are approximately
244 * 0 this was a 0-bit, if they are approximately equal to the number of edges
245 * expected for a 212kHz subcarrier, this was a 1-bit. For timing we use the
246 * timer that's still running from frame_send_rwd in order to get a synchronization
247 * with the frame that we just sent.
249 * FIXME: Because we're relying on the hysteresis to just do the right thing
250 * the range is severely reduced (and you'll probably also need a good antenna).
251 * So this should be fixed some time in the future for a proper receiver.
253 static void frame_receive_rwd(struct legic_frame
* const f
, int bits
, int crypt
)
255 uint32_t the_bit
= 1; /* Use a bitmask to save on shifts */
257 int i
, old_level
= 0, edges
= 0;
258 int next_bit_at
= TAG_TIME_WAIT
;
260 if(bits
> 32) bits
= 32;
262 AT91C_BASE_PIOA
->PIO_ODR
= GPIO_SSC_DIN
;
263 AT91C_BASE_PIOA
->PIO_PER
= GPIO_SSC_DIN
;
265 /* we have some time now, precompute the cipher
266 * since we cannot compute it on the fly while reading */
267 legic_prng_forward(2);
270 for(i
=0; i
<bits
; i
++) {
271 data
|= legic_prng_get_bit() << i
;
272 legic_prng_forward(1);
278 next_bit_at
+= TAG_TIME_BIT
;
280 for(i
=0; i
<bits
; i
++) {
282 while(timer
->TC_CV
< next_bit_at
) {
283 int level
= (AT91C_BASE_PIOA
->PIO_PDSR
& GPIO_SSC_DIN
);
284 if(level
!= old_level
)
288 next_bit_at
+= TAG_TIME_BIT
;
290 // We expect 42 edges
291 if(edges
> 20 && edges
< 60) {
300 // Reset the timer, to synchronize the next frame
304 static void frame_append_bit(struct legic_frame
* const f
, int bit
) {
305 // Overflow, won't happen
306 if (f
->bits
>= 31) return;
308 f
->data
|= (bit
<< f
->bits
);
312 static void frame_clean(struct legic_frame
* const f
) {
317 // Setup pm3 as a Legic Reader
318 static uint32_t perform_setup_phase_rwd(int iv
) {
319 /* Switch on carrier and let the tag charge for 1ms */
320 AT91C_BASE_PIOA
->PIO_SODR
= GPIO_SSC_DOUT
;
321 SpinDelay(20); // was 1ms before.
323 /* no keystream yet */
327 frame_send_rwd(iv
, 7);
330 frame_clean(¤t_frame
);
331 frame_receive_rwd(¤t_frame
, 6, 1);
334 legic_prng_forward(3);
338 frame_send_rwd(0x39, 6);
340 return current_frame
.data
;
343 static void LegicCommonInit(void) {
345 FpgaDownloadAndGo(FPGA_BITSTREAM_HF
);
346 SetAdcMuxFor(GPIO_MUXSEL_HIPKD
);
348 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX
);
350 /* Bitbang the transmitter */
351 AT91C_BASE_PIOA
->PIO_CODR
= GPIO_SSC_DOUT
;
352 AT91C_BASE_PIOA
->PIO_OER
= GPIO_SSC_DOUT
;
353 AT91C_BASE_PIOA
->PIO_PER
= GPIO_SSC_DOUT
;
355 // reserve a cardmem, meaning we can use the tracelog function in bigbuff easier.
356 cardmem
= BigBuf_malloc(LEGIC_CARD_MEMSIZE
);
357 memset(cardmem
, 0x00, LEGIC_CARD_MEMSIZE
);
364 crc_init(&legic_crc
, 4, 0x19 >> 1, 0x5, 0);
367 /* Switch off carrier, make sure tag is reset */
368 static void switch_off_tag_rwd(void) {
369 AT91C_BASE_PIOA
->PIO_CODR
= GPIO_SSC_DOUT
;
374 /* calculate crc for a legic command */
375 static int LegicCRC(int byte_index
, int value
, int cmd_sz
) {
376 crc_clear(&legic_crc
);
377 crc_update(&legic_crc
, 1, 1); /* CMD_READ */
378 crc_update(&legic_crc
, byte_index
, cmd_sz
-1);
379 crc_update(&legic_crc
, value
, 8);
380 return crc_finish(&legic_crc
);
383 int legic_read_byte(int byte_index
, int cmd_sz
) {
385 int byte
= 0, calcCrc
= 0, crc
= 0;
386 int cmd
= 1 | (byte_index
<< 1);
388 uint8_t cmdbytes
[2] = {cmd
&& 0xff, (cmd
>> 8 ) & 0xFF};
389 uint32_t starttime
= timer
->TC_CV
, endtime
= 0;
394 frame_send_rwd(cmd
, cmd_sz
);
397 endtime
= timer
->TC_CV
;
398 LogTrace(cmdbytes
, 2, starttime
, endtime
, NULL
, TRUE
);
401 frame_clean(¤t_frame
);
403 starttime
= timer
->TC_CV
;
406 frame_receive_rwd(¤t_frame
, 12, 1);
409 endtime
= timer
->TC_CV
;
410 cmdbytes
[0] = current_frame
.data
& 0xff;
411 cmdbytes
[1] = (current_frame
.data
>> 8) & 0xFF;
412 LogTrace(cmdbytes
, 2, starttime
, endtime
, NULL
, FALSE
);
414 byte
= current_frame
.data
& 0xff;
415 calcCrc
= LegicCRC(byte_index
, byte
, cmd_sz
);
416 crc
= (current_frame
.data
>> 8);
418 if( calcCrc
!= crc
) {
419 Dbprintf("!!! crc mismatch: expected %x but got %x !!!", calcCrc
, crc
);
424 legic_prng_forward(4);
429 * - assemble a write_cmd_frame with crc and send it
430 * - wait until the tag sends back an ACK ('1' bit unencrypted)
431 * - forward the prng based on the timing
433 //int legic_write_byte(int byte, int addr, int addr_sz, int PrngCorrection) {
434 int legic_write_byte(int byte
, int addr
, int addr_sz
) {
436 //do not write UID, CRC at offset 0-4.
437 if(addr
<= 0x04) return 0;
440 crc_clear(&legic_crc
);
441 crc_update(&legic_crc
, 0, 1); /* CMD_WRITE */
442 crc_update(&legic_crc
, addr
, addr_sz
);
443 crc_update(&legic_crc
, byte
, 8);
444 uint32_t crc
= crc_finish(&legic_crc
);
446 // send write command
447 uint32_t cmd
= ((crc
<<(addr_sz
+1+8)) //CRC
448 |(byte
<<(addr_sz
+1)) //Data
449 |(addr
<<1) //Address
450 |(0x00 <<0)); //CMD = W
451 uint32_t cmd_sz
= addr_sz
+1+8+4; //crc+data+cmd
453 legic_prng_forward(2); /* we wait anyways */
455 while(timer
->TC_CV
< 387) ; /* ~ 258us */
457 frame_send_rwd(cmd
, cmd_sz
);
459 // wllm-rbnt doesnt have these
460 // AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
461 // AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
464 int t
, old_level
= 0, edges
= 0;
467 while(timer
->TC_CV
< 387) ; /* ~ 258us */
469 for( t
= 0; t
< 80; t
++) {
471 next_bit_at
+= TAG_TIME_BIT
;
472 while(timer
->TC_CV
< next_bit_at
) {
473 int level
= (AT91C_BASE_PIOA
->PIO_PDSR
& GPIO_SSC_DIN
);
474 if(level
!= old_level
) {
479 if(edges
> 20 && edges
< 60) { /* expected are 42 edges */
480 int t
= timer
->TC_CV
;
481 int c
= t
/ TAG_TIME_BIT
;
484 legic_prng_forward(c
);
493 int LegicRfReader(int offset
, int bytes
, int iv
) {
495 // ice_legic_setup();
496 // ice_legic_select_card();
499 int byte_index
= 0, cmd_sz
= 0, card_sz
= 0;
501 iv
= (iv
<= 0 ) ? SESSION_IV
: iv
;
505 if ( MF_DBGLEVEL
>= 2) DbpString("setting up legic card");
507 uint32_t tag_type
= perform_setup_phase_rwd(iv
);
509 //we lose to mutch time with dprintf
510 switch_off_tag_rwd();
514 if ( MF_DBGLEVEL
>= 2) DbpString("MIM22 card found, reading card ...");
519 if ( MF_DBGLEVEL
>= 2) DbpString("MIM256 card found, reading card ...");
524 if ( MF_DBGLEVEL
>= 2) DbpString("MIM1024 card found, reading card ...");
529 if ( MF_DBGLEVEL
>= 1) Dbprintf("Unknown card format: %x",tag_type
);
535 if(bytes
+offset
>= card_sz
)
536 bytes
= card_sz
- offset
;
538 perform_setup_phase_rwd(iv
);
540 legic_prng_forward(2);
543 while(byte_index
< bytes
) {
544 int r
= legic_read_byte(byte_index
+offset
, cmd_sz
);
545 if(r
== -1 || BUTTON_PRESS()) {
546 switch_off_tag_rwd();
548 if ( MF_DBGLEVEL
>= 2) DbpString("operation aborted");
551 cardmem
[byte_index
] = r
;
556 switch_off_tag_rwd();
559 if ( MF_DBGLEVEL
>= 1) Dbprintf("Card read, use 'hf legic decode' or");
560 if ( MF_DBGLEVEL
>= 1) Dbprintf("'data hexsamples %d' to view results", (bytes
+7) & ~7);
564 /*int _LegicRfWriter(int offset, int bytes, int addr_sz, uint8_t *BigBuf, int RoundBruteforceValue) {
568 perform_setup_phase_rwd(SESSION_IV);
569 //legic_prng_forward(2);
570 while(byte_index < bytes) {
573 //check if the DCF should be changed
574 if ( (offset == 0x05) && (bytes == 0x02) ) {
575 //write DCF in reverse order (addr 0x06 before 0x05)
576 r = legic_write_byte(BigBuf[(0x06-byte_index)], (0x06-byte_index), addr_sz, RoundBruteforceValue);
577 //legic_prng_forward(1);
580 r = legic_write_byte(BigBuf[(0x06-byte_index)], (0x06-byte_index), addr_sz, RoundBruteforceValue);
582 //legic_prng_forward(1);
585 r = legic_write_byte(BigBuf[byte_index+offset], byte_index+offset, addr_sz, RoundBruteforceValue);
587 if((r != 0) || BUTTON_PRESS()) {
588 Dbprintf("operation aborted @ 0x%03.3x", byte_index);
589 switch_off_tag_rwd();
597 if(byte_index & 0x10) LED_C_ON(); else LED_C_OFF();
601 DbpString("write successful");
605 void LegicRfWriter(int offset
, int bytes
, int iv
) {
607 int byte_index
= 0, addr_sz
= 0;
609 iv
= (iv
<=0 ) ? SESSION_IV
: iv
;
613 if ( MF_DBGLEVEL
>= 2) DbpString("setting up legic card");
615 uint32_t tag_type
= perform_setup_phase_rwd(iv
);
617 switch_off_tag_rwd();
621 if(offset
+bytes
> 22) {
622 Dbprintf("Error: can not write to 0x%03.3x on MIM22", offset
+bytes
);
626 if ( MF_DBGLEVEL
>= 2) Dbprintf("MIM22 card found, writing 0x%02.2x - 0x%02.2x ...", offset
, offset
+bytes
);
629 if(offset
+bytes
> 0x100) {
630 Dbprintf("Error: can not write to 0x%03.3x on MIM256", offset
+bytes
);
634 if ( MF_DBGLEVEL
>= 2) Dbprintf("MIM256 card found, writing 0x%02.2x - 0x%02.2x ...", offset
, offset
+bytes
);
637 if(offset
+bytes
> 0x400) {
638 Dbprintf("Error: can not write to 0x%03.3x on MIM1024", offset
+bytes
);
642 if ( MF_DBGLEVEL
>= 2) Dbprintf("MIM1024 card found, writing 0x%03.3x - 0x%03.3x ...", offset
, offset
+bytes
);
645 Dbprintf("No or unknown card found, aborting");
650 perform_setup_phase_rwd(iv
);
651 while(byte_index
< bytes
) {
654 //check if the DCF should be changed
655 if ( ((byte_index
+offset
) == 0x05) && (bytes
>= 0x02) ) {
656 //write DCF in reverse order (addr 0x06 before 0x05)
657 r
= legic_write_byte(cardmem
[(0x06-byte_index
)], (0x06-byte_index
), addr_sz
);
659 // write second byte on success...
662 r
= legic_write_byte(cardmem
[(0x06-byte_index
)], (0x06-byte_index
), addr_sz
);
666 r
= legic_write_byte(cardmem
[byte_index
+offset
], byte_index
+offset
, addr_sz
);
669 if((r
!= 0) || BUTTON_PRESS()) {
670 Dbprintf("operation aborted @ 0x%03.3x", byte_index
);
671 switch_off_tag_rwd();
680 if ( MF_DBGLEVEL
>= 1) DbpString("write successful");
683 void LegicRfRawWriter(int address
, int byte
, int iv
) {
685 int byte_index
= 0, addr_sz
= 0;
687 iv
= (iv
<= 0) ? SESSION_IV
: iv
;
691 if ( MF_DBGLEVEL
>= 2) DbpString("setting up legic card");
693 uint32_t tag_type
= perform_setup_phase_rwd(iv
);
695 switch_off_tag_rwd();
700 Dbprintf("Error: can not write to 0x%03.3x on MIM22", address
);
704 if ( MF_DBGLEVEL
>= 2) Dbprintf("MIM22 card found, writing at addr 0x%02.2x - value 0x%02.2x ...", address
, byte
);
707 if(address
> 0x100) {
708 Dbprintf("Error: can not write to 0x%03.3x on MIM256", address
);
712 if ( MF_DBGLEVEL
>= 2) Dbprintf("MIM256 card found, writing at addr 0x%02.2x - value 0x%02.2x ...", address
, byte
);
715 if(address
> 0x400) {
716 Dbprintf("Error: can not write to 0x%03.3x on MIM1024", address
);
720 if ( MF_DBGLEVEL
>= 2) Dbprintf("MIM1024 card found, writing at addr 0x%03.3x - value 0x%03.3x ...", address
, byte
);
723 Dbprintf("No or unknown card found, aborting");
727 Dbprintf("integer value: %d address: %d addr_sz: %d", byte
, address
, addr_sz
);
730 perform_setup_phase_rwd(iv
);
731 //legic_prng_forward(2);
733 int r
= legic_write_byte(byte
, address
, addr_sz
);
735 if((r
!= 0) || BUTTON_PRESS()) {
736 Dbprintf("operation aborted @ 0x%03.3x (%1d)", byte_index
, r
);
737 switch_off_tag_rwd();
743 if ( MF_DBGLEVEL
>= 1) DbpString("write successful");
746 /* Handle (whether to respond) a frame in tag mode
747 * Only called when simulating a tag.
749 static void frame_handle_tag(struct legic_frame
const * const f
)
751 uint8_t *BigBuf
= BigBuf_get_addr();
753 /* First Part of Handshake (IV) */
758 prng_timer
->TC_CCR
= AT91C_TC_SWTRG
;
759 while(prng_timer
->TC_CV
> 1) ;
761 legic_prng_init(f
->data
);
762 frame_send_tag(0x3d, 6, 1); /* 0x3d^0x26 = 0x1b */
763 legic_state
= STATE_IV
;
764 legic_read_count
= 0;
766 legic_prng_iv
= f
->data
;
771 //while(timer->TC_CV < 280);
777 if(legic_state
== STATE_IV
) {
778 int local_key
= get_key_stream(3, 6);
779 int xored
= 0x39 ^ local_key
;
780 if((f
->bits
== 6) && (f
->data
== xored
)) {
781 legic_state
= STATE_CON
;
786 //while(timer->TC_CV < 200);
791 legic_state
= STATE_DISCON
;
793 Dbprintf("iv: %02x frame: %02x key: %02x xored: %02x", legic_prng_iv
, f
->data
, local_key
, xored
);
800 if(legic_state
== STATE_CON
) {
801 int key
= get_key_stream(2, 11); //legic_phase_drift, 11);
802 int addr
= f
->data
^ key
; addr
= addr
>> 1;
803 int data
= BigBuf
[addr
];
804 int hash
= LegicCRC(addr
, data
, 11) << 8;
805 BigBuf
[OFFSET_LOG
+legic_read_count
] = (uint8_t)addr
;
808 //Dbprintf("Data:%03.3x, key:%03.3x, addr: %03.3x, read_c:%u", f->data, key, addr, read_c);
809 legic_prng_forward(legic_reqresp_drift
);
811 frame_send_tag(hash
| data
, 12, 1);
816 legic_prng_forward(2);
817 //while(timer->TC_CV < 180);
826 int key
= get_key_stream(-1, 23); //legic_frame_drift, 23);
827 int addr
= f
->data
^ key
; addr
= addr
>> 1; addr
= addr
& 0x3ff;
828 int data
= f
->data
^ key
; data
= data
>> 11; data
= data
& 0xff;
831 legic_state
= STATE_DISCON
;
833 Dbprintf("write - addr: %x, data: %x", addr
, data
);
837 if(legic_state
!= STATE_DISCON
) {
838 Dbprintf("Unexpected: sz:%u, Data:%03.3x, State:%u, Count:%u", f
->bits
, f
->data
, legic_state
, legic_read_count
);
840 Dbprintf("IV: %03.3x", legic_prng_iv
);
841 for(i
= 0; i
<legic_read_count
; i
++) {
842 Dbprintf("Read Nb: %u, Addr: %u", i
, BigBuf
[OFFSET_LOG
+i
]);
845 for(i
= -1; i
<legic_read_count
; i
++) {
847 t
= BigBuf
[OFFSET_LOG
+256+i
*4];
848 t
|= BigBuf
[OFFSET_LOG
+256+i
*4+1] << 8;
849 t
|= BigBuf
[OFFSET_LOG
+256+i
*4+2] <<16;
850 t
|= BigBuf
[OFFSET_LOG
+256+i
*4+3] <<24;
852 Dbprintf("Cycles: %u, Frame Length: %u, Time: %u",
853 BigBuf
[OFFSET_LOG
+128+i
],
854 BigBuf
[OFFSET_LOG
+384+i
],
858 legic_state
= STATE_DISCON
;
859 legic_read_count
= 0;
865 /* Read bit by bit untill full frame is received
866 * Call to process frame end answer
868 static void emit(int bit
) {
872 frame_append_bit(¤t_frame
, 1);
875 frame_append_bit(¤t_frame
, 0);
878 if(current_frame
.bits
<= 4) {
879 frame_clean(¤t_frame
);
881 frame_handle_tag(¤t_frame
);
882 frame_clean(¤t_frame
);
889 void LegicRfSimulate(int phase
, int frame
, int reqresp
)
891 /* ADC path high-frequency peak detector, FPGA in high-frequency simulator mode,
892 * modulation mode set to 212kHz subcarrier. We are getting the incoming raw
893 * envelope waveform on DIN and should send our response on DOUT.
895 * The LEGIC RF protocol is pulse-pause-encoding from reader to card, so we'll
896 * measure the time between two rising edges on DIN, and no encoding on the
897 * subcarrier from card to reader, so we'll just shift out our verbatim data
898 * on DOUT, 1 bit is 100us. The time from reader to card frame is still unclear,
899 * seems to be 300us-ish.
902 legic_phase_drift
= phase
;
903 legic_frame_drift
= frame
;
904 legic_reqresp_drift
= reqresp
;
906 FpgaDownloadAndGo(FPGA_BITSTREAM_HF
);
907 SetAdcMuxFor(GPIO_MUXSEL_HIPKD
);
909 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR
| FPGA_HF_SIMULATOR_MODULATE_212K
);
911 /* Bitbang the receiver */
912 AT91C_BASE_PIOA
->PIO_ODR
= GPIO_SSC_DIN
;
913 AT91C_BASE_PIOA
->PIO_PER
= GPIO_SSC_DIN
;
916 crc_init(&legic_crc
, 4, 0x19 >> 1, 0x5, 0);
920 legic_state
= STATE_DISCON
;
923 DbpString("Starting Legic emulator, press button to end");
925 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
926 int level
= !!(AT91C_BASE_PIOA
->PIO_PDSR
& GPIO_SSC_DIN
);
927 int time
= timer
->TC_CV
;
929 if(level
!= old_level
) {
931 timer
->TC_CCR
= AT91C_TC_CLKEN
| AT91C_TC_SWTRG
;
933 if (FUZZ_EQUAL(time
, RWD_TIME_1
, RWD_TIME_FUZZ
)) {
938 } else if (FUZZ_EQUAL(time
, RWD_TIME_0
, RWD_TIME_FUZZ
)) {
953 if(time
>= (RWD_TIME_1
+RWD_TIME_FUZZ
) && active
) {
959 if(time
>= (20*RWD_TIME_1
) && (timer
->TC_SR
& AT91C_TC_CLKSTA
)) {
960 timer
->TC_CCR
= AT91C_TC_CLKDIS
;
966 if ( MF_DBGLEVEL
>= 1) DbpString("Stopped");
970 //-----------------------------------------------------------------------------
971 //-----------------------------------------------------------------------------
974 //-----------------------------------------------------------------------------
975 // Code up a string of octets at layer 2 (including CRC, we don't generate
976 // that here) so that they can be transmitted to the reader. Doesn't transmit
977 // them yet, just leaves them ready to send in ToSend[].
978 //-----------------------------------------------------------------------------
979 // static void CodeLegicAsTag(const uint8_t *cmd, int len)
985 // // Transmit a burst of ones, as the initial thing that lets the
986 // // reader get phase sync. This (TR1) must be > 80/fs, per spec,
987 // // but tag that I've tried (a Paypass) exceeds that by a fair bit,
989 // for(i = 0; i < 20; i++) {
990 // ToSendStuffBit(1);
991 // ToSendStuffBit(1);
992 // ToSendStuffBit(1);
993 // ToSendStuffBit(1);
997 // for(i = 0; i < 10; i++) {
998 // ToSendStuffBit(0);
999 // ToSendStuffBit(0);
1000 // ToSendStuffBit(0);
1001 // ToSendStuffBit(0);
1003 // for(i = 0; i < 2; i++) {
1004 // ToSendStuffBit(1);
1005 // ToSendStuffBit(1);
1006 // ToSendStuffBit(1);
1007 // ToSendStuffBit(1);
1010 // for(i = 0; i < len; i++) {
1012 // uint8_t b = cmd[i];
1015 // ToSendStuffBit(0);
1016 // ToSendStuffBit(0);
1017 // ToSendStuffBit(0);
1018 // ToSendStuffBit(0);
1021 // for(j = 0; j < 8; j++) {
1023 // ToSendStuffBit(1);
1024 // ToSendStuffBit(1);
1025 // ToSendStuffBit(1);
1026 // ToSendStuffBit(1);
1028 // ToSendStuffBit(0);
1029 // ToSendStuffBit(0);
1030 // ToSendStuffBit(0);
1031 // ToSendStuffBit(0);
1037 // ToSendStuffBit(1);
1038 // ToSendStuffBit(1);
1039 // ToSendStuffBit(1);
1040 // ToSendStuffBit(1);
1044 // for(i = 0; i < 10; i++) {
1045 // ToSendStuffBit(0);
1046 // ToSendStuffBit(0);
1047 // ToSendStuffBit(0);
1048 // ToSendStuffBit(0);
1050 // for(i = 0; i < 2; i++) {
1051 // ToSendStuffBit(1);
1052 // ToSendStuffBit(1);
1053 // ToSendStuffBit(1);
1054 // ToSendStuffBit(1);
1057 // // Convert from last byte pos to length
1061 //-----------------------------------------------------------------------------
1062 // The software UART that receives commands from the reader, and its state
1064 //-----------------------------------------------------------------------------
1068 STATE_GOT_FALLING_EDGE_OF_SOF
,
1069 STATE_AWAITING_START_BIT
,
1070 STATE_RECEIVING_DATA
1080 /* Receive & handle a bit coming from the reader.
1082 * This function is called 4 times per bit (every 2 subcarrier cycles).
1083 * Subcarrier frequency fs is 212kHz, 1/fs = 4,72us, i.e. function is called every 9,44us
1086 * LED A -> ON once we have received the SOF and are expecting the rest.
1087 * LED A -> OFF once we have received EOF or are in error state or unsynced
1089 * Returns: true if we received a EOF
1090 * false if we are still waiting for some more
1092 // static RAMFUNC int HandleLegicUartBit(uint8_t bit)
1094 // switch(Uart.state) {
1095 // case STATE_UNSYNCD:
1097 // // we went low, so this could be the beginning of an SOF
1098 // Uart.state = STATE_GOT_FALLING_EDGE_OF_SOF;
1104 // case STATE_GOT_FALLING_EDGE_OF_SOF:
1106 // if(Uart.posCnt == 2) { // sample every 4 1/fs in the middle of a bit
1108 // if(Uart.bitCnt > 9) {
1109 // // we've seen enough consecutive
1110 // // zeros that it's a valid SOF
1112 // Uart.byteCnt = 0;
1113 // Uart.state = STATE_AWAITING_START_BIT;
1114 // LED_A_ON(); // Indicate we got a valid SOF
1116 // // didn't stay down long enough
1117 // // before going high, error
1118 // Uart.state = STATE_UNSYNCD;
1121 // // do nothing, keep waiting
1125 // if(Uart.posCnt >= 4) Uart.posCnt = 0;
1126 // if(Uart.bitCnt > 12) {
1127 // // Give up if we see too many zeros without
1130 // Uart.state = STATE_UNSYNCD;
1134 // case STATE_AWAITING_START_BIT:
1137 // if(Uart.posCnt > 50/2) { // max 57us between characters = 49 1/fs, max 3 etus after low phase of SOF = 24 1/fs
1138 // // stayed high for too long between
1139 // // characters, error
1140 // Uart.state = STATE_UNSYNCD;
1143 // // falling edge, this starts the data byte
1146 // Uart.shiftReg = 0;
1147 // Uart.state = STATE_RECEIVING_DATA;
1151 // case STATE_RECEIVING_DATA:
1153 // if(Uart.posCnt == 2) {
1154 // // time to sample a bit
1155 // Uart.shiftReg >>= 1;
1157 // Uart.shiftReg |= 0x200;
1161 // if(Uart.posCnt >= 4) {
1164 // if(Uart.bitCnt == 10) {
1165 // if((Uart.shiftReg & 0x200) && !(Uart.shiftReg & 0x001))
1167 // // this is a data byte, with correct
1168 // // start and stop bits
1169 // Uart.output[Uart.byteCnt] = (Uart.shiftReg >> 1) & 0xff;
1172 // if(Uart.byteCnt >= Uart.byteCntMax) {
1173 // // Buffer overflowed, give up
1175 // Uart.state = STATE_UNSYNCD;
1177 // // so get the next byte now
1179 // Uart.state = STATE_AWAITING_START_BIT;
1181 // } else if (Uart.shiftReg == 0x000) {
1182 // // this is an EOF byte
1183 // LED_A_OFF(); // Finished receiving
1184 // Uart.state = STATE_UNSYNCD;
1185 // if (Uart.byteCnt != 0) {
1189 // // this is an error
1191 // Uart.state = STATE_UNSYNCD;
1198 // Uart.state = STATE_UNSYNCD;
1206 static void UartReset()
1208 Uart
.byteCntMax
= MAX_FRAME_SIZE
;
1209 Uart
.state
= STATE_UNSYNCD
;
1213 memset(Uart
.output
, 0x00, MAX_FRAME_SIZE
);
1216 // static void UartInit(uint8_t *data)
1218 // Uart.output = data;
1222 //=============================================================================
1223 // An LEGIC reader. We take layer two commands, code them
1224 // appropriately, and then send them to the tag. We then listen for the
1225 // tag's response, which we leave in the buffer to be demodulated on the
1227 //=============================================================================
1232 DEMOD_PHASE_REF_TRAINING
,
1233 DEMOD_AWAITING_FALLING_EDGE_OF_SOF
,
1234 DEMOD_GOT_FALLING_EDGE_OF_SOF
,
1235 DEMOD_AWAITING_START_BIT
,
1236 DEMOD_RECEIVING_DATA
1249 * Handles reception of a bit from the tag
1251 * This function is called 2 times per bit (every 4 subcarrier cycles).
1252 * Subcarrier frequency fs is 212kHz, 1/fs = 4,72us, i.e. function is called every 9,44us
1255 * LED C -> ON once we have received the SOF and are expecting the rest.
1256 * LED C -> OFF once we have received EOF or are unsynced
1258 * Returns: true if we received a EOF
1259 * false if we are still waiting for some more
1263 #ifndef SUBCARRIER_DETECT_THRESHOLD
1264 # define SUBCARRIER_DETECT_THRESHOLD 8
1267 // Subcarrier amplitude v = sqrt(ci^2 + cq^2), approximated here by max(abs(ci),abs(cq)) + 1/2*min(abs(ci),abs(cq)))
1268 #ifndef CHECK_FOR_SUBCARRIER
1269 # define CHECK_FOR_SUBCARRIER() { v = MAX(ai, aq) + MIN(halfci, halfcq); }
1272 // The soft decision on the bit uses an estimate of just the
1273 // quadrant of the reference angle, not the exact angle.
1274 // Subcarrier amplitude v = sqrt(ci^2 + cq^2), approximated here by max(abs(ci),abs(cq)) + 1/2*min(abs(ci),abs(cq)))
1275 #define MAKE_SOFT_DECISION() { \
1276 if(Demod.sumI > 0) \
1281 if(Demod.sumQ > 0) \
1288 static RAMFUNC
int HandleLegicSamplesDemod(int ci
, int cq
)
1293 int halfci
= (ai
>> 1);
1294 int halfcq
= (aq
>> 1);
1296 switch(Demod
.state
) {
1299 CHECK_FOR_SUBCARRIER()
1301 if(v
> SUBCARRIER_DETECT_THRESHOLD
) { // subcarrier detected
1302 Demod
.state
= DEMOD_PHASE_REF_TRAINING
;
1309 case DEMOD_PHASE_REF_TRAINING
:
1310 if(Demod
.posCount
< 8) {
1312 CHECK_FOR_SUBCARRIER()
1314 if (v
> SUBCARRIER_DETECT_THRESHOLD
) {
1315 // set the reference phase (will code a logic '1') by averaging over 32 1/fs.
1316 // note: synchronization time > 80 1/fs
1322 Demod
.state
= DEMOD_UNSYNCD
;
1325 Demod
.state
= DEMOD_AWAITING_FALLING_EDGE_OF_SOF
;
1329 case DEMOD_AWAITING_FALLING_EDGE_OF_SOF
:
1331 MAKE_SOFT_DECISION()
1333 //Dbprintf("ICE: %d %d %d %d %d", v, Demod.sumI, Demod.sumQ, ci, cq );
1334 // logic '0' detected
1337 Demod
.state
= DEMOD_GOT_FALLING_EDGE_OF_SOF
;
1339 // start of SOF sequence
1342 // maximum length of TR1 = 200 1/fs
1343 if(Demod
.posCount
> 25*2) Demod
.state
= DEMOD_UNSYNCD
;
1348 case DEMOD_GOT_FALLING_EDGE_OF_SOF
:
1351 MAKE_SOFT_DECISION()
1354 // low phase of SOF too short (< 9 etu). Note: spec is >= 10, but FPGA tends to "smear" edges
1355 if(Demod
.posCount
< 10*2) {
1356 Demod
.state
= DEMOD_UNSYNCD
;
1358 LED_C_ON(); // Got SOF
1359 Demod
.state
= DEMOD_AWAITING_START_BIT
;
1364 // low phase of SOF too long (> 12 etu)
1365 if(Demod
.posCount
> 13*2) {
1366 Demod
.state
= DEMOD_UNSYNCD
;
1372 case DEMOD_AWAITING_START_BIT
:
1375 MAKE_SOFT_DECISION()
1378 // max 19us between characters = 16 1/fs, max 3 etu after low phase of SOF = 24 1/fs
1379 if(Demod
.posCount
> 3*2) {
1380 Demod
.state
= DEMOD_UNSYNCD
;
1384 // start bit detected
1386 Demod
.posCount
= 1; // this was the first half
1389 Demod
.state
= DEMOD_RECEIVING_DATA
;
1393 case DEMOD_RECEIVING_DATA
:
1395 MAKE_SOFT_DECISION()
1397 if(Demod
.posCount
== 0) {
1398 // first half of bit
1402 // second half of bit
1404 Demod
.shiftReg
>>= 1;
1406 if(Demod
.thisBit
> 0)
1407 Demod
.shiftReg
|= 0x200;
1411 if(Demod
.bitCount
== 10) {
1413 uint16_t s
= Demod
.shiftReg
;
1415 if((s
& 0x200) && !(s
& 0x001)) {
1416 // stop bit == '1', start bit == '0'
1417 uint8_t b
= (s
>> 1);
1418 Demod
.output
[Demod
.len
] = b
;
1420 Demod
.state
= DEMOD_AWAITING_START_BIT
;
1422 Demod
.state
= DEMOD_UNSYNCD
;
1426 // This is EOF (start, stop and all data bits == '0'
1436 Demod
.state
= DEMOD_UNSYNCD
;
1443 // Clear out the state of the "UART" that receives from the tag.
1444 static void DemodReset() {
1446 Demod
.state
= DEMOD_UNSYNCD
;
1453 memset(Demod
.output
, 0x00, MAX_FRAME_SIZE
);
1456 static void DemodInit(uint8_t *data
) {
1457 Demod
.output
= data
;
1462 * Demodulate the samples we received from the tag, also log to tracebuffer
1463 * quiet: set to 'TRUE' to disable debug output
1465 #define LEGIC_DMA_BUFFER_SIZE 256
1466 static void GetSamplesForLegicDemod(int n
, bool quiet
)
1469 bool gotFrame
= FALSE
;
1470 int lastRxCounter
= LEGIC_DMA_BUFFER_SIZE
;
1471 int ci
, cq
, samples
= 0;
1475 // And put the FPGA in the appropriate mode
1476 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR
| FPGA_HF_READER_RX_XCORR_QUARTER_FREQ
);
1478 // The response (tag -> reader) that we're receiving.
1479 // Set up the demodulator for tag -> reader responses.
1480 DemodInit(BigBuf_malloc(MAX_FRAME_SIZE
));
1482 // The DMA buffer, used to stream samples from the FPGA
1483 int8_t *dmaBuf
= (int8_t*) BigBuf_malloc(LEGIC_DMA_BUFFER_SIZE
);
1484 int8_t *upTo
= dmaBuf
;
1486 // Setup and start DMA.
1487 if ( !FpgaSetupSscDma((uint8_t*) dmaBuf
, LEGIC_DMA_BUFFER_SIZE
) ){
1488 if (MF_DBGLEVEL
> 1) Dbprintf("FpgaSetupSscDma failed. Exiting");
1492 // Signal field is ON with the appropriate LED:
1495 int behindBy
= lastRxCounter
- AT91C_BASE_PDC_SSC
->PDC_RCR
;
1496 if(behindBy
> max
) max
= behindBy
;
1498 while(((lastRxCounter
-AT91C_BASE_PDC_SSC
->PDC_RCR
) & (LEGIC_DMA_BUFFER_SIZE
-1)) > 2) {
1502 if(upTo
>= dmaBuf
+ LEGIC_DMA_BUFFER_SIZE
) {
1504 AT91C_BASE_PDC_SSC
->PDC_RNPR
= (uint32_t) upTo
;
1505 AT91C_BASE_PDC_SSC
->PDC_RNCR
= LEGIC_DMA_BUFFER_SIZE
;
1508 if(lastRxCounter
<= 0)
1509 lastRxCounter
= LEGIC_DMA_BUFFER_SIZE
;
1513 gotFrame
= HandleLegicSamplesDemod(ci
, cq
);
1518 if(samples
> n
|| gotFrame
)
1522 FpgaDisableSscDma();
1524 if (!quiet
&& Demod
.len
== 0) {
1525 Dbprintf("max behindby = %d, samples = %d, gotFrame = %d, Demod.len = %d, Demod.sumI = %d, Demod.sumQ = %d",
1536 if (Demod
.len
> 0) {
1537 uint8_t parity
[MAX_PARITY_SIZE
] = {0x00};
1538 LogTrace(Demod
.output
, Demod
.len
, 0, 0, parity
, FALSE
);
1541 //-----------------------------------------------------------------------------
1542 // Transmit the command (to the tag) that was placed in ToSend[].
1543 //-----------------------------------------------------------------------------
1544 static void TransmitForLegic(void)
1550 while(AT91C_BASE_SSC
->SSC_SR
& (AT91C_SSC_TXRDY
))
1551 AT91C_BASE_SSC
->SSC_THR
= 0xff;
1553 // Signal field is ON with the appropriate Red LED
1556 // Signal we are transmitting with the Green LED
1558 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX
| FPGA_HF_READER_TX_SHALLOW_MOD
);
1560 for(c
= 0; c
< 10;) {
1561 if(AT91C_BASE_SSC
->SSC_SR
& (AT91C_SSC_TXRDY
)) {
1562 AT91C_BASE_SSC
->SSC_THR
= 0xff;
1565 if(AT91C_BASE_SSC
->SSC_SR
& (AT91C_SSC_RXRDY
)) {
1566 volatile uint32_t r
= AT91C_BASE_SSC
->SSC_RHR
;
1574 if(AT91C_BASE_SSC
->SSC_SR
& (AT91C_SSC_TXRDY
)) {
1575 AT91C_BASE_SSC
->SSC_THR
= ToSend
[c
];
1576 legic_prng_forward(1); // forward the lfsr
1578 if(c
>= ToSendMax
) {
1582 if(AT91C_BASE_SSC
->SSC_SR
& (AT91C_SSC_RXRDY
)) {
1583 volatile uint32_t r
= AT91C_BASE_SSC
->SSC_RHR
;
1592 //-----------------------------------------------------------------------------
1593 // Code a layer 2 command (string of octets, including CRC) into ToSend[],
1594 // so that it is ready to transmit to the tag using TransmitForLegic().
1595 //-----------------------------------------------------------------------------
1596 static void CodeLegicBitsAsReader(const uint8_t *cmd
, uint8_t cmdlen
, int bits
)
1604 for(i
= 0; i
< 7; i
++)
1608 for(i
= 0; i
< cmdlen
; i
++) {
1614 for(j
= 0; j
< bits
; j
++) {
1624 // Convert from last character reference to length
1629 Convenience function to encode, transmit and trace Legic comms
1631 static void CodeAndTransmitLegicAsReader(const uint8_t *cmd
, uint8_t cmdlen
, int bits
)
1633 CodeLegicBitsAsReader(cmd
, cmdlen
, bits
);
1636 uint8_t parity
[1] = {0x00};
1637 LogTrace(cmd
, cmdlen
, 0, 0, parity
, TRUE
);
1641 int ice_legic_select_card()
1643 //int cmd_size=0, card_size=0;
1644 uint8_t wakeup
[] = { 0x7F };
1645 uint8_t getid
[] = {0x19};
1647 legic_prng_init(SESSION_IV
);
1649 // first, wake up the tag, 7bits
1650 CodeAndTransmitLegicAsReader(wakeup
, sizeof(wakeup
), 7);
1652 GetSamplesForLegicDemod(1000, TRUE
);
1654 // frame_clean(¤t_frame);
1655 //frame_receive_rwd(¤t_frame, 6, 1);
1657 legic_prng_forward(1); /* we wait anyways */
1659 //while(timer->TC_CV < 387) ; /* ~ 258us */
1660 //frame_send_rwd(0x19, 6);
1661 CodeAndTransmitLegicAsReader(getid
, sizeof(getid
), 8);
1662 GetSamplesForLegicDemod(1000, TRUE
);
1664 //if (Demod.len < 14) return 2;
1665 Dbprintf("CARD TYPE: %02x LEN: %d", Demod
.output
[0], Demod
.len
);
1667 switch(Demod
.output
[0]) {
1669 DbpString("MIM 256 card found");
1674 DbpString("MIM 1024 card found");
1676 // card_size = 1024;
1683 // bytes = card_size;
1685 // if(bytes + offset >= card_size)
1686 // bytes = card_size - offset;
1688 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
1693 // Set up LEGIC communication
1694 void ice_legic_setup() {
1697 FpgaDownloadAndGo(FPGA_BITSTREAM_HF
);
1698 BigBuf_free(); BigBuf_Clear_ext(false);
1704 // Set up the synchronous serial port
1707 // connect Demodulated Signal to ADC:
1708 SetAdcMuxFor(GPIO_MUXSEL_HIPKD
);
1710 // Signal field is on with the appropriate LED
1712 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX
| FPGA_HF_READER_TX_SHALLOW_MOD
);
1715 //StartCountSspClk();
1718 crc_init(&legic_crc
, 4, 0x19 >> 1, 0x5, 0);