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1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
10
11 #include "proxmark3.h"
12 #include "apps.h"
13 #include "util.h"
14 #include "hitag2.h"
15 #include "crc16.h"
16 #include "string.h"
17 #include "lfdemod.h"
18 #include "lfsampling.h"
19 #include "protocols.h"
20 #include "usb_cdc.h" // for usb_poll_validate_length
21
22 #ifndef SHORT_COIL
23 # define SHORT_COIL() LOW(GPIO_SSC_DOUT)
24 #endif
25 #ifndef OPEN_COIL
26 # define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
27 #endif
28
29 /**
30 * Function to do a modulation and then get samples.
31 * @param delay_off
32 * @param periods 0xFFFF0000 is period_0, 0x0000FFFF is period_1
33 * @param useHighFreg
34 * @param command
35 */
36 void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t periods, uint32_t useHighFreq, uint8_t *command)
37 {
38 /* Make sure the tag is reset */
39 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
40 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
41 SpinDelay(200);
42
43 uint16_t period_0 = periods >> 16;
44 uint16_t period_1 = periods & 0xFFFF;
45
46 // 95 == 125 KHz 88 == 124.8 KHz
47 int divisor_used = (useHighFreq) ? 88 : 95;
48 sample_config sc = { 0,0,1, divisor_used, 0};
49 setSamplingConfig(&sc);
50
51 //clear read buffer
52 BigBuf_Clear_keep_EM();
53
54 LFSetupFPGAForADC(sc.divisor, 1);
55
56 // And a little more time for the tag to fully power up
57 SpinDelay(50);
58
59 // now modulate the reader field
60 while(*command != '\0' && *command != ' ') {
61 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
62 LED_D_OFF();
63 WaitUS(delay_off);
64 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
65
66 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
67 LED_D_ON();
68 if(*(command++) == '0')
69 WaitUS(period_0);
70 else
71 WaitUS(period_1);
72 }
73 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
74 LED_D_OFF();
75 WaitUS(delay_off);
76 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
77 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
78
79 // now do the read
80 DoAcquisition_config(false);
81 }
82
83 /* blank r/w tag data stream
84 ...0000000000000000 01111111
85 1010101010101010101010101010101010101010101010101010101010101010
86 0011010010100001
87 01111111
88 101010101010101[0]000...
89
90 [5555fe852c5555555555555555fe0000]
91 */
92 void ReadTItag(void)
93 {
94 StartTicks();
95 // some hardcoded initial params
96 // when we read a TI tag we sample the zerocross line at 2Mhz
97 // TI tags modulate a 1 as 16 cycles of 123.2Khz
98 // TI tags modulate a 0 as 16 cycles of 134.2Khz
99 #define FSAMPLE 2000000
100 #define FREQLO 123200
101 #define FREQHI 134200
102
103 signed char *dest = (signed char *)BigBuf_get_addr();
104 uint16_t n = BigBuf_max_traceLen();
105 // 128 bit shift register [shift3:shift2:shift1:shift0]
106 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
107
108 int i, cycles=0, samples=0;
109 // how many sample points fit in 16 cycles of each frequency
110 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
111 // when to tell if we're close enough to one freq or another
112 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
113
114 // TI tags charge at 134.2Khz
115 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
116 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
117
118 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
119 // connects to SSP_DIN and the SSP_DOUT logic level controls
120 // whether we're modulating the antenna (high)
121 // or listening to the antenna (low)
122 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
123
124 // get TI tag data into the buffer
125 AcquireTiType();
126
127 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
128
129 for (i=0; i<n-1; i++) {
130 // count cycles by looking for lo to hi zero crossings
131 if ( (dest[i]<0) && (dest[i+1]>0) ) {
132 cycles++;
133 // after 16 cycles, measure the frequency
134 if (cycles>15) {
135 cycles=0;
136 samples=i-samples; // number of samples in these 16 cycles
137
138 // TI bits are coming to us lsb first so shift them
139 // right through our 128 bit right shift register
140 shift0 = (shift0>>1) | (shift1 << 31);
141 shift1 = (shift1>>1) | (shift2 << 31);
142 shift2 = (shift2>>1) | (shift3 << 31);
143 shift3 >>= 1;
144
145 // check if the cycles fall close to the number
146 // expected for either the low or high frequency
147 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
148 // low frequency represents a 1
149 shift3 |= (1<<31);
150 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
151 // high frequency represents a 0
152 } else {
153 // probably detected a gay waveform or noise
154 // use this as gaydar or discard shift register and start again
155 shift3 = shift2 = shift1 = shift0 = 0;
156 }
157 samples = i;
158
159 // for each bit we receive, test if we've detected a valid tag
160
161 // if we see 17 zeroes followed by 6 ones, we might have a tag
162 // remember the bits are backwards
163 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
164 // if start and end bytes match, we have a tag so break out of the loop
165 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
166 cycles = 0xF0B; //use this as a flag (ugly but whatever)
167 break;
168 }
169 }
170 }
171 }
172 }
173
174 // if flag is set we have a tag
175 if (cycles!=0xF0B) {
176 DbpString("Info: No valid tag detected.");
177 } else {
178 // put 64 bit data into shift1 and shift0
179 shift0 = (shift0>>24) | (shift1 << 8);
180 shift1 = (shift1>>24) | (shift2 << 8);
181
182 // align 16 bit crc into lower half of shift2
183 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
184
185 // if r/w tag, check ident match
186 if (shift3 & (1<<15) ) {
187 DbpString("Info: TI tag is rewriteable");
188 // only 15 bits compare, last bit of ident is not valid
189 if (((shift3 >> 16) ^ shift0) & 0x7fff ) {
190 DbpString("Error: Ident mismatch!");
191 } else {
192 DbpString("Info: TI tag ident is valid");
193 }
194 } else {
195 DbpString("Info: TI tag is readonly");
196 }
197
198 // WARNING the order of the bytes in which we calc crc below needs checking
199 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
200 // bytes in reverse or something
201 // calculate CRC
202 uint32_t crc=0;
203
204 crc = update_crc16(crc, (shift0)&0xff);
205 crc = update_crc16(crc, (shift0>>8)&0xff);
206 crc = update_crc16(crc, (shift0>>16)&0xff);
207 crc = update_crc16(crc, (shift0>>24)&0xff);
208 crc = update_crc16(crc, (shift1)&0xff);
209 crc = update_crc16(crc, (shift1>>8)&0xff);
210 crc = update_crc16(crc, (shift1>>16)&0xff);
211 crc = update_crc16(crc, (shift1>>24)&0xff);
212
213 Dbprintf("Info: Tag data: %x%08x, crc=%x", (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
214 if (crc != (shift2&0xffff)) {
215 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
216 } else {
217 DbpString("Info: CRC is good");
218 }
219 }
220 StopTicks();
221 }
222
223 void WriteTIbyte(uint8_t b)
224 {
225 int i = 0;
226
227 // modulate 8 bits out to the antenna
228 for (i=0; i<8; i++)
229 {
230 if ( b & ( 1 << i ) ) {
231 // stop modulating antenna 1ms
232 LOW(GPIO_SSC_DOUT);
233 WaitUS(1000);
234 // modulate antenna 1ms
235 HIGH(GPIO_SSC_DOUT);
236 WaitUS(1000);
237 } else {
238 // stop modulating antenna 1ms
239 LOW(GPIO_SSC_DOUT);
240 WaitUS(300);
241 // modulate antenna 1m
242 HIGH(GPIO_SSC_DOUT);
243 WaitUS(1700);
244 }
245 }
246 }
247
248 void AcquireTiType(void)
249 {
250 int i, j, n;
251 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
252 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
253 #define TIBUFLEN 1250
254
255 // clear buffer
256 uint32_t *buf = (uint32_t *)BigBuf_get_addr();
257
258 //clear buffer now so it does not interfere with timing later
259 BigBuf_Clear_ext(false);
260
261 // Set up the synchronous serial port
262 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
263 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
264
265 // steal this pin from the SSP and use it to control the modulation
266 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
267 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
268
269 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
270 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
271
272 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
273 // 48/2 = 24 MHz clock must be divided by 12
274 AT91C_BASE_SSC->SSC_CMR = 12;
275
276 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
277 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
278 AT91C_BASE_SSC->SSC_TCMR = 0;
279 AT91C_BASE_SSC->SSC_TFMR = 0;
280 // iceman, FpgaSetupSsc() ?? the code above? can it be replaced?
281 LED_D_ON();
282
283 // modulate antenna
284 HIGH(GPIO_SSC_DOUT);
285
286 // Charge TI tag for 50ms.
287 WaitMS(50);
288
289 // stop modulating antenna and listen
290 LOW(GPIO_SSC_DOUT);
291
292 LED_D_OFF();
293
294 i = 0;
295 for(;;) {
296 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
297 buf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
298 i++; if(i >= TIBUFLEN) break;
299 }
300 WDT_HIT();
301 }
302
303 // return stolen pin to SSP
304 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
305 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
306
307 char *dest = (char *)BigBuf_get_addr();
308 n = TIBUFLEN * 32;
309
310 // unpack buffer
311 for (i = TIBUFLEN-1; i >= 0; i--) {
312 for (j = 0; j < 32; j++) {
313 if(buf[i] & (1 << j)) {
314 dest[--n] = 1;
315 } else {
316 dest[--n] = -1;
317 }
318 }
319 }
320 }
321
322 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
323 // if crc provided, it will be written with the data verbatim (even if bogus)
324 // if not provided a valid crc will be computed from the data and written.
325 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
326 {
327 StartTicks();
328 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
329 if(crc == 0) {
330 crc = update_crc16(crc, (idlo)&0xff);
331 crc = update_crc16(crc, (idlo>>8)&0xff);
332 crc = update_crc16(crc, (idlo>>16)&0xff);
333 crc = update_crc16(crc, (idlo>>24)&0xff);
334 crc = update_crc16(crc, (idhi)&0xff);
335 crc = update_crc16(crc, (idhi>>8)&0xff);
336 crc = update_crc16(crc, (idhi>>16)&0xff);
337 crc = update_crc16(crc, (idhi>>24)&0xff);
338 }
339 Dbprintf("Writing to tag: %x%08x, crc=%x", (unsigned int) idhi, (unsigned int) idlo, crc);
340
341 // TI tags charge at 134.2Khz
342 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
343 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
344 // connects to SSP_DIN and the SSP_DOUT logic level controls
345 // whether we're modulating the antenna (high)
346 // or listening to the antenna (low)
347 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
348 LED_A_ON();
349
350 // steal this pin from the SSP and use it to control the modulation
351 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
352 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
353
354 // writing algorithm:
355 // a high bit consists of a field off for 1ms and field on for 1ms
356 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
357 // initiate a charge time of 50ms (field on) then immediately start writing bits
358 // start by writing 0xBB (keyword) and 0xEB (password)
359 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
360 // finally end with 0x0300 (write frame)
361 // all data is sent lsb first
362 // finish with 15ms programming time
363
364 // modulate antenna
365 HIGH(GPIO_SSC_DOUT);
366 WaitMS(50); // charge time
367
368 WriteTIbyte(0xbb); // keyword
369 WriteTIbyte(0xeb); // password
370 WriteTIbyte( (idlo )&0xff );
371 WriteTIbyte( (idlo>>8 )&0xff );
372 WriteTIbyte( (idlo>>16)&0xff );
373 WriteTIbyte( (idlo>>24)&0xff );
374 WriteTIbyte( (idhi )&0xff );
375 WriteTIbyte( (idhi>>8 )&0xff );
376 WriteTIbyte( (idhi>>16)&0xff );
377 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
378 WriteTIbyte( (crc )&0xff ); // crc lo
379 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
380 WriteTIbyte(0x00); // write frame lo
381 WriteTIbyte(0x03); // write frame hi
382 HIGH(GPIO_SSC_DOUT);
383 WaitMS(50); // programming time
384
385 LED_A_OFF();
386
387 // get TI tag data into the buffer
388 AcquireTiType();
389
390 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
391 DbpString("Now use `lf ti read` to check");
392 StopTicks();
393 }
394
395 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
396 {
397 int i = 0;
398 uint8_t *buf = BigBuf_get_addr();
399
400 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD);
401
402 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
403 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
404 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
405
406 StartTicks();
407
408 for(;;) {
409 WDT_HIT();
410
411 if (ledcontrol) LED_D_ON();
412
413 // wait until SSC_CLK goes HIGH
414 // used as a simple detection of a reader field?
415 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
416 WDT_HIT();
417 if ( usb_poll_validate_length() || BUTTON_PRESS() )
418 goto OUT;
419 }
420
421 if(buf[i])
422 OPEN_COIL();
423 else
424 SHORT_COIL();
425
426 if (ledcontrol) LED_D_OFF();
427
428 //wait until SSC_CLK goes LOW
429 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
430 WDT_HIT();
431 if ( usb_poll_validate_length() || BUTTON_PRESS() )
432 goto OUT;
433 }
434
435 i++;
436 if(i == period) {
437 i = 0;
438 if (gap) {
439 WDT_HIT();
440 SHORT_COIL();
441 WaitUS(gap);
442 }
443 }
444 }
445 OUT:
446 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
447 StopTicks();
448 LED_D_OFF();
449 return;
450 }
451
452 #define DEBUG_FRAME_CONTENTS 1
453 void SimulateTagLowFrequencyBidir(int divisor, int t0)
454 {
455 }
456
457 // compose fc/8 fc/10 waveform (FSK2)
458 static void fc(int c, int *n)
459 {
460 uint8_t *dest = BigBuf_get_addr();
461 int idx;
462
463 // for when we want an fc8 pattern every 4 logical bits
464 if(c==0) {
465 dest[((*n)++)]=1;
466 dest[((*n)++)]=1;
467 dest[((*n)++)]=1;
468 dest[((*n)++)]=1;
469 dest[((*n)++)]=0;
470 dest[((*n)++)]=0;
471 dest[((*n)++)]=0;
472 dest[((*n)++)]=0;
473 }
474
475 // an fc/8 encoded bit is a bit pattern of 11110000 x6 = 48 samples
476 if(c==8) {
477 for (idx=0; idx<6; idx++) {
478 dest[((*n)++)]=1;
479 dest[((*n)++)]=1;
480 dest[((*n)++)]=1;
481 dest[((*n)++)]=1;
482 dest[((*n)++)]=0;
483 dest[((*n)++)]=0;
484 dest[((*n)++)]=0;
485 dest[((*n)++)]=0;
486 }
487 }
488
489 // an fc/10 encoded bit is a bit pattern of 1111100000 x5 = 50 samples
490 if(c==10) {
491 for (idx=0; idx<5; idx++) {
492 dest[((*n)++)]=1;
493 dest[((*n)++)]=1;
494 dest[((*n)++)]=1;
495 dest[((*n)++)]=1;
496 dest[((*n)++)]=1;
497 dest[((*n)++)]=0;
498 dest[((*n)++)]=0;
499 dest[((*n)++)]=0;
500 dest[((*n)++)]=0;
501 dest[((*n)++)]=0;
502 }
503 }
504 }
505 // compose fc/X fc/Y waveform (FSKx)
506 static void fcAll(uint8_t fc, int *n, uint8_t clock, uint16_t *modCnt)
507 {
508 uint8_t *dest = BigBuf_get_addr();
509 uint8_t halfFC = fc/2;
510 uint8_t wavesPerClock = clock/fc;
511 uint8_t mod = clock % fc; //modifier
512 uint8_t modAdj = fc/mod; //how often to apply modifier
513 bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=TRUE;
514 // loop through clock - step field clock
515 for (uint8_t idx=0; idx < wavesPerClock; idx++){
516 // put 1/2 FC length 1's and 1/2 0's per field clock wave (to create the wave)
517 memset(dest+(*n), 0, fc-halfFC); //in case of odd number use extra here
518 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
519 *n += fc;
520 }
521 if (mod>0) (*modCnt)++;
522 if ((mod>0) && modAdjOk){ //fsk2
523 if ((*modCnt % modAdj) == 0){ //if 4th 8 length wave in a rf/50 add extra 8 length wave
524 memset(dest+(*n), 0, fc-halfFC);
525 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
526 *n += fc;
527 }
528 }
529 if (mod>0 && !modAdjOk){ //fsk1
530 memset(dest+(*n), 0, mod-(mod/2));
531 memset(dest+(*n)+(mod-(mod/2)), 1, mod/2);
532 *n += mod;
533 }
534 }
535
536 // prepare a waveform pattern in the buffer based on the ID given then
537 // simulate a HID tag until the button is pressed
538 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
539 {
540 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
541 set_tracing(FALSE);
542
543 int n = 0, i = 0;
544 /*
545 HID tag bitstream format
546 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
547 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
548 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
549 A fc8 is inserted before every 4 bits
550 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
551 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
552 */
553
554 if (hi > 0xFFF) {
555 DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags");
556 return;
557 }
558 fc(0,&n);
559 // special start of frame marker containing invalid bit sequences
560 fc(8, &n); fc(8, &n); // invalid
561 fc(8, &n); fc(10, &n); // logical 0
562 fc(10, &n); fc(10, &n); // invalid
563 fc(8, &n); fc(10, &n); // logical 0
564
565 WDT_HIT();
566 // manchester encode bits 43 to 32
567 for (i=11; i>=0; i--) {
568 if ((i%4)==3) fc(0,&n);
569 if ((hi>>i)&1) {
570 fc(10, &n); fc(8, &n); // low-high transition
571 } else {
572 fc(8, &n); fc(10, &n); // high-low transition
573 }
574 }
575
576 WDT_HIT();
577 // manchester encode bits 31 to 0
578 for (i=31; i>=0; i--) {
579 if ((i%4)==3) fc(0,&n);
580 if ((lo>>i)&1) {
581 fc(10, &n); fc(8, &n); // low-high transition
582 } else {
583 fc(8, &n); fc(10, &n); // high-low transition
584 }
585 }
586 WDT_HIT();
587
588 if (ledcontrol) LED_A_ON();
589 SimulateTagLowFrequency(n, 0, ledcontrol);
590 if (ledcontrol) LED_A_OFF();
591 }
592
593 // prepare a waveform pattern in the buffer based on the ID given then
594 // simulate a FSK tag until the button is pressed
595 // arg1 contains fcHigh and fcLow, arg2 contains invert and clock
596 void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
597 {
598 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
599
600 // free eventually allocated BigBuf memory
601 BigBuf_free(); BigBuf_Clear_ext(false);
602 clear_trace();
603 set_tracing(FALSE);
604
605 int ledcontrol = 1, n = 0, i = 0;
606 uint8_t fcHigh = arg1 >> 8;
607 uint8_t fcLow = arg1 & 0xFF;
608 uint16_t modCnt = 0;
609 uint8_t clk = arg2 & 0xFF;
610 uint8_t invert = (arg2 >> 8) & 1;
611
612 for (i=0; i<size; i++){
613
614 if (BitStream[i] == invert)
615 fcAll(fcLow, &n, clk, &modCnt);
616 else
617 fcAll(fcHigh, &n, clk, &modCnt);
618 }
619 WDT_HIT();
620
621 Dbprintf("Simulating with fcHigh: %d, fcLow: %d, clk: %d, invert: %d, n: %d", fcHigh, fcLow, clk, invert, n);
622
623 if (ledcontrol) LED_A_ON();
624 SimulateTagLowFrequency(n, 0, ledcontrol);
625 if (ledcontrol) LED_A_OFF();
626 }
627
628 // compose ask waveform for one bit(ASK)
629 static void askSimBit(uint8_t c, int *n, uint8_t clock, uint8_t manchester)
630 {
631 uint8_t *dest = BigBuf_get_addr();
632 uint8_t halfClk = clock/2;
633 // c = current bit 1 or 0
634 if (manchester==1){
635 memset(dest+(*n), c, halfClk);
636 memset(dest+(*n) + halfClk, c^1, halfClk);
637 } else {
638 memset(dest+(*n), c, clock);
639 }
640 *n += clock;
641 }
642
643 static void biphaseSimBit(uint8_t c, int *n, uint8_t clock, uint8_t *phase)
644 {
645 uint8_t *dest = BigBuf_get_addr();
646 uint8_t halfClk = clock/2;
647 if (c){
648 memset(dest+(*n), c ^ 1 ^ *phase, halfClk);
649 memset(dest+(*n) + halfClk, c ^ *phase, halfClk);
650 } else {
651 memset(dest+(*n), c ^ *phase, clock);
652 *phase ^= 1;
653 }
654 *n += clock;
655 }
656
657 static void stAskSimBit(int *n, uint8_t clock) {
658 uint8_t *dest = BigBuf_get_addr();
659 uint8_t halfClk = clock/2;
660 //ST = .5 high .5 low 1.5 high .5 low 1 high
661 memset(dest+(*n), 1, halfClk);
662 memset(dest+(*n) + halfClk, 0, halfClk);
663 memset(dest+(*n) + clock, 1, clock + halfClk);
664 memset(dest+(*n) + clock*2 + halfClk, 0, halfClk);
665 memset(dest+(*n) + clock*3, 1, clock);
666 *n += clock*4;
667 }
668
669 // args clock, ask/man or askraw, invert, transmission separator
670 void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
671 {
672 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
673 set_tracing(FALSE);
674
675 int ledcontrol = 1, n = 0, i = 0;
676 uint8_t clk = (arg1 >> 8) & 0xFF;
677 uint8_t encoding = arg1 & 0xFF;
678 uint8_t separator = arg2 & 1;
679 uint8_t invert = (arg2 >> 8) & 1;
680
681 if (encoding == 2){ //biphase
682 uint8_t phase = 0;
683 for (i=0; i<size; i++){
684 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
685 }
686 if (phase == 1) { //run a second set inverted to keep phase in check
687 for (i=0; i<size; i++){
688 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
689 }
690 }
691 } else { // ask/manchester || ask/raw
692 for (i=0; i<size; i++){
693 askSimBit(BitStream[i]^invert, &n, clk, encoding);
694 }
695 if (encoding==0 && BitStream[0]==BitStream[size-1]){ //run a second set inverted (for biphase phase)
696 for (i=0; i<size; i++){
697 askSimBit(BitStream[i]^invert^1, &n, clk, encoding);
698 }
699 }
700 }
701 if (separator==1 && encoding == 1)
702 stAskSimBit(&n, clk);
703 else if (separator==1)
704 Dbprintf("sorry but separator option not yet available");
705
706 WDT_HIT();
707
708 Dbprintf("Simulating with clk: %d, invert: %d, encoding: %d, separator: %d, n: %d",clk, invert, encoding, separator, n);
709
710 if (ledcontrol) LED_A_ON();
711 SimulateTagLowFrequency(n, 0, ledcontrol);
712 if (ledcontrol) LED_A_OFF();
713 }
714
715 //carrier can be 2,4 or 8
716 static void pskSimBit(uint8_t waveLen, int *n, uint8_t clk, uint8_t *curPhase, bool phaseChg)
717 {
718 uint8_t *dest = BigBuf_get_addr();
719 uint8_t halfWave = waveLen/2;
720 //uint8_t idx;
721 int i = 0;
722 if (phaseChg){
723 // write phase change
724 memset(dest+(*n), *curPhase^1, halfWave);
725 memset(dest+(*n) + halfWave, *curPhase, halfWave);
726 *n += waveLen;
727 *curPhase ^= 1;
728 i += waveLen;
729 }
730 //write each normal clock wave for the clock duration
731 for (; i < clk; i+=waveLen){
732 memset(dest+(*n), *curPhase, halfWave);
733 memset(dest+(*n) + halfWave, *curPhase^1, halfWave);
734 *n += waveLen;
735 }
736 }
737
738 // args clock, carrier, invert,
739 void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
740 {
741 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
742 set_tracing(FALSE);
743
744 int ledcontrol = 1, n = 0, i = 0;
745 uint8_t clk = arg1 >> 8;
746 uint8_t carrier = arg1 & 0xFF;
747 uint8_t invert = arg2 & 0xFF;
748 uint8_t curPhase = 0;
749 for (i=0; i<size; i++){
750 if (BitStream[i] == curPhase){
751 pskSimBit(carrier, &n, clk, &curPhase, FALSE);
752 } else {
753 pskSimBit(carrier, &n, clk, &curPhase, TRUE);
754 }
755 }
756
757 WDT_HIT();
758
759 Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n);
760
761 if (ledcontrol) LED_A_ON();
762 SimulateTagLowFrequency(n, 0, ledcontrol);
763 if (ledcontrol) LED_A_OFF();
764 }
765
766 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
767 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
768 {
769 uint8_t *dest = BigBuf_get_addr();
770 size_t size = 0;
771 uint32_t hi2=0, hi=0, lo=0;
772 int idx=0;
773 // Configure to go in 125Khz listen mode
774 LFSetupFPGAForADC(95, true);
775
776 //clear read buffer
777 BigBuf_Clear_keep_EM();
778
779 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
780
781 WDT_HIT();
782 if (ledcontrol) LED_A_ON();
783
784 DoAcquisition_default(-1,true);
785 // FSK demodulator
786 size = 50*128*2; //big enough to catch 2 sequences of largest format
787 idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
788
789 if (idx>0 && lo>0 && (size==96 || size==192)){
790 // go over previously decoded manchester data and decode into usable tag ID
791 if (hi2 != 0){ //extra large HID tags 88/192 bits
792 Dbprintf("TAG ID: %x%08x%08x (%d)",
793 (unsigned int) hi2,
794 (unsigned int) hi,
795 (unsigned int) lo,
796 (unsigned int) (lo>>1) & 0xFFFF
797 );
798 } else { //standard HID tags 44/96 bits
799 uint8_t bitlen = 0;
800 uint32_t fc = 0;
801 uint32_t cardnum = 0;
802
803 if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
804 uint32_t lo2=0;
805 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
806 uint8_t idx3 = 1;
807 while(lo2 > 1){ //find last bit set to 1 (format len bit)
808 lo2=lo2 >> 1;
809 idx3++;
810 }
811 bitlen = idx3+19;
812 fc =0;
813 cardnum=0;
814 if(bitlen == 26){
815 cardnum = (lo>>1)&0xFFFF;
816 fc = (lo>>17)&0xFF;
817 }
818 if(bitlen == 37){
819 cardnum = (lo>>1)&0x7FFFF;
820 fc = ((hi&0xF)<<12)|(lo>>20);
821 }
822 if(bitlen == 34){
823 cardnum = (lo>>1)&0xFFFF;
824 fc= ((hi&1)<<15)|(lo>>17);
825 }
826 if(bitlen == 35){
827 cardnum = (lo>>1)&0xFFFFF;
828 fc = ((hi&1)<<11)|(lo>>21);
829 }
830 }
831 else { //if bit 38 is not set then 37 bit format is used
832 bitlen= 37;
833 fc =0;
834 cardnum=0;
835 if(bitlen==37){
836 cardnum = (lo>>1)&0x7FFFF;
837 fc = ((hi&0xF)<<12)|(lo>>20);
838 }
839 }
840 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
841 (unsigned int) hi,
842 (unsigned int) lo,
843 (unsigned int) (lo>>1) & 0xFFFF,
844 (unsigned int) bitlen,
845 (unsigned int) fc,
846 (unsigned int) cardnum);
847 }
848 if (findone){
849 if (ledcontrol) LED_A_OFF();
850 *high = hi;
851 *low = lo;
852 return;
853 }
854 // reset
855 }
856 hi2 = hi = lo = idx = 0;
857 WDT_HIT();
858 }
859 DbpString("Stopped");
860 if (ledcontrol) LED_A_OFF();
861 }
862
863 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
864 void CmdAWIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
865 {
866 uint8_t *dest = BigBuf_get_addr();
867 size_t size;
868 int idx=0;
869 //clear read buffer
870 BigBuf_Clear_keep_EM();
871 // Configure to go in 125Khz listen mode
872 LFSetupFPGAForADC(95, true);
873
874 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
875
876 WDT_HIT();
877 if (ledcontrol) LED_A_ON();
878
879 DoAcquisition_default(-1,true);
880 // FSK demodulator
881 size = 50*128*2; //big enough to catch 2 sequences of largest format
882 idx = AWIDdemodFSK(dest, &size);
883
884 if (idx<=0 || size!=96) continue;
885 // Index map
886 // 0 10 20 30 40 50 60
887 // | | | | | | |
888 // 01234567 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 - to 96
889 // -----------------------------------------------------------------------------
890 // 00000001 000 1 110 1 101 1 011 1 101 1 010 0 000 1 000 1 010 0 001 0 110 1 100 0 000 1 000 1
891 // premable bbb o bbb o bbw o fff o fff o ffc o ccc o ccc o ccc o ccc o ccc o wxx o xxx o xxx o - to 96
892 // |---26 bit---| |-----117----||-------------142-------------|
893 // b = format bit len, o = odd parity of last 3 bits
894 // f = facility code, c = card number
895 // w = wiegand parity
896 // (26 bit format shown)
897
898 //get raw ID before removing parities
899 uint32_t rawLo = bytebits_to_byte(dest+idx+64,32);
900 uint32_t rawHi = bytebits_to_byte(dest+idx+32,32);
901 uint32_t rawHi2 = bytebits_to_byte(dest+idx,32);
902
903 size = removeParity(dest, idx+8, 4, 1, 88);
904 if (size != 66) continue;
905
906 // Index map
907 // 0 10 20 30 40 50 60
908 // | | | | | | |
909 // 01234567 8 90123456 7890123456789012 3 456789012345678901234567890123456
910 // -----------------------------------------------------------------------------
911 // 00011010 1 01110101 0000000010001110 1 000000000000000000000000000000000
912 // bbbbbbbb w ffffffff cccccccccccccccc w xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
913 // |26 bit| |-117--| |-----142------|
914 //
915 // 00110010 0 0000011111010000000000000001000100101000100001111 0 00000000
916 // bbbbbbbb w ffffffffffffffffccccccccccccccccccccccccccccccccc w xxxxxxxx
917 // |50 bit| |----4000------||-----------2248975-------------|
918 //
919 // b = format bit len, o = odd parity of last 3 bits
920 // f = facility code, c = card number
921 // w = wiegand parity
922
923 uint32_t fc = 0;
924 uint32_t cardnum = 0;
925 uint32_t code1 = 0;
926 uint32_t code2 = 0;
927 uint8_t fmtLen = bytebits_to_byte(dest,8);
928 switch(fmtLen) {
929 case 26:
930 fc = bytebits_to_byte(dest + 9, 8);
931 cardnum = bytebits_to_byte(dest + 17, 16);
932 code1 = bytebits_to_byte(dest + 8,fmtLen);
933 Dbprintf("AWID Found - BitLength: %d, FC: %d, Card: %u - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, fc, cardnum, code1, rawHi2, rawHi, rawLo);
934 break;
935 case 50:
936 fc = bytebits_to_byte(dest + 9, 16);
937 cardnum = bytebits_to_byte(dest + 25, 32);
938 code1 = bytebits_to_byte(dest + 8, (fmtLen-32) );
939 code2 = bytebits_to_byte(dest + 8 + (fmtLen-32), 32);
940 Dbprintf("AWID Found - BitLength: %d, FC: %d, Card: %u - Wiegand: %x%08x, Raw: %08x%08x%08x", fmtLen, fc, cardnum, code1, code2, rawHi2, rawHi, rawLo);
941 break;
942 default:
943 if (fmtLen > 32 ) {
944 cardnum = bytebits_to_byte(dest+8+(fmtLen-17), 16);
945 code1 = bytebits_to_byte(dest+8,fmtLen-32);
946 code2 = bytebits_to_byte(dest+8+(fmtLen-32),32);
947 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%u) - Wiegand: %x%08x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, code2, rawHi2, rawHi, rawLo);
948 } else {
949 cardnum = bytebits_to_byte(dest+8+(fmtLen-17), 16);
950 code1 = bytebits_to_byte(dest+8,fmtLen);
951 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%u) - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, rawHi2, rawHi, rawLo);
952 }
953 break;
954 }
955 if (findone){
956 if (ledcontrol) LED_A_OFF();
957 return;
958 }
959 idx = 0;
960 WDT_HIT();
961 }
962 DbpString("Stopped");
963 if (ledcontrol) LED_A_OFF();
964 }
965
966 void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
967 {
968 uint8_t *dest = BigBuf_get_addr();
969
970 size_t size=0, idx=0;
971 int clk=0, invert=0, errCnt=0, maxErr=20;
972 uint32_t hi=0;
973 uint64_t lo=0;
974 //clear read buffer
975 BigBuf_Clear_keep_EM();
976 // Configure to go in 125Khz listen mode
977 LFSetupFPGAForADC(95, true);
978
979 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
980
981 WDT_HIT();
982 if (ledcontrol) LED_A_ON();
983
984 DoAcquisition_default(-1,true);
985 size = BigBuf_max_traceLen();
986 //askdemod and manchester decode
987 if (size > 16385) size = 16385; //big enough to catch 2 sequences of largest format
988 errCnt = askdemod(dest, &size, &clk, &invert, maxErr, 0, 1);
989 WDT_HIT();
990
991 if (errCnt<0) continue;
992
993 errCnt = Em410xDecode(dest, &size, &idx, &hi, &lo);
994 if (errCnt){
995 if (size>64){
996 Dbprintf("EM XL TAG ID: %06x%08x%08x - (%05d_%03d_%08d)",
997 hi,
998 (uint32_t)(lo>>32),
999 (uint32_t)lo,
1000 (uint32_t)(lo&0xFFFF),
1001 (uint32_t)((lo>>16LL) & 0xFF),
1002 (uint32_t)(lo & 0xFFFFFF));
1003 } else {
1004 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
1005 (uint32_t)(lo>>32),
1006 (uint32_t)lo,
1007 (uint32_t)(lo&0xFFFF),
1008 (uint32_t)((lo>>16LL) & 0xFF),
1009 (uint32_t)(lo & 0xFFFFFF));
1010 }
1011
1012 if (findone){
1013 if (ledcontrol) LED_A_OFF();
1014 *high=lo>>32;
1015 *low=lo & 0xFFFFFFFF;
1016 return;
1017 }
1018 }
1019 WDT_HIT();
1020 hi = lo = size = idx = 0;
1021 clk = invert = errCnt = 0;
1022 }
1023 DbpString("Stopped");
1024 if (ledcontrol) LED_A_OFF();
1025 }
1026
1027 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
1028 {
1029 uint8_t *dest = BigBuf_get_addr();
1030 int idx=0;
1031 uint32_t code=0, code2=0;
1032 uint8_t version=0;
1033 uint8_t facilitycode=0;
1034 uint16_t number=0;
1035 uint8_t crc = 0;
1036 uint16_t calccrc = 0;
1037
1038 //clear read buffer
1039 BigBuf_Clear_keep_EM();
1040
1041 // Configure to go in 125Khz listen mode
1042 LFSetupFPGAForADC(95, true);
1043
1044 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
1045 WDT_HIT();
1046 if (ledcontrol) LED_A_ON();
1047 DoAcquisition_default(-1,true);
1048 //fskdemod and get start index
1049 WDT_HIT();
1050 idx = IOdemodFSK(dest, BigBuf_max_traceLen());
1051 if (idx<0) continue;
1052 //valid tag found
1053
1054 //Index map
1055 //0 10 20 30 40 50 60
1056 //| | | | | | |
1057 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
1058 //-----------------------------------------------------------------------------
1059 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 checksum 11
1060 //
1061 //Checksum:
1062 //00000000 0 11110000 1 11100000 1 00000001 1 00000011 1 10110110 1 01110101 11
1063 //preamble F0 E0 01 03 B6 75
1064 // How to calc checksum,
1065 // http://www.proxmark.org/forum/viewtopic.php?id=364&p=6
1066 // F0 + E0 + 01 + 03 + B6 = 28A
1067 // 28A & FF = 8A
1068 // FF - 8A = 75
1069 // Checksum: 0x75
1070 //XSF(version)facility:codeone+codetwo
1071 //Handle the data
1072 if(findone){ //only print binary if we are doing one
1073 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
1074 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
1075 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
1076 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
1077 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
1078 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
1079 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
1080 }
1081 code = bytebits_to_byte(dest+idx,32);
1082 code2 = bytebits_to_byte(dest+idx+32,32);
1083 version = bytebits_to_byte(dest+idx+27,8); //14,4
1084 facilitycode = bytebits_to_byte(dest+idx+18,8);
1085 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
1086
1087 crc = bytebits_to_byte(dest+idx+54,8);
1088 for (uint8_t i=1; i<6; ++i)
1089 calccrc += bytebits_to_byte(dest+idx+9*i,8);
1090 calccrc &= 0xff;
1091 calccrc = 0xff - calccrc;
1092
1093 char *crcStr = (crc == calccrc) ? "ok":"!crc";
1094
1095 Dbprintf("IO Prox XSF(%02d)%02x:%05d (%08x%08x) [%02x %s]",version,facilitycode,number,code,code2, crc, crcStr);
1096 // if we're only looking for one tag
1097 if (findone){
1098 if (ledcontrol) LED_A_OFF();
1099 *high=code;
1100 *low=code2;
1101 return;
1102 }
1103 code=code2=0;
1104 version=facilitycode=0;
1105 number=0;
1106 idx=0;
1107
1108 WDT_HIT();
1109 }
1110 DbpString("Stopped");
1111 if (ledcontrol) LED_A_OFF();
1112 }
1113
1114 /*------------------------------
1115 * T5555/T5557/T5567/T5577 routines
1116 *------------------------------
1117 * NOTE: T55x7/T5555 configuration register definitions moved to protocols.h
1118 *
1119 * Relevant communication times in microsecond
1120 * To compensate antenna falling times shorten the write times
1121 * and enlarge the gap ones.
1122 * Q5 tags seems to have issues when these values changes.
1123 */
1124
1125 #define START_GAP 50*8 // was 250 // SPEC: 1*8 to 50*8 - typ 15*8 (15fc)
1126 #define WRITE_GAP 20*8 // was 160 // SPEC: 1*8 to 20*8 - typ 10*8 (10fc)
1127 #define WRITE_0 18*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (24fc)
1128 #define WRITE_1 54*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (56fc) 432 for T55x7; 448 for E5550
1129 #define READ_GAP 15*8
1130
1131 // VALUES TAKEN FROM EM4x function: SendForward
1132 // START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
1133 // WRITE_GAP = 128; (16*8)
1134 // WRITE_1 = 256 32*8; (32*8)
1135
1136 // These timings work for 4469/4269/4305 (with the 55*8 above)
1137 // WRITE_0 = 23*8 , 9*8
1138
1139 // Sam7s has several timers, we will use the source TIMER_CLOCK1 (aka AT91C_TC_CLKS_TIMER_DIV1_CLOCK)
1140 // TIMER_CLOCK1 = MCK/2, MCK is running at 48 MHz, Timer is running at 48/2 = 24 MHz
1141 // Hitag units (T0) have duration of 8 microseconds (us), which is 1/125000 per second (carrier)
1142 // T0 = TIMER_CLOCK1 / 125000 = 192
1143 // 1 Cycle = 8 microseconds(us) == 1 field clock
1144
1145 // new timer:
1146 // = 1us = 1.5ticks
1147 // 1fc = 8us = 12ticks
1148 void TurnReadLFOn(uint32_t delay) {
1149 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1150
1151 // measure antenna strength.
1152 //int adcval = ((MAX_ADC_LF_VOLTAGE * AvgAdc(ADC_CHAN_LF)) >> 10);
1153
1154 // Give it a bit of time for the resonant antenna to settle.
1155 WaitUS(delay);
1156 }
1157
1158 // Write one bit to card
1159 void T55xxWriteBit(int bit) {
1160 if (!bit)
1161 TurnReadLFOn(WRITE_0);
1162 else
1163 TurnReadLFOn(WRITE_1);
1164 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1165 WaitUS(WRITE_GAP);
1166 }
1167
1168 // Send T5577 reset command then read stream (see if we can identify the start of the stream)
1169 void T55xxResetRead(void) {
1170 LED_A_ON();
1171 //clear buffer now so it does not interfere with timing later
1172 BigBuf_Clear_keep_EM();
1173
1174 // Set up FPGA, 125kHz
1175 LFSetupFPGAForADC(95, true);
1176
1177 // Trigger T55x7 in mode.
1178 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1179 WaitUS(START_GAP);
1180
1181 // reset tag - op code 00
1182 T55xxWriteBit(0);
1183 T55xxWriteBit(0);
1184
1185 // Turn field on to read the response
1186 TurnReadLFOn(READ_GAP);
1187
1188 // Acquisition
1189 doT55x7Acquisition(BigBuf_max_traceLen());
1190
1191 // Turn the field off
1192 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1193 cmd_send(CMD_ACK,0,0,0,0,0);
1194 LED_A_OFF();
1195 }
1196
1197 // Write one card block in page 0, no lock
1198 void T55xxWriteBlockExt(uint32_t Data, uint8_t Block, uint32_t Pwd, uint8_t arg) {
1199 LED_A_ON();
1200 bool PwdMode = arg & 0x1;
1201 uint8_t Page = (arg & 0x2)>>1;
1202 uint32_t i = 0;
1203
1204 // Set up FPGA, 125kHz
1205 LFSetupFPGAForADC(95, true);
1206
1207 // Trigger T55x7 in mode.
1208 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1209 WaitUS(START_GAP);
1210
1211 // Opcode 10
1212 T55xxWriteBit(1);
1213 T55xxWriteBit(Page); //Page 0
1214 if (PwdMode){
1215 // Send Pwd
1216 for (i = 0x80000000; i != 0; i >>= 1)
1217 T55xxWriteBit(Pwd & i);
1218 }
1219 // Send Lock bit
1220 T55xxWriteBit(0);
1221
1222 // Send Data
1223 for (i = 0x80000000; i != 0; i >>= 1)
1224 T55xxWriteBit(Data & i);
1225
1226 // Send Block number
1227 for (i = 0x04; i != 0; i >>= 1)
1228 T55xxWriteBit(Block & i);
1229
1230 // Perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
1231 // so wait a little more)
1232 TurnReadLFOn(20 * 1000);
1233
1234 //could attempt to do a read to confirm write took
1235 // as the tag should repeat back the new block
1236 // until it is reset, but to confirm it we would
1237 // need to know the current block 0 config mode
1238
1239 // turn field off
1240 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1241 LED_A_OFF();
1242 }
1243
1244 // Write one card block in page 0, no lock
1245 void T55xxWriteBlock(uint32_t Data, uint8_t Block, uint32_t Pwd, uint8_t arg) {
1246 T55xxWriteBlockExt(Data, Block, Pwd, arg);
1247 cmd_send(CMD_ACK,0,0,0,0,0);
1248 }
1249
1250 // Read one card block in page [page]
1251 void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) {
1252 LED_A_ON();
1253 bool PwdMode = arg0 & 0x1;
1254 uint8_t Page = (arg0 & 0x2) >> 1;
1255 uint32_t i = 0;
1256 bool RegReadMode = (Block == 0xFF);
1257
1258 //clear buffer now so it does not interfere with timing later
1259 BigBuf_Clear_keep_EM();
1260
1261 //make sure block is at max 7
1262 Block &= 0x7;
1263
1264 // Set up FPGA, 125kHz to power up the tag
1265 LFSetupFPGAForADC(95, true);
1266 SpinDelay(3);
1267
1268 // Trigger T55x7 Direct Access Mode with start gap
1269 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1270 WaitUS(START_GAP);
1271
1272 // Opcode 1[page]
1273 T55xxWriteBit(1);
1274 T55xxWriteBit(Page); //Page 0
1275
1276 if (PwdMode){
1277 // Send Pwd
1278 for (i = 0x80000000; i != 0; i >>= 1)
1279 T55xxWriteBit(Pwd & i);
1280 }
1281 // Send a zero bit separation
1282 T55xxWriteBit(0);
1283
1284 // Send Block number (if direct access mode)
1285 if (!RegReadMode)
1286 for (i = 0x04; i != 0; i >>= 1)
1287 T55xxWriteBit(Block & i);
1288
1289 // Turn field on to read the response
1290 TurnReadLFOn(READ_GAP);
1291
1292 // Acquisition
1293 doT55x7Acquisition(12000);
1294
1295 // Turn the field off
1296 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1297 cmd_send(CMD_ACK,0,0,0,0,0);
1298 LED_A_OFF();
1299 }
1300
1301 void T55xxWakeUp(uint32_t Pwd){
1302 LED_B_ON();
1303 uint32_t i = 0;
1304
1305 // Set up FPGA, 125kHz
1306 LFSetupFPGAForADC(95, true);
1307
1308 // Trigger T55x7 Direct Access Mode
1309 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1310 WaitUS(START_GAP);
1311
1312 // Opcode 10
1313 T55xxWriteBit(1);
1314 T55xxWriteBit(0); //Page 0
1315
1316 // Send Pwd
1317 for (i = 0x80000000; i != 0; i >>= 1)
1318 T55xxWriteBit(Pwd & i);
1319
1320 // Turn and leave field on to let the begin repeating transmission
1321 TurnReadLFOn(20*1000);
1322 }
1323
1324 /*-------------- Cloning routines -----------*/
1325 void WriteT55xx(uint32_t *blockdata, uint8_t startblock, uint8_t numblocks) {
1326 // write last block first and config block last (if included)
1327 for (uint8_t i = numblocks+startblock; i > startblock; i--)
1328 T55xxWriteBlockExt(blockdata[i-1], i-1, 0, 0);
1329 }
1330
1331 // Copy HID id to card and setup block 0 config
1332 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT) {
1333 uint32_t data[] = {0,0,0,0,0,0,0};
1334 uint8_t last_block = 0;
1335
1336 if (longFMT){
1337 // Ensure no more than 84 bits supplied
1338 if (hi2 > 0xFFFFF) {
1339 DbpString("Tags can only have 84 bits.");
1340 return;
1341 }
1342 // Build the 6 data blocks for supplied 84bit ID
1343 last_block = 6;
1344 // load preamble (1D) & long format identifier (9E manchester encoded)
1345 data[1] = 0x1D96A900 | (manchesterEncode2Bytes((hi2 >> 16) & 0xF) & 0xFF);
1346 // load raw id from hi2, hi, lo to data blocks (manchester encoded)
1347 data[2] = manchesterEncode2Bytes(hi2 & 0xFFFF);
1348 data[3] = manchesterEncode2Bytes(hi >> 16);
1349 data[4] = manchesterEncode2Bytes(hi & 0xFFFF);
1350 data[5] = manchesterEncode2Bytes(lo >> 16);
1351 data[6] = manchesterEncode2Bytes(lo & 0xFFFF);
1352 } else {
1353 // Ensure no more than 44 bits supplied
1354 if (hi > 0xFFF) {
1355 DbpString("Tags can only have 44 bits.");
1356 return;
1357 }
1358 // Build the 3 data blocks for supplied 44bit ID
1359 last_block = 3;
1360 // load preamble
1361 data[1] = 0x1D000000 | (manchesterEncode2Bytes(hi) & 0xFFFFFF);
1362 data[2] = manchesterEncode2Bytes(lo >> 16);
1363 data[3] = manchesterEncode2Bytes(lo & 0xFFFF);
1364 }
1365 // load chip config block
1366 data[0] = T55x7_BITRATE_RF_50 | T55x7_MODULATION_FSK2a | last_block << T55x7_MAXBLOCK_SHIFT;
1367
1368 //TODO add selection of chip for Q5 or T55x7
1369 // data[0] = (((50-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | last_block << T5555_MAXBLOCK_SHIFT;
1370
1371 LED_D_ON();
1372 // Program the data blocks for supplied ID
1373 // and the block 0 for HID format
1374 WriteT55xx(data, 0, last_block+1);
1375
1376 LED_D_OFF();
1377
1378 DbpString("DONE!");
1379 }
1380
1381 void CopyIOtoT55x7(uint32_t hi, uint32_t lo) {
1382 uint32_t data[] = {T55x7_BITRATE_RF_64 | T55x7_MODULATION_FSK2a | (2 << T55x7_MAXBLOCK_SHIFT), hi, lo};
1383 //TODO add selection of chip for Q5 or T55x7
1384 //t5555 (Q5) BITRATE = (RF-2)/2 (iceman)
1385 // data[0] = (64 << T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | 2 << T5555_MAXBLOCK_SHIFT;
1386
1387 LED_D_ON();
1388 // Program the data blocks for supplied ID
1389 // and the block 0 config
1390 WriteT55xx(data, 0, 3);
1391 LED_D_OFF();
1392 DbpString("DONE!");
1393 }
1394
1395 // Clone Indala 64-bit tag by UID to T55x7
1396 void CopyIndala64toT55x7(uint32_t hi, uint32_t lo) {
1397 //Program the 2 data blocks for supplied 64bit UID
1398 // and the Config for Indala 64 format (RF/32;PSK1 with RF/2;Maxblock=2)
1399 uint32_t data[] = { T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | (2 << T55x7_MAXBLOCK_SHIFT), hi, lo};
1400 //TODO add selection of chip for Q5 or T55x7
1401 // data[0] = (((32-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_PSK1 | 2 << T5555_MAXBLOCK_SHIFT;
1402
1403 WriteT55xx(data, 0, 3);
1404 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1405 // T5567WriteBlock(0x603E1042,0);
1406 DbpString("DONE!");
1407 }
1408 // Clone Indala 224-bit tag by UID to T55x7
1409 void CopyIndala224toT55x7(uint32_t uid1, uint32_t uid2, uint32_t uid3, uint32_t uid4, uint32_t uid5, uint32_t uid6, uint32_t uid7) {
1410 //Program the 7 data blocks for supplied 224bit UID
1411 uint32_t data[] = {0, uid1, uid2, uid3, uid4, uid5, uid6, uid7};
1412 // and the block 0 for Indala224 format
1413 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1414 data[0] = T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | (7 << T55x7_MAXBLOCK_SHIFT);
1415 //TODO add selection of chip for Q5 or T55x7
1416 // data[0] = (((32-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_PSK1 | 7 << T5555_MAXBLOCK_SHIFT;
1417 WriteT55xx(data, 0, 8);
1418 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1419 // T5567WriteBlock(0x603E10E2,0);
1420 DbpString("DONE!");
1421 }
1422 // clone viking tag to T55xx
1423 void CopyVikingtoT55xx(uint32_t block1, uint32_t block2, uint8_t Q5) {
1424 uint32_t data[] = {T55x7_BITRATE_RF_32 | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT), block1, block2};
1425 //t5555 (Q5) BITRATE = (RF-2)/2 (iceman)
1426 if (Q5) data[0] = (32 << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | 2 << T5555_MAXBLOCK_SHIFT;
1427 // Program the data blocks for supplied ID and the block 0 config
1428 WriteT55xx(data, 0, 3);
1429 LED_D_OFF();
1430 cmd_send(CMD_ACK,0,0,0,0,0);
1431 }
1432
1433 // Define 9bit header for EM410x tags
1434 #define EM410X_HEADER 0x1FF
1435 #define EM410X_ID_LENGTH 40
1436
1437 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo) {
1438 int i, id_bit;
1439 uint64_t id = EM410X_HEADER;
1440 uint64_t rev_id = 0; // reversed ID
1441 int c_parity[4]; // column parity
1442 int r_parity = 0; // row parity
1443 uint32_t clock = 0;
1444
1445 // Reverse ID bits given as parameter (for simpler operations)
1446 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1447 if (i < 32) {
1448 rev_id = (rev_id << 1) | (id_lo & 1);
1449 id_lo >>= 1;
1450 } else {
1451 rev_id = (rev_id << 1) | (id_hi & 1);
1452 id_hi >>= 1;
1453 }
1454 }
1455
1456 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1457 id_bit = rev_id & 1;
1458
1459 if (i % 4 == 0) {
1460 // Don't write row parity bit at start of parsing
1461 if (i)
1462 id = (id << 1) | r_parity;
1463 // Start counting parity for new row
1464 r_parity = id_bit;
1465 } else {
1466 // Count row parity
1467 r_parity ^= id_bit;
1468 }
1469
1470 // First elements in column?
1471 if (i < 4)
1472 // Fill out first elements
1473 c_parity[i] = id_bit;
1474 else
1475 // Count column parity
1476 c_parity[i % 4] ^= id_bit;
1477
1478 // Insert ID bit
1479 id = (id << 1) | id_bit;
1480 rev_id >>= 1;
1481 }
1482
1483 // Insert parity bit of last row
1484 id = (id << 1) | r_parity;
1485
1486 // Fill out column parity at the end of tag
1487 for (i = 0; i < 4; ++i)
1488 id = (id << 1) | c_parity[i];
1489
1490 // Add stop bit
1491 id <<= 1;
1492
1493 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1494 LED_D_ON();
1495
1496 // Write EM410x ID
1497 uint32_t data[] = {0, (uint32_t)(id>>32), (uint32_t)(id & 0xFFFFFFFF)};
1498
1499 clock = (card & 0xFF00) >> 8;
1500 clock = (clock == 0) ? 64 : clock;
1501 Dbprintf("Clock rate: %d", clock);
1502 if (card & 0xFF) { //t55x7
1503 clock = GetT55xxClockBit(clock);
1504 if (clock == 0) {
1505 Dbprintf("Invalid clock rate: %d", clock);
1506 return;
1507 }
1508 data[0] = clock | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT);
1509 } else { //t5555 (Q5)
1510 clock = (clock-2)>>1; //n = (RF-2)/2
1511 data[0] = (clock << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | (2 << T5555_MAXBLOCK_SHIFT);
1512 }
1513
1514 WriteT55xx(data, 0, 3);
1515
1516 LED_D_OFF();
1517 Dbprintf("Tag %s written with 0x%08x%08x\n",
1518 card ? "T55x7":"T5555",
1519 (uint32_t)(id >> 32),
1520 (uint32_t)id);
1521 }
1522
1523 //-----------------------------------
1524 // EM4469 / EM4305 routines
1525 //-----------------------------------
1526 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1527 #define FWD_CMD_WRITE 0xA
1528 #define FWD_CMD_READ 0x9
1529 #define FWD_CMD_DISABLE 0x5
1530
1531 uint8_t forwardLink_data[64]; //array of forwarded bits
1532 uint8_t * forward_ptr; //ptr for forward message preparation
1533 uint8_t fwd_bit_sz; //forwardlink bit counter
1534 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1535
1536 //====================================================================
1537 // prepares command bits
1538 // see EM4469 spec
1539 //====================================================================
1540 //--------------------------------------------------------------------
1541 // VALUES TAKEN FROM EM4x function: SendForward
1542 // START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
1543 // WRITE_GAP = 128; (16*8)
1544 // WRITE_1 = 256 32*8; (32*8)
1545
1546 // These timings work for 4469/4269/4305 (with the 55*8 above)
1547 // WRITE_0 = 23*8 , 9*8
1548
1549 uint8_t Prepare_Cmd( uint8_t cmd ) {
1550
1551 *forward_ptr++ = 0; //start bit
1552 *forward_ptr++ = 0; //second pause for 4050 code
1553
1554 *forward_ptr++ = cmd;
1555 cmd >>= 1;
1556 *forward_ptr++ = cmd;
1557 cmd >>= 1;
1558 *forward_ptr++ = cmd;
1559 cmd >>= 1;
1560 *forward_ptr++ = cmd;
1561
1562 return 6; //return number of emited bits
1563 }
1564
1565 //====================================================================
1566 // prepares address bits
1567 // see EM4469 spec
1568 //====================================================================
1569 uint8_t Prepare_Addr( uint8_t addr ) {
1570
1571 register uint8_t line_parity;
1572
1573 uint8_t i;
1574 line_parity = 0;
1575 for(i=0;i<6;i++) {
1576 *forward_ptr++ = addr;
1577 line_parity ^= addr;
1578 addr >>= 1;
1579 }
1580
1581 *forward_ptr++ = (line_parity & 1);
1582
1583 return 7; //return number of emited bits
1584 }
1585
1586 //====================================================================
1587 // prepares data bits intreleaved with parity bits
1588 // see EM4469 spec
1589 //====================================================================
1590 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1591
1592 register uint8_t line_parity;
1593 register uint8_t column_parity;
1594 register uint8_t i, j;
1595 register uint16_t data;
1596
1597 data = data_low;
1598 column_parity = 0;
1599
1600 for(i=0; i<4; i++) {
1601 line_parity = 0;
1602 for(j=0; j<8; j++) {
1603 line_parity ^= data;
1604 column_parity ^= (data & 1) << j;
1605 *forward_ptr++ = data;
1606 data >>= 1;
1607 }
1608 *forward_ptr++ = line_parity;
1609 if(i == 1)
1610 data = data_hi;
1611 }
1612
1613 for(j=0; j<8; j++) {
1614 *forward_ptr++ = column_parity;
1615 column_parity >>= 1;
1616 }
1617 *forward_ptr = 0;
1618
1619 return 45; //return number of emited bits
1620 }
1621
1622 //====================================================================
1623 // Forward Link send function
1624 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1625 // fwd_bit_count set with number of bits to be sent
1626 //====================================================================
1627 void SendForward(uint8_t fwd_bit_count) {
1628
1629 fwd_write_ptr = forwardLink_data;
1630 fwd_bit_sz = fwd_bit_count;
1631
1632 LED_D_ON();
1633
1634 // Set up FPGA, 125kHz
1635 LFSetupFPGAForADC(95, true);
1636
1637 // force 1st mod pulse (start gap must be longer for 4305)
1638 fwd_bit_sz--; //prepare next bit modulation
1639 fwd_write_ptr++;
1640 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1641 WaitUS(55*8); //55 cycles off (8us each)for 4305 // ICEMAN: problem with (us) clock is 21.3us increments
1642 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1643 WaitUS(16*8); //16 cycles on (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
1644
1645 // now start writting
1646 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1647 if(((*fwd_write_ptr++) & 1) == 1)
1648 WaitUS(32*8); //32 cycles at 125Khz (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
1649 else {
1650 //These timings work for 4469/4269/4305 (with the 55*8 above)
1651 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1652 WaitUS(16*8); //16-4 cycles off (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
1653 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1654 WaitUS(16*8); //16 cycles on (8us each) // ICEMAN: problem with (us) clock is 21.3us increments
1655 }
1656 }
1657 }
1658
1659 void EM4xLogin(uint32_t Password) {
1660
1661 uint8_t fwd_bit_count;
1662 forward_ptr = forwardLink_data;
1663 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1664 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1665 SendForward(fwd_bit_count);
1666
1667 //Wait for command to complete
1668 WaitMS(20);
1669 }
1670
1671 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1672
1673 uint8_t fwd_bit_count;
1674 uint8_t *dest = BigBuf_get_addr();
1675 uint16_t bufsize = BigBuf_max_traceLen(); // ICEMAN: this tries to fill up all tracelog space
1676 uint32_t i = 0;
1677
1678 // Clear destination buffer before sending the command
1679 BigBuf_Clear_ext(false);
1680
1681 //If password mode do login
1682 if (PwdMode == 1) EM4xLogin(Pwd);
1683
1684 forward_ptr = forwardLink_data;
1685 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1686 fwd_bit_count += Prepare_Addr( Address );
1687
1688 SendForward(fwd_bit_count);
1689
1690 // Now do the acquisition
1691 // ICEMAN, change to the one in lfsampling.c
1692 i = 0;
1693 for(;;) {
1694 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1695 AT91C_BASE_SSC->SSC_THR = 0x43;
1696 }
1697 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1698 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1699 ++i;
1700 if (i >= bufsize) break;
1701 }
1702 }
1703
1704 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1705 cmd_send(CMD_ACK,0,0,0,0,0);
1706 LED_D_OFF();
1707 }
1708
1709 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1710
1711 uint8_t fwd_bit_count;
1712
1713 //If password mode do login
1714 if (PwdMode == 1) EM4xLogin(Pwd);
1715
1716 forward_ptr = forwardLink_data;
1717 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1718 fwd_bit_count += Prepare_Addr( Address );
1719 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1720
1721 SendForward(fwd_bit_count);
1722
1723 //Wait for write to complete
1724 WaitMS(20);
1725 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1726 LED_D_OFF();
1727 }
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