1 //-----------------------------------------------------------------------------
2 // Miscellaneous routines for low frequency tag operations.
3 // Tags supported here so far are Texas Instruments (TI), HID
4 // Also routines for raw mode reading/simulating of LF waveform
6 //-----------------------------------------------------------------------------
10 #include "../common/crc16.c"
12 int sprintf(char *dest
, const char *fmt
, ...);
14 void AcquireRawAdcSamples125k(BOOL at134khz
)
17 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 88); //134.8Khz
18 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER
);
20 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
21 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER
);
24 // Connect the A/D to the peak-detected low-frequency path.
25 SetAdcMuxFor(GPIO_MUXSEL_LOPKD
);
27 // Give it a bit of time for the resonant antenna to settle.
30 // Now set up the SSC to get the ADC samples that are now streaming at us.
33 // Now call the acquisition routine
34 DoAcquisition125k(at134khz
);
37 // split into two routines so we can avoid timing issues after sending commands //
38 void DoAcquisition125k(BOOL at134khz
)
40 BYTE
*dest
= (BYTE
*)BigBuf
;
41 int n
= sizeof(BigBuf
);
43 char output_string
[64];
48 if (AT91C_BASE_SSC
->SSC_SR
& AT91C_SSC_TXRDY
) {
49 AT91C_BASE_SSC
->SSC_THR
= 0x43;
52 if(AT91C_BASE_SSC
->SSC_SR
& AT91C_SSC_RXRDY
) {
53 dest
[i
] = (BYTE
)AT91C_BASE_SSC
->SSC_RHR
;
59 sprintf(output_string
, "read samples, dest[0]=%x dest[1]=%x at134khz=%d",
60 dest
[0], dest
[1], at134khz
);
61 DbpString(output_string
);
64 void ModThenAcquireRawAdcSamples125k(int delay_off
,int period_0
,int period_1
,BYTE
*command
)
68 /* Make sure the tag is reset */
69 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
72 // see if 'h' was specified
73 if(command
[strlen((char *) command
) - 1] == 'h')
79 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 88); //134.8Khz
80 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER
);
82 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
83 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER
);
86 // Give it a bit of time for the resonant antenna to settle.
88 // And a little more time for the tag to fully power up
91 // Now set up the SSC to get the ADC samples that are now streaming at us.
94 // now modulate the reader field
95 while(*command
!= '\0' && *command
!= ' ')
97 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
99 SpinDelayUs(delay_off
);
101 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 88); //134.8Khz
102 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER
);
104 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
105 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER
);
108 if(*(command
++) == '0') {
109 SpinDelayUs(period_0
);
111 SpinDelayUs(period_1
);
114 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
116 SpinDelayUs(delay_off
);
118 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 88); //134.8Khz
119 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER
);
121 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
122 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER
);
126 DoAcquisition125k(at134khz
);
129 /* blank r/w tag data stream
130 ...0000000000000000 01111111
131 1010101010101010101010101010101010101010101010101010101010101010
134 101010101010101[0]000...
136 [5555fe852c5555555555555555fe0000]
140 // some hardcoded initial params
141 // when we read a TI tag we sample the zerocross line at 2Mhz
142 // TI tags modulate a 1 as 16 cycles of 123.2Khz
143 // TI tags modulate a 0 as 16 cycles of 134.2Khz
144 #define FSAMPLE 2000000
145 #define FREQLO 123200
146 #define FREQHI 134200
148 signed char *dest
= (signed char *)BigBuf
;
149 int n
= sizeof(BigBuf
);
150 // int *dest = GraphBuffer;
151 // int n = GraphTraceLen;
153 // 128 bit shift register [shift3:shift2:shift1:shift0]
154 DWORD shift3
= 0, shift2
= 0, shift1
= 0, shift0
= 0;
156 int i
, cycles
=0, samples
=0;
157 // how many sample points fit in 16 cycles of each frequency
158 DWORD sampleslo
= (FSAMPLE
<<4)/FREQLO
, sampleshi
= (FSAMPLE
<<4)/FREQHI
;
159 // when to tell if we're close enough to one freq or another
160 DWORD threshold
= (sampleslo
- sampleshi
+ 1)>>1;
162 // TI tags charge at 134.2Khz
163 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 88); //134.8Khz
165 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
166 // connects to SSP_DIN and the SSP_DOUT logic level controls
167 // whether we're modulating the antenna (high)
168 // or listening to the antenna (low)
169 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU
);
171 // get TI tag data into the buffer
174 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
176 for (i
=0; i
<n
-1; i
++) {
177 // count cycles by looking for lo to hi zero crossings
178 if ( (dest
[i
]<0) && (dest
[i
+1]>0) ) {
180 // after 16 cycles, measure the frequency
183 samples
=i
-samples
; // number of samples in these 16 cycles
185 // TI bits are coming to us lsb first so shift them
186 // right through our 128 bit right shift register
187 shift0
= (shift0
>>1) | (shift1
<< 31);
188 shift1
= (shift1
>>1) | (shift2
<< 31);
189 shift2
= (shift2
>>1) | (shift3
<< 31);
192 // check if the cycles fall close to the number
193 // expected for either the low or high frequency
194 if ( (samples
>(sampleslo
-threshold
)) && (samples
<(sampleslo
+threshold
)) ) {
195 // low frequency represents a 1
197 } else if ( (samples
>(sampleshi
-threshold
)) && (samples
<(sampleshi
+threshold
)) ) {
198 // high frequency represents a 0
200 // probably detected a gay waveform or noise
201 // use this as gaydar or discard shift register and start again
202 shift3
= shift2
= shift1
= shift0
= 0;
206 // for each bit we receive, test if we've detected a valid tag
208 // if we see 17 zeroes followed by 6 ones, we might have a tag
209 // remember the bits are backwards
210 if ( ((shift0
& 0x7fffff) == 0x7e0000) ) {
211 // if start and end bytes match, we have a tag so break out of the loop
212 if ( ((shift0
>>16)&0xff) == ((shift3
>>8)&0xff) ) {
213 cycles
= 0xF0B; //use this as a flag (ugly but whatever)
221 // if flag is set we have a tag
223 DbpString("Info: No valid tag detected.");
225 // put 64 bit data into shift1 and shift0
226 shift0
= (shift0
>>24) | (shift1
<< 8);
227 shift1
= (shift1
>>24) | (shift2
<< 8);
229 // align 16 bit crc into lower half of shift2
230 shift2
= ((shift2
>>24) | (shift3
<< 8)) & 0x0ffff;
232 // if r/w tag, check ident match
233 if ( shift3
&(1<<15) ) {
234 DbpString("Info: TI tag is rewriteable");
235 // only 15 bits compare, last bit of ident is not valid
236 if ( ((shift3
>>16)^shift0
)&0x7fff ) {
237 DbpString("Error: Ident mismatch!");
239 DbpString("Info: TI tag ident is valid");
242 DbpString("Info: TI tag is readonly");
245 // WARNING the order of the bytes in which we calc crc below needs checking
246 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
247 // bytes in reverse or something
251 crc
= update_crc16(crc
, (shift0
)&0xff);
252 crc
= update_crc16(crc
, (shift0
>>8)&0xff);
253 crc
= update_crc16(crc
, (shift0
>>16)&0xff);
254 crc
= update_crc16(crc
, (shift0
>>24)&0xff);
255 crc
= update_crc16(crc
, (shift1
)&0xff);
256 crc
= update_crc16(crc
, (shift1
>>8)&0xff);
257 crc
= update_crc16(crc
, (shift1
>>16)&0xff);
258 crc
= update_crc16(crc
, (shift1
>>24)&0xff);
260 char output_string
[64];
261 sprintf(output_string
, "Info: Tag data_hi=%x, data_lo=%x, crc=%x",
262 (unsigned int)shift1
, (unsigned int)shift0
, (unsigned int)shift2
& 0xFFFF);
263 DbpString(output_string
);
264 if (crc
!= (shift2
&0xffff)) {
265 sprintf(output_string
, "Error: CRC mismatch, expected %x", (unsigned int)crc
);
266 DbpString(output_string
);
268 DbpString("Info: CRC is good");
273 void WriteTIbyte(BYTE b
)
277 // modulate 8 bits out to the antenna
281 // stop modulating antenna
288 // stop modulating antenna
298 void AcquireTiType(void)
301 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
302 // each sample is 1 bit stuffed into a DWORD so we need 1250 DWORDS
303 #define TIBUFLEN 1250
306 memset(BigBuf
,0,sizeof(BigBuf
));
308 // Set up the synchronous serial port
309 AT91C_BASE_PIOA
->PIO_PDR
= GPIO_SSC_DIN
;
310 AT91C_BASE_PIOA
->PIO_ASR
= GPIO_SSC_DIN
;
312 // steal this pin from the SSP and use it to control the modulation
313 AT91C_BASE_PIOA
->PIO_PER
= GPIO_SSC_DOUT
;
314 AT91C_BASE_PIOA
->PIO_OER
= GPIO_SSC_DOUT
;
316 AT91C_BASE_SSC
->SSC_CR
= AT91C_SSC_SWRST
;
317 AT91C_BASE_SSC
->SSC_CR
= AT91C_SSC_RXEN
| AT91C_SSC_TXEN
;
319 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
320 // 48/2 = 24 MHz clock must be divided by 12
321 AT91C_BASE_SSC
->SSC_CMR
= 12;
323 AT91C_BASE_SSC
->SSC_RCMR
= SSC_CLOCK_MODE_SELECT(0);
324 AT91C_BASE_SSC
->SSC_RFMR
= SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF
;
325 AT91C_BASE_SSC
->SSC_TCMR
= 0;
326 AT91C_BASE_SSC
->SSC_TFMR
= 0;
333 // Charge TI tag for 50ms.
336 // stop modulating antenna and listen
343 if(AT91C_BASE_SSC
->SSC_SR
& AT91C_SSC_RXRDY
) {
344 BigBuf
[i
] = AT91C_BASE_SSC
->SSC_RHR
; // store 32 bit values in buffer
345 i
++; if(i
>= TIBUFLEN
) break;
350 // return stolen pin to SSP
351 AT91C_BASE_PIOA
->PIO_PDR
= GPIO_SSC_DOUT
;
352 AT91C_BASE_PIOA
->PIO_ASR
= GPIO_SSC_DIN
| GPIO_SSC_DOUT
;
354 char *dest
= (char *)BigBuf
;
357 for (i
=TIBUFLEN
-1; i
>=0; i
--) {
358 // DbpIntegers(0, 0, BigBuf[i]);
359 for (j
=0; j
<32; j
++) {
360 if(BigBuf
[i
] & (1 << j
)) {
369 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
370 // if crc provided, it will be written with the data verbatim (even if bogus)
371 // if not provided a valid crc will be computed from the data and written.
372 void WriteTItag(DWORD idhi
, DWORD idlo
, WORD crc
)
375 // WARNING the order of the bytes in which we calc crc below needs checking
376 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
377 // bytes in reverse or something
380 crc
= update_crc16(crc
, (idlo
)&0xff);
381 crc
= update_crc16(crc
, (idlo
>>8)&0xff);
382 crc
= update_crc16(crc
, (idlo
>>16)&0xff);
383 crc
= update_crc16(crc
, (idlo
>>24)&0xff);
384 crc
= update_crc16(crc
, (idhi
)&0xff);
385 crc
= update_crc16(crc
, (idhi
>>8)&0xff);
386 crc
= update_crc16(crc
, (idhi
>>16)&0xff);
387 crc
= update_crc16(crc
, (idhi
>>24)&0xff);
389 char output_string
[64];
390 sprintf(output_string
, "Writing the following data to tag: %x, %x, %x",
391 (unsigned int) idhi
, (unsigned int) idlo
, crc
);
392 DbpString(output_string
);
394 // TI tags charge at 134.2Khz
395 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 88); //134.8Khz
396 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
397 // connects to SSP_DIN and the SSP_DOUT logic level controls
398 // whether we're modulating the antenna (high)
399 // or listening to the antenna (low)
400 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU
);
403 // steal this pin from the SSP and use it to control the modulation
404 AT91C_BASE_PIOA
->PIO_PER
= GPIO_SSC_DOUT
;
405 AT91C_BASE_PIOA
->PIO_OER
= GPIO_SSC_DOUT
;
407 // writing algorithm:
408 // a high bit consists of a field off for 1ms and field on for 1ms
409 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
410 // initiate a charge time of 50ms (field on) then immediately start writing bits
411 // start by writing 0xBB (keyword) and 0xEB (password)
412 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
413 // finally end with 0x0300 (write frame)
414 // all data is sent lsb firts
415 // finish with 15ms programming time
419 SpinDelay(50); // charge time
421 WriteTIbyte(0xbb); // keyword
422 WriteTIbyte(0xeb); // password
423 WriteTIbyte( (idlo
)&0xff );
424 WriteTIbyte( (idlo
>>8 )&0xff );
425 WriteTIbyte( (idlo
>>16)&0xff );
426 WriteTIbyte( (idlo
>>24)&0xff );
427 WriteTIbyte( (idhi
)&0xff );
428 WriteTIbyte( (idhi
>>8 )&0xff );
429 WriteTIbyte( (idhi
>>16)&0xff );
430 WriteTIbyte( (idhi
>>24)&0xff ); // data hi to lo
431 WriteTIbyte( (crc
)&0xff ); // crc lo
432 WriteTIbyte( (crc
>>8 )&0xff ); // crc hi
433 WriteTIbyte(0x00); // write frame lo
434 WriteTIbyte(0x03); // write frame hi
436 SpinDelay(50); // programming time
440 // get TI tag data into the buffer
443 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF
);
444 DbpString("Now use tiread to check");
447 void SimulateTagLowFrequency(int period
, int ledcontrol
)
450 BYTE
*tab
= (BYTE
*)BigBuf
;
452 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_SIMULATOR
);
454 AT91C_BASE_PIOA
->PIO_PER
= GPIO_SSC_DOUT
| GPIO_SSC_CLK
;
456 AT91C_BASE_PIOA
->PIO_OER
= GPIO_SSC_DOUT
;
457 AT91C_BASE_PIOA
->PIO_ODR
= GPIO_SSC_CLK
;
459 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
460 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
464 while(!(AT91C_BASE_PIOA
->PIO_PDSR
& GPIO_SSC_CLK
)) {
466 DbpString("Stopped");
483 while(AT91C_BASE_PIOA
->PIO_PDSR
& GPIO_SSC_CLK
) {
485 DbpString("Stopped");
492 if(i
== period
) i
= 0;
496 /* Provides a framework for bidirectional LF tag communication
497 * Encoding is currently Hitag2, but the general idea can probably
498 * be transferred to other encodings.
500 * The new FPGA code will, for the LF simulator mode, give on SSC_FRAME
501 * (PA15) a thresholded version of the signal from the ADC. Setting the
502 * ADC path to the low frequency peak detection signal, will enable a
503 * somewhat reasonable receiver for modulation on the carrier signal
504 * that is generated by the reader. The signal is low when the reader
505 * field is switched off, and high when the reader field is active. Due
506 * to the way that the signal looks like, mostly only the rising edge is
507 * useful, your mileage may vary.
509 * Neat perk: PA15 can not only be used as a bit-banging GPIO, but is also
510 * TIOA1, which can be used as the capture input for timer 1. This should
511 * make it possible to measure the exact edge-to-edge time, without processor
514 * Arguments: divisor is the divisor to be sent to the FPGA (e.g. 95 for 125kHz)
515 * t0 is the carrier frequency cycle duration in terms of MCK (384 for 125kHz)
517 * The following defines are in carrier periods:
519 #define HITAG_T_0_MIN 15 /* T[0] should be 18..22 */
520 #define HITAG_T_1_MIN 24 /* T[1] should be 26..30 */
521 #define HITAG_T_EOF 40 /* T_EOF should be > 36 */
522 #define HITAG_T_WRESP 208 /* T_wresp should be 204..212 */
524 static void hitag_handle_frame(int t0
, int frame_len
, char *frame
);
525 //#define DEBUG_RA_VALUES 1
526 #define DEBUG_FRAME_CONTENTS 1
527 void SimulateTagLowFrequencyBidir(int divisor
, int t0
)
529 #if DEBUG_RA_VALUES || DEBUG_FRAME_CONTENTS
535 DbpString("Starting Hitag2 emulator, press button to end");
538 /* Set up simulator mode, frequency divisor which will drive the FPGA
539 * and analog mux selection.
541 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_SIMULATOR
);
542 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, divisor
);
543 SetAdcMuxFor(GPIO_MUXSEL_LOPKD
);
547 * Capture mode, timer source MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
548 * external trigger rising edge, load RA on rising edge of TIOA, load RB on rising
549 * edge of TIOA. Assign PA15 to TIOA1 (peripheral B)
552 AT91C_BASE_PMC
->PMC_PCER
= (1 << AT91C_ID_TC1
);
553 AT91C_BASE_PIOA
->PIO_BSR
= GPIO_SSC_FRAME
;
554 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKDIS
;
555 AT91C_BASE_TC1
->TC_CMR
= TC_CMR_TCCLKS_TIMER_CLOCK1
|
556 AT91C_TC_ETRGEDG_RISING
|
558 AT91C_TC_LDRA_RISING
|
559 AT91C_TC_LDRB_RISING
;
560 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_CLKEN
|
563 /* calculate the new value for the carrier period in terms of TC1 values */
567 while(!BUTTON_PRESS()) {
569 if(AT91C_BASE_TC1
->TC_SR
& AT91C_TC_LDRAS
) {
570 int ra
= AT91C_BASE_TC1
->TC_RA
;
571 if((ra
> t0
*HITAG_T_EOF
) | overflow
) ra
= t0
*HITAG_T_EOF
+1;
573 if(ra
> 255 || overflow
) ra
= 255;
574 ((char*)BigBuf
)[i
] = ra
;
578 if(overflow
|| (ra
> t0
*HITAG_T_EOF
) || (ra
< t0
*HITAG_T_0_MIN
)) {
580 } else if(ra
>= t0
*HITAG_T_1_MIN
) {
582 if(frame_pos
< 8*sizeof(frame
)) {
583 frame
[frame_pos
/ 8] |= 1<<( 7-(frame_pos
%8) );
586 } else if(ra
>= t0
*HITAG_T_0_MIN
) {
588 if(frame_pos
< 8*sizeof(frame
)) {
589 frame
[frame_pos
/ 8] |= 0<<( 7-(frame_pos
%8) );
597 if(AT91C_BASE_TC1
->TC_CV
> t0
*HITAG_T_EOF
) {
598 /* Minor nuisance: In Capture mode, the timer can not be
599 * stopped by a Compare C. There's no way to stop the clock
600 * in software, so we'll just have to note the fact that an
601 * overflow happened and the next loaded timer value might
602 * have wrapped. Also, this marks the end of frame, and the
603 * still running counter can be used to determine the correct
604 * time for the start of the reply.
609 /* Have a frame, do something with it */
610 #if DEBUG_FRAME_CONTENTS
611 ((char*)BigBuf
)[i
++] = frame_pos
;
612 memcpy( ((char*)BigBuf
)+i
, frame
, 7);
614 i
= i
% sizeof(BigBuf
);
616 hitag_handle_frame(t0
, frame_pos
, frame
);
617 memset(frame
, 0, sizeof(frame
));
625 DbpString("All done");
628 static void hitag_send_bit(int t0
, int bit
) {
630 /* Manchester: Loaded, then unloaded */
633 while(AT91C_BASE_TC1
->TC_CV
< t0
*15);
635 while(AT91C_BASE_TC1
->TC_CV
< t0
*31);
637 } else if(bit
== 0) {
638 /* Manchester: Unloaded, then loaded */
641 while(AT91C_BASE_TC1
->TC_CV
< t0
*15);
643 while(AT91C_BASE_TC1
->TC_CV
< t0
*31);
646 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_SWTRG
; /* Reset clock for the next bit */
649 static void hitag_send_frame(int t0
, int frame_len
, const char const * frame
, int fdt
)
652 AT91C_BASE_PIOA
->PIO_OER
= GPIO_SSC_DOUT
;
654 /* Wait for HITAG_T_WRESP carrier periods after the last reader bit,
655 * not that since the clock counts since the rising edge, but T_wresp is
656 * with respect to the falling edge, we need to wait actually (T_wresp - T_g)
657 * periods. The gap time T_g varies (4..10).
659 while(AT91C_BASE_TC1
->TC_CV
< t0
*(fdt
-8));
661 int saved_cmr
= AT91C_BASE_TC1
->TC_CMR
;
662 AT91C_BASE_TC1
->TC_CMR
&= ~AT91C_TC_ETRGEDG
; /* Disable external trigger for the clock */
663 AT91C_BASE_TC1
->TC_CCR
= AT91C_TC_SWTRG
; /* Reset the clock and use it for response timing */
667 hitag_send_bit(t0
, 1); /* Start of frame */
669 for(i
=0; i
<frame_len
; i
++) {
670 hitag_send_bit(t0
, !!(frame
[i
/ 8] & (1<<( 7-(i
%8) ))) );
674 AT91C_BASE_TC1
->TC_CMR
= saved_cmr
;
677 /* Callback structure to cleanly separate tag emulation code from the radio layer. */
678 static int hitag_cb(const char* response_data
, const int response_length
, const int fdt
, void *cb_cookie
)
680 hitag_send_frame(*(int*)cb_cookie
, response_length
, response_data
, fdt
);
683 /* Frame length in bits, frame contents in MSBit first format */
684 static void hitag_handle_frame(int t0
, int frame_len
, char *frame
)
686 hitag2_handle_command(frame
, frame_len
, hitag_cb
, &t0
);
689 // compose fc/8 fc/10 waveform
690 static void fc(int c
, int *n
) {
691 BYTE
*dest
= (BYTE
*)BigBuf
;
694 // for when we want an fc8 pattern every 4 logical bits
705 // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples
707 for (idx
=0; idx
<6; idx
++) {
719 // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples
721 for (idx
=0; idx
<5; idx
++) {
736 // prepare a waveform pattern in the buffer based on the ID given then
737 // simulate a HID tag until the button is pressed
738 void CmdHIDsimTAG(int hi
, int lo
, int ledcontrol
)
742 HID tag bitstream format
743 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
744 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
745 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
746 A fc8 is inserted before every 4 bits
747 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
748 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
752 DbpString("Tags can only have 44 bits.");
756 // special start of frame marker containing invalid bit sequences
757 fc(8, &n
); fc(8, &n
); // invalid
758 fc(8, &n
); fc(10, &n
); // logical 0
759 fc(10, &n
); fc(10, &n
); // invalid
760 fc(8, &n
); fc(10, &n
); // logical 0
763 // manchester encode bits 43 to 32
764 for (i
=11; i
>=0; i
--) {
765 if ((i
%4)==3) fc(0,&n
);
767 fc(10, &n
); fc(8, &n
); // low-high transition
769 fc(8, &n
); fc(10, &n
); // high-low transition
774 // manchester encode bits 31 to 0
775 for (i
=31; i
>=0; i
--) {
776 if ((i
%4)==3) fc(0,&n
);
778 fc(10, &n
); fc(8, &n
); // low-high transition
780 fc(8, &n
); fc(10, &n
); // high-low transition
786 SimulateTagLowFrequency(n
, ledcontrol
);
793 // loop to capture raw HID waveform then FSK demodulate the TAG ID from it
794 void CmdHIDdemodFSK(int findone
, int *high
, int *low
, int ledcontrol
)
796 BYTE
*dest
= (BYTE
*)BigBuf
;
797 int m
=0, n
=0, i
=0, idx
=0, found
=0, lastval
=0;
800 FpgaSendCommand(FPGA_CMD_SET_DIVISOR
, 95); //125Khz
801 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER
);
803 // Connect the A/D to the peak-detected low-frequency path.
804 SetAdcMuxFor(GPIO_MUXSEL_LOPKD
);
806 // Give it a bit of time for the resonant antenna to settle.
809 // Now set up the SSC to get the ADC samples that are now streaming at us.
817 DbpString("Stopped");
827 if(AT91C_BASE_SSC
->SSC_SR
& (AT91C_SSC_TXRDY
)) {
828 AT91C_BASE_SSC
->SSC_THR
= 0x43;
832 if(AT91C_BASE_SSC
->SSC_SR
& (AT91C_SSC_RXRDY
)) {
833 dest
[i
] = (BYTE
)AT91C_BASE_SSC
->SSC_RHR
;
834 // we don't care about actual value, only if it's more or less than a
835 // threshold essentially we capture zero crossings for later analysis
836 if(dest
[i
] < 127) dest
[i
] = 0; else dest
[i
] = 1;
848 // sync to first lo-hi transition
849 for( idx
=1; idx
<m
; idx
++) {
850 if (dest
[idx
-1]<dest
[idx
])
856 // count cycles between consecutive lo-hi transitions, there should be either 8 (fc/8)
857 // or 10 (fc/10) cycles but in practice due to noise etc we may end up with with anywhere
858 // between 7 to 11 cycles so fuzz it by treat anything <9 as 8 and anything else as 10
859 for( i
=0; idx
<m
; idx
++) {
860 if (dest
[idx
-1]<dest
[idx
]) {
875 // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
880 for( idx
=0; idx
<m
; idx
++) {
881 if (dest
[idx
]==lastval
) {
884 // a bit time is five fc/10 or six fc/8 cycles so figure out how many bits a pattern width represents,
885 // an extra fc/8 pattern preceeds every 4 bits (about 200 cycles) just to complicate things but it gets
886 // swallowed up by rounding
887 // expected results are 1 or 2 bits, any more and it's an invalid manchester encoding
888 // special start of frame markers use invalid manchester states (no transitions) by using sequences
891 n
=(n
+1)/6; // fc/8 in sets of 6
893 n
=(n
+1)/5; // fc/10 in sets of 5
895 switch (n
) { // stuff appropriate bits in buffer
898 dest
[i
++]=dest
[idx
-1];
901 dest
[i
++]=dest
[idx
-1];
902 dest
[i
++]=dest
[idx
-1];
904 case 3: // 3 bit start of frame markers
905 dest
[i
++]=dest
[idx
-1];
906 dest
[i
++]=dest
[idx
-1];
907 dest
[i
++]=dest
[idx
-1];
909 // When a logic 0 is immediately followed by the start of the next transmisson
910 // (special pattern) a pattern of 4 bit duration lengths is created.
912 dest
[i
++]=dest
[idx
-1];
913 dest
[i
++]=dest
[idx
-1];
914 dest
[i
++]=dest
[idx
-1];
915 dest
[i
++]=dest
[idx
-1];
917 default: // this shouldn't happen, don't stuff any bits
927 // final loop, go over previously decoded manchester data and decode into usable tag ID
928 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
929 for( idx
=0; idx
<m
-6; idx
++) {
930 // search for a start of frame marker
931 if ( dest
[idx
] && dest
[idx
+1] && dest
[idx
+2] && (!dest
[idx
+3]) && (!dest
[idx
+4]) && (!dest
[idx
+5]) )
935 if (found
&& (hi
|lo
)) {
936 char output_string
[64];
937 sprintf(output_string
, "TAG ID: %x %x %x",
938 (unsigned int) hi
, (unsigned int) lo
, (unsigned int) (lo
>>1) & 0xFFFF);
939 DbpString(output_string
);
940 /* if we're only looking for one tag */
953 if (dest
[idx
] && (!dest
[idx
+1]) ) {
956 } else if ( (!dest
[idx
]) && dest
[idx
+1]) {
966 if ( dest
[idx
] && dest
[idx
+1] && dest
[idx
+2] && (!dest
[idx
+3]) && (!dest
[idx
+4]) && (!dest
[idx
+5]) )
970 if (found
&& (hi
|lo
)) {
971 char output_string
[64];
972 sprintf(output_string
, "TAG ID: %x %x %x",
973 (unsigned int) hi
, (unsigned int) lo
, (unsigned int) (lo
>>1) & 0xFFFF);
974 DbpString(output_string
);
975 /* if we're only looking for one tag */