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[proxmark3-svn] / armsrc / lfops.c
1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
10
11 #include "proxmark3.h"
12 #include "apps.h"
13 #include "util.h"
14 #include "hitag2.h"
15 #include "crc16.h"
16 #include "string.h"
17 #include "lfdemod.h"
18 #include "lfsampling.h"
19
20
21 /**
22 * Function to do a modulation and then get samples.
23 * @param delay_off
24 * @param period_0
25 * @param period_1
26 * @param command
27 */
28 void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
29 {
30
31 int divisor_used = 95; // 125 KHz
32 // see if 'h' was specified
33
34 if (command[strlen((char *) command) - 1] == 'h')
35 divisor_used = 88; // 134.8 KHz
36
37 sample_config sc = { 0,0,1, divisor_used, 0};
38 setSamplingConfig(&sc);
39
40 /* Make sure the tag is reset */
41 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
42 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
43 SpinDelay(2500);
44
45 LFSetupFPGAForADC(sc.divisor, 1);
46
47 // And a little more time for the tag to fully power up
48 SpinDelay(2000);
49
50 // now modulate the reader field
51 while(*command != '\0' && *command != ' ') {
52 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
53 LED_D_OFF();
54 SpinDelayUs(delay_off);
55 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
56
57 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
58 LED_D_ON();
59 if(*(command++) == '0')
60 SpinDelayUs(period_0);
61 else
62 SpinDelayUs(period_1);
63 }
64 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
65 LED_D_OFF();
66 SpinDelayUs(delay_off);
67 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
68
69 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
70
71 // now do the read
72 DoAcquisition_config(false);
73 }
74
75
76
77 /* blank r/w tag data stream
78 ...0000000000000000 01111111
79 1010101010101010101010101010101010101010101010101010101010101010
80 0011010010100001
81 01111111
82 101010101010101[0]000...
83
84 [5555fe852c5555555555555555fe0000]
85 */
86 void ReadTItag(void)
87 {
88 // some hardcoded initial params
89 // when we read a TI tag we sample the zerocross line at 2Mhz
90 // TI tags modulate a 1 as 16 cycles of 123.2Khz
91 // TI tags modulate a 0 as 16 cycles of 134.2Khz
92 #define FSAMPLE 2000000
93 #define FREQLO 123200
94 #define FREQHI 134200
95
96 signed char *dest = (signed char *)BigBuf_get_addr();
97 uint16_t n = BigBuf_max_traceLen();
98 // 128 bit shift register [shift3:shift2:shift1:shift0]
99 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
100
101 int i, cycles=0, samples=0;
102 // how many sample points fit in 16 cycles of each frequency
103 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
104 // when to tell if we're close enough to one freq or another
105 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
106
107 // TI tags charge at 134.2Khz
108 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
109 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
110
111 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
112 // connects to SSP_DIN and the SSP_DOUT logic level controls
113 // whether we're modulating the antenna (high)
114 // or listening to the antenna (low)
115 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
116
117 // get TI tag data into the buffer
118 AcquireTiType();
119
120 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
121
122 for (i=0; i<n-1; i++) {
123 // count cycles by looking for lo to hi zero crossings
124 if ( (dest[i]<0) && (dest[i+1]>0) ) {
125 cycles++;
126 // after 16 cycles, measure the frequency
127 if (cycles>15) {
128 cycles=0;
129 samples=i-samples; // number of samples in these 16 cycles
130
131 // TI bits are coming to us lsb first so shift them
132 // right through our 128 bit right shift register
133 shift0 = (shift0>>1) | (shift1 << 31);
134 shift1 = (shift1>>1) | (shift2 << 31);
135 shift2 = (shift2>>1) | (shift3 << 31);
136 shift3 >>= 1;
137
138 // check if the cycles fall close to the number
139 // expected for either the low or high frequency
140 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
141 // low frequency represents a 1
142 shift3 |= (1<<31);
143 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
144 // high frequency represents a 0
145 } else {
146 // probably detected a gay waveform or noise
147 // use this as gaydar or discard shift register and start again
148 shift3 = shift2 = shift1 = shift0 = 0;
149 }
150 samples = i;
151
152 // for each bit we receive, test if we've detected a valid tag
153
154 // if we see 17 zeroes followed by 6 ones, we might have a tag
155 // remember the bits are backwards
156 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
157 // if start and end bytes match, we have a tag so break out of the loop
158 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
159 cycles = 0xF0B; //use this as a flag (ugly but whatever)
160 break;
161 }
162 }
163 }
164 }
165 }
166
167 // if flag is set we have a tag
168 if (cycles!=0xF0B) {
169 DbpString("Info: No valid tag detected.");
170 } else {
171 // put 64 bit data into shift1 and shift0
172 shift0 = (shift0>>24) | (shift1 << 8);
173 shift1 = (shift1>>24) | (shift2 << 8);
174
175 // align 16 bit crc into lower half of shift2
176 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
177
178 // if r/w tag, check ident match
179 if (shift3 & (1<<15) ) {
180 DbpString("Info: TI tag is rewriteable");
181 // only 15 bits compare, last bit of ident is not valid
182 if (((shift3 >> 16) ^ shift0) & 0x7fff ) {
183 DbpString("Error: Ident mismatch!");
184 } else {
185 DbpString("Info: TI tag ident is valid");
186 }
187 } else {
188 DbpString("Info: TI tag is readonly");
189 }
190
191 // WARNING the order of the bytes in which we calc crc below needs checking
192 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
193 // bytes in reverse or something
194 // calculate CRC
195 uint32_t crc=0;
196
197 crc = update_crc16(crc, (shift0)&0xff);
198 crc = update_crc16(crc, (shift0>>8)&0xff);
199 crc = update_crc16(crc, (shift0>>16)&0xff);
200 crc = update_crc16(crc, (shift0>>24)&0xff);
201 crc = update_crc16(crc, (shift1)&0xff);
202 crc = update_crc16(crc, (shift1>>8)&0xff);
203 crc = update_crc16(crc, (shift1>>16)&0xff);
204 crc = update_crc16(crc, (shift1>>24)&0xff);
205
206 Dbprintf("Info: Tag data: %x%08x, crc=%x",
207 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
208 if (crc != (shift2&0xffff)) {
209 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
210 } else {
211 DbpString("Info: CRC is good");
212 }
213 }
214 }
215
216 void WriteTIbyte(uint8_t b)
217 {
218 int i = 0;
219
220 // modulate 8 bits out to the antenna
221 for (i=0; i<8; i++)
222 {
223 if (b&(1<<i)) {
224 // stop modulating antenna
225 LOW(GPIO_SSC_DOUT);
226 SpinDelayUs(1000);
227 // modulate antenna
228 HIGH(GPIO_SSC_DOUT);
229 SpinDelayUs(1000);
230 } else {
231 // stop modulating antenna
232 LOW(GPIO_SSC_DOUT);
233 SpinDelayUs(300);
234 // modulate antenna
235 HIGH(GPIO_SSC_DOUT);
236 SpinDelayUs(1700);
237 }
238 }
239 }
240
241 void AcquireTiType(void)
242 {
243 int i, j, n;
244 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
245 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
246 #define TIBUFLEN 1250
247
248 // clear buffer
249 uint32_t *BigBuf = (uint32_t *)BigBuf_get_addr();
250 memset(BigBuf,0,BigBuf_max_traceLen()/sizeof(uint32_t));
251
252 // Set up the synchronous serial port
253 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
254 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
255
256 // steal this pin from the SSP and use it to control the modulation
257 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
258 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
259
260 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
261 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
262
263 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
264 // 48/2 = 24 MHz clock must be divided by 12
265 AT91C_BASE_SSC->SSC_CMR = 12;
266
267 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
268 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
269 AT91C_BASE_SSC->SSC_TCMR = 0;
270 AT91C_BASE_SSC->SSC_TFMR = 0;
271
272 LED_D_ON();
273
274 // modulate antenna
275 HIGH(GPIO_SSC_DOUT);
276
277 // Charge TI tag for 50ms.
278 SpinDelay(50);
279
280 // stop modulating antenna and listen
281 LOW(GPIO_SSC_DOUT);
282
283 LED_D_OFF();
284
285 i = 0;
286 for(;;) {
287 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
288 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
289 i++; if(i >= TIBUFLEN) break;
290 }
291 WDT_HIT();
292 }
293
294 // return stolen pin to SSP
295 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
296 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
297
298 char *dest = (char *)BigBuf_get_addr();
299 n = TIBUFLEN*32;
300 // unpack buffer
301 for (i=TIBUFLEN-1; i>=0; i--) {
302 for (j=0; j<32; j++) {
303 if(BigBuf[i] & (1 << j)) {
304 dest[--n] = 1;
305 } else {
306 dest[--n] = -1;
307 }
308 }
309 }
310 }
311
312 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
313 // if crc provided, it will be written with the data verbatim (even if bogus)
314 // if not provided a valid crc will be computed from the data and written.
315 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
316 {
317 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
318 if(crc == 0) {
319 crc = update_crc16(crc, (idlo)&0xff);
320 crc = update_crc16(crc, (idlo>>8)&0xff);
321 crc = update_crc16(crc, (idlo>>16)&0xff);
322 crc = update_crc16(crc, (idlo>>24)&0xff);
323 crc = update_crc16(crc, (idhi)&0xff);
324 crc = update_crc16(crc, (idhi>>8)&0xff);
325 crc = update_crc16(crc, (idhi>>16)&0xff);
326 crc = update_crc16(crc, (idhi>>24)&0xff);
327 }
328 Dbprintf("Writing to tag: %x%08x, crc=%x",
329 (unsigned int) idhi, (unsigned int) idlo, crc);
330
331 // TI tags charge at 134.2Khz
332 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
333 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
334 // connects to SSP_DIN and the SSP_DOUT logic level controls
335 // whether we're modulating the antenna (high)
336 // or listening to the antenna (low)
337 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
338 LED_A_ON();
339
340 // steal this pin from the SSP and use it to control the modulation
341 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
342 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
343
344 // writing algorithm:
345 // a high bit consists of a field off for 1ms and field on for 1ms
346 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
347 // initiate a charge time of 50ms (field on) then immediately start writing bits
348 // start by writing 0xBB (keyword) and 0xEB (password)
349 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
350 // finally end with 0x0300 (write frame)
351 // all data is sent lsb firts
352 // finish with 15ms programming time
353
354 // modulate antenna
355 HIGH(GPIO_SSC_DOUT);
356 SpinDelay(50); // charge time
357
358 WriteTIbyte(0xbb); // keyword
359 WriteTIbyte(0xeb); // password
360 WriteTIbyte( (idlo )&0xff );
361 WriteTIbyte( (idlo>>8 )&0xff );
362 WriteTIbyte( (idlo>>16)&0xff );
363 WriteTIbyte( (idlo>>24)&0xff );
364 WriteTIbyte( (idhi )&0xff );
365 WriteTIbyte( (idhi>>8 )&0xff );
366 WriteTIbyte( (idhi>>16)&0xff );
367 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
368 WriteTIbyte( (crc )&0xff ); // crc lo
369 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
370 WriteTIbyte(0x00); // write frame lo
371 WriteTIbyte(0x03); // write frame hi
372 HIGH(GPIO_SSC_DOUT);
373 SpinDelay(50); // programming time
374
375 LED_A_OFF();
376
377 // get TI tag data into the buffer
378 AcquireTiType();
379
380 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
381 DbpString("Now use tiread to check");
382 }
383
384 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
385 {
386 int i;
387 uint8_t *tab = BigBuf_get_addr();
388
389 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
390 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
391
392 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
393
394 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
395 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
396
397 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
398 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
399
400 i = 0;
401 for(;;) {
402 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
403 if(BUTTON_PRESS()) {
404 DbpString("Stopped");
405 return;
406 }
407 WDT_HIT();
408 }
409
410 if (ledcontrol)
411 LED_D_ON();
412
413 if(tab[i])
414 OPEN_COIL();
415 else
416 SHORT_COIL();
417
418 if (ledcontrol)
419 LED_D_OFF();
420 //wait for next sample time
421 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
422 if(BUTTON_PRESS()) {
423 DbpString("Stopped");
424 return;
425 }
426 WDT_HIT();
427 }
428
429 i++;
430 if(i == period) {
431 i = 0;
432 if (gap) {
433 SHORT_COIL();
434 SpinDelayUs(gap);
435 }
436 }
437 }
438 }
439
440 #define DEBUG_FRAME_CONTENTS 1
441 void SimulateTagLowFrequencyBidir(int divisor, int t0)
442 {
443 }
444
445 // compose fc/8 fc/10 waveform (FSK2)
446 static void fc(int c, int *n)
447 {
448 uint8_t *dest = BigBuf_get_addr();
449 int idx;
450
451 // for when we want an fc8 pattern every 4 logical bits
452 if(c==0) {
453 dest[((*n)++)]=1;
454 dest[((*n)++)]=1;
455 dest[((*n)++)]=1;
456 dest[((*n)++)]=1;
457 dest[((*n)++)]=0;
458 dest[((*n)++)]=0;
459 dest[((*n)++)]=0;
460 dest[((*n)++)]=0;
461 }
462
463 // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples
464 if(c==8) {
465 for (idx=0; idx<6; idx++) {
466 dest[((*n)++)]=1;
467 dest[((*n)++)]=1;
468 dest[((*n)++)]=1;
469 dest[((*n)++)]=1;
470 dest[((*n)++)]=0;
471 dest[((*n)++)]=0;
472 dest[((*n)++)]=0;
473 dest[((*n)++)]=0;
474 }
475 }
476
477 // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples
478 if(c==10) {
479 for (idx=0; idx<5; idx++) {
480 dest[((*n)++)]=1;
481 dest[((*n)++)]=1;
482 dest[((*n)++)]=1;
483 dest[((*n)++)]=1;
484 dest[((*n)++)]=1;
485 dest[((*n)++)]=0;
486 dest[((*n)++)]=0;
487 dest[((*n)++)]=0;
488 dest[((*n)++)]=0;
489 dest[((*n)++)]=0;
490 }
491 }
492 }
493 // compose fc/X fc/Y waveform (FSKx)
494 static void fcAll(uint8_t c, int *n, uint8_t clock)
495 {
496 uint8_t *dest = BigBuf_get_addr();
497 uint8_t idx;
498 uint8_t fcCnt;
499 // c = count of field clock for this bit
500
501 int mod = clock % c;
502 // loop through clock - step field clock
503 for (idx=0; idx < (uint8_t) clock/c; idx++){
504 // loop through field clock length - put 1/2 FC length 1's and 1/2 0's per field clock wave (to create the wave)
505 for (fcCnt=0; fcCnt < c; fcCnt++){
506 if (fcCnt < c/2){
507 dest[((*n)++)]=1;
508 } else {
509 dest[((*n)++)]=0;
510 }
511 }
512 }
513 Dbprintf("mod: %d",mod);
514 if (mod>0){ //for FC counts that don't add up to a full clock cycle padd with extra wave
515 for (idx=0; idx < mod; idx++){
516 if (idx < mod/2) {
517 dest[((*n)++)]=1;
518 } else {
519 dest[((*n)++)]=0;
520 }
521 }
522 }
523 }
524
525 // prepare a waveform pattern in the buffer based on the ID given then
526 // simulate a HID tag until the button is pressed
527 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
528 {
529 int n=0, i=0;
530 /*
531 HID tag bitstream format
532 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
533 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
534 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
535 A fc8 is inserted before every 4 bits
536 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
537 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
538 */
539
540 if (hi>0xFFF) {
541 DbpString("Tags can only have 44 bits.");
542 return;
543 }
544 fc(0,&n);
545 // special start of frame marker containing invalid bit sequences
546 fc(8, &n); fc(8, &n); // invalid
547 fc(8, &n); fc(10, &n); // logical 0
548 fc(10, &n); fc(10, &n); // invalid
549 fc(8, &n); fc(10, &n); // logical 0
550
551 WDT_HIT();
552 // manchester encode bits 43 to 32
553 for (i=11; i>=0; i--) {
554 if ((i%4)==3) fc(0,&n);
555 if ((hi>>i)&1) {
556 fc(10, &n); fc(8, &n); // low-high transition
557 } else {
558 fc(8, &n); fc(10, &n); // high-low transition
559 }
560 }
561
562 WDT_HIT();
563 // manchester encode bits 31 to 0
564 for (i=31; i>=0; i--) {
565 if ((i%4)==3) fc(0,&n);
566 if ((lo>>i)&1) {
567 fc(10, &n); fc(8, &n); // low-high transition
568 } else {
569 fc(8, &n); fc(10, &n); // high-low transition
570 }
571 }
572
573 if (ledcontrol)
574 LED_A_ON();
575 SimulateTagLowFrequency(n, 0, ledcontrol);
576
577 if (ledcontrol)
578 LED_A_OFF();
579 }
580
581 // prepare a waveform pattern in the buffer based on the ID given then
582 // simulate a FSK tag until the button is pressed
583 // arg1 contains fcHigh and fcLow, arg2 contains invert and clock
584 void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
585 {
586 int ledcontrol=1;
587 int n=0, i=0;
588 uint8_t fcHigh = arg1 >> 8;
589 uint8_t fcLow = arg1 & 0xFF;
590 //spacer bit
591 uint8_t clk = arg2 & 0xFF;
592 uint8_t invert = (arg2 >> 8) & 1;
593 //fcAll(0, &n, clk);
594
595 WDT_HIT();
596 for (i=0; i<size; i++){
597 //if ((i%4==3) fcAll(0,&n));
598 if (BitStream[i] == invert){
599 fcAll(fcLow, &n, clk);
600 } else {
601 fcAll(fcHigh, &n, clk);
602 }
603 }
604 Dbprintf("Simulating with fcHigh: %d, fcLow: %d, clk: %d, invert: %d, n: %d",fcHigh, fcLow, clk, invert, n);
605 //Dbprintf("First 64:");
606 //uint8_t *dest = BigBuf_get_addr();
607 //i=0;
608 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
609 //i+=16;
610 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
611 //i+=16;
612 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
613 //i+=16;
614 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
615
616 if (ledcontrol)
617 LED_A_ON();
618 SimulateTagLowFrequency(n, 0, ledcontrol);
619
620 if (ledcontrol)
621 LED_A_OFF();
622 }
623
624 // compose ask waveform for one bit(ASK)
625 static void askSimBit(uint8_t c, int *n, uint8_t clock, uint8_t manchester)
626 {
627 uint8_t *dest = BigBuf_get_addr();
628 uint8_t idx;
629 // c = current bit 1 or 0
630 int i = 0;
631 // for when we want a separator
632 if (c==2) { //separator
633 for (i=0; i<clock/2; i++){
634 dest[((*n)++)]=0;
635 }
636 } else {
637 if (manchester){
638 for (idx=0; idx < (uint8_t) clock/2; idx++){
639 dest[((*n)++)]=c;
640 }
641 for (idx=0; idx < (uint8_t) clock/2; idx++){
642 dest[((*n)++)]=c^1;
643 }
644 } else {
645 for (idx=0; idx < (uint8_t) clock; idx++){
646 dest[((*n)++)]=c;
647 }
648 }
649 }
650 }
651
652 // args clock, ask/man or askraw, invert, transmission separator
653 void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
654 {
655 int ledcontrol = 1;
656 int n=0, i=0;
657 uint8_t clk = (arg1 >> 8) & 0xFF;
658 uint8_t manchester = arg1 & 1;
659 uint8_t separator = arg2 & 1;
660 uint8_t invert = (arg2 >> 8) & 1;
661 WDT_HIT();
662 for (i=0; i<size; i++){
663 askSimBit(BitStream[i]^invert, &n, clk, manchester);
664 }
665 if (separator==1) Dbprintf("sorry but separator option not yet available"); //askSimBit(2, &n, clk, manchester);
666
667 Dbprintf("Simulating with clk: %d, invert: %d, manchester: %d, separator: %d, n: %d",clk, invert, manchester, separator, n);
668 //DEBUG
669 //Dbprintf("First 64:");
670 //uint8_t *dest = BigBuf_get_addr();
671 //i=0;
672 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
673 //i+=16;
674 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
675 //i+=16;
676 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
677 //i+=16;
678 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
679
680
681 if (ledcontrol)
682 LED_A_ON();
683 SimulateTagLowFrequency(n, 0, ledcontrol);
684
685 if (ledcontrol)
686 LED_A_OFF();
687 }
688
689 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
690 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
691 {
692 uint8_t *dest = BigBuf_get_addr();
693 const size_t sizeOfBigBuff = BigBuf_max_traceLen();
694 size_t size = 0;
695 uint32_t hi2=0, hi=0, lo=0;
696 int idx=0;
697 // Configure to go in 125Khz listen mode
698 LFSetupFPGAForADC(95, true);
699
700 while(!BUTTON_PRESS()) {
701
702 WDT_HIT();
703 if (ledcontrol) LED_A_ON();
704
705 DoAcquisition_default(-1,true);
706 // FSK demodulator
707 size = sizeOfBigBuff; //variable size will change after demod so re initialize it before use
708 idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
709
710 if (idx>0 && lo>0){
711 // final loop, go over previously decoded manchester data and decode into usable tag ID
712 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
713 if (hi2 != 0){ //extra large HID tags
714 Dbprintf("TAG ID: %x%08x%08x (%d)",
715 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
716 }else { //standard HID tags <38 bits
717 //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
718 uint8_t bitlen = 0;
719 uint32_t fc = 0;
720 uint32_t cardnum = 0;
721 if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
722 uint32_t lo2=0;
723 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
724 uint8_t idx3 = 1;
725 while(lo2 > 1){ //find last bit set to 1 (format len bit)
726 lo2=lo2 >> 1;
727 idx3++;
728 }
729 bitlen = idx3+19;
730 fc =0;
731 cardnum=0;
732 if(bitlen == 26){
733 cardnum = (lo>>1)&0xFFFF;
734 fc = (lo>>17)&0xFF;
735 }
736 if(bitlen == 37){
737 cardnum = (lo>>1)&0x7FFFF;
738 fc = ((hi&0xF)<<12)|(lo>>20);
739 }
740 if(bitlen == 34){
741 cardnum = (lo>>1)&0xFFFF;
742 fc= ((hi&1)<<15)|(lo>>17);
743 }
744 if(bitlen == 35){
745 cardnum = (lo>>1)&0xFFFFF;
746 fc = ((hi&1)<<11)|(lo>>21);
747 }
748 }
749 else { //if bit 38 is not set then 37 bit format is used
750 bitlen= 37;
751 fc =0;
752 cardnum=0;
753 if(bitlen==37){
754 cardnum = (lo>>1)&0x7FFFF;
755 fc = ((hi&0xF)<<12)|(lo>>20);
756 }
757 }
758 //Dbprintf("TAG ID: %x%08x (%d)",
759 // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
760 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
761 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF,
762 (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
763 }
764 if (findone){
765 if (ledcontrol) LED_A_OFF();
766 *high = hi;
767 *low = lo;
768 return;
769 }
770 // reset
771 hi2 = hi = lo = 0;
772 }
773 WDT_HIT();
774 }
775 DbpString("Stopped");
776 if (ledcontrol) LED_A_OFF();
777 }
778
779 void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
780 {
781 uint8_t *dest = BigBuf_get_addr();
782
783 size_t size=0, idx=0;
784 int clk=0, invert=0, errCnt=0, maxErr=20;
785 uint64_t lo=0;
786 // Configure to go in 125Khz listen mode
787 LFSetupFPGAForADC(95, true);
788
789 while(!BUTTON_PRESS()) {
790
791 WDT_HIT();
792 if (ledcontrol) LED_A_ON();
793
794 DoAcquisition_default(-1,true);
795 size = BigBuf_max_traceLen();
796 //Dbprintf("DEBUG: Buffer got");
797 //askdemod and manchester decode
798 errCnt = askmandemod(dest, &size, &clk, &invert, maxErr);
799 //Dbprintf("DEBUG: ASK Got");
800 WDT_HIT();
801
802 if (errCnt>=0){
803 lo = Em410xDecode(dest, &size, &idx);
804 //Dbprintf("DEBUG: EM GOT");
805 if (lo>0){
806 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
807 (uint32_t)(lo>>32),
808 (uint32_t)lo,
809 (uint32_t)(lo&0xFFFF),
810 (uint32_t)((lo>>16LL) & 0xFF),
811 (uint32_t)(lo & 0xFFFFFF));
812 }
813 if (findone){
814 if (ledcontrol) LED_A_OFF();
815 *high=lo>>32;
816 *low=lo & 0xFFFFFFFF;
817 return;
818 }
819 } else{
820 //Dbprintf("DEBUG: No Tag");
821 }
822 WDT_HIT();
823 lo = 0;
824 clk=0;
825 invert=0;
826 errCnt=0;
827 size=0;
828 }
829 DbpString("Stopped");
830 if (ledcontrol) LED_A_OFF();
831 }
832
833 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
834 {
835 uint8_t *dest = BigBuf_get_addr();
836 int idx=0;
837 uint32_t code=0, code2=0;
838 uint8_t version=0;
839 uint8_t facilitycode=0;
840 uint16_t number=0;
841 // Configure to go in 125Khz listen mode
842 LFSetupFPGAForADC(95, true);
843
844 while(!BUTTON_PRESS()) {
845 WDT_HIT();
846 if (ledcontrol) LED_A_ON();
847 DoAcquisition_default(-1,true);
848 //fskdemod and get start index
849 WDT_HIT();
850 idx = IOdemodFSK(dest, BigBuf_max_traceLen());
851 if (idx>0){
852 //valid tag found
853
854 //Index map
855 //0 10 20 30 40 50 60
856 //| | | | | | |
857 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
858 //-----------------------------------------------------------------------------
859 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 ???????? 11
860 //
861 //XSF(version)facility:codeone+codetwo
862 //Handle the data
863 if(findone){ //only print binary if we are doing one
864 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
865 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
866 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
867 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
868 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
869 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
870 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
871 }
872 code = bytebits_to_byte(dest+idx,32);
873 code2 = bytebits_to_byte(dest+idx+32,32);
874 version = bytebits_to_byte(dest+idx+27,8); //14,4
875 facilitycode = bytebits_to_byte(dest+idx+18,8) ;
876 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
877
878 Dbprintf("XSF(%02d)%02x:%05d (%08x%08x)",version,facilitycode,number,code,code2);
879 // if we're only looking for one tag
880 if (findone){
881 if (ledcontrol) LED_A_OFF();
882 //LED_A_OFF();
883 *high=code;
884 *low=code2;
885 return;
886 }
887 code=code2=0;
888 version=facilitycode=0;
889 number=0;
890 idx=0;
891 }
892 WDT_HIT();
893 }
894 DbpString("Stopped");
895 if (ledcontrol) LED_A_OFF();
896 }
897
898 /*------------------------------
899 * T5555/T5557/T5567 routines
900 *------------------------------
901 */
902
903 /* T55x7 configuration register definitions */
904 #define T55x7_POR_DELAY 0x00000001
905 #define T55x7_ST_TERMINATOR 0x00000008
906 #define T55x7_PWD 0x00000010
907 #define T55x7_MAXBLOCK_SHIFT 5
908 #define T55x7_AOR 0x00000200
909 #define T55x7_PSKCF_RF_2 0
910 #define T55x7_PSKCF_RF_4 0x00000400
911 #define T55x7_PSKCF_RF_8 0x00000800
912 #define T55x7_MODULATION_DIRECT 0
913 #define T55x7_MODULATION_PSK1 0x00001000
914 #define T55x7_MODULATION_PSK2 0x00002000
915 #define T55x7_MODULATION_PSK3 0x00003000
916 #define T55x7_MODULATION_FSK1 0x00004000
917 #define T55x7_MODULATION_FSK2 0x00005000
918 #define T55x7_MODULATION_FSK1a 0x00006000
919 #define T55x7_MODULATION_FSK2a 0x00007000
920 #define T55x7_MODULATION_MANCHESTER 0x00008000
921 #define T55x7_MODULATION_BIPHASE 0x00010000
922 #define T55x7_BITRATE_RF_8 0
923 #define T55x7_BITRATE_RF_16 0x00040000
924 #define T55x7_BITRATE_RF_32 0x00080000
925 #define T55x7_BITRATE_RF_40 0x000C0000
926 #define T55x7_BITRATE_RF_50 0x00100000
927 #define T55x7_BITRATE_RF_64 0x00140000
928 #define T55x7_BITRATE_RF_100 0x00180000
929 #define T55x7_BITRATE_RF_128 0x001C0000
930
931 /* T5555 (Q5) configuration register definitions */
932 #define T5555_ST_TERMINATOR 0x00000001
933 #define T5555_MAXBLOCK_SHIFT 0x00000001
934 #define T5555_MODULATION_MANCHESTER 0
935 #define T5555_MODULATION_PSK1 0x00000010
936 #define T5555_MODULATION_PSK2 0x00000020
937 #define T5555_MODULATION_PSK3 0x00000030
938 #define T5555_MODULATION_FSK1 0x00000040
939 #define T5555_MODULATION_FSK2 0x00000050
940 #define T5555_MODULATION_BIPHASE 0x00000060
941 #define T5555_MODULATION_DIRECT 0x00000070
942 #define T5555_INVERT_OUTPUT 0x00000080
943 #define T5555_PSK_RF_2 0
944 #define T5555_PSK_RF_4 0x00000100
945 #define T5555_PSK_RF_8 0x00000200
946 #define T5555_USE_PWD 0x00000400
947 #define T5555_USE_AOR 0x00000800
948 #define T5555_BITRATE_SHIFT 12
949 #define T5555_FAST_WRITE 0x00004000
950 #define T5555_PAGE_SELECT 0x00008000
951
952 /*
953 * Relevant times in microsecond
954 * To compensate antenna falling times shorten the write times
955 * and enlarge the gap ones.
956 */
957 #define START_GAP 250
958 #define WRITE_GAP 160
959 #define WRITE_0 144 // 192
960 #define WRITE_1 400 // 432 for T55x7; 448 for E5550
961
962 // Write one bit to card
963 void T55xxWriteBit(int bit)
964 {
965 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
966 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
967 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
968 if (bit == 0)
969 SpinDelayUs(WRITE_0);
970 else
971 SpinDelayUs(WRITE_1);
972 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
973 SpinDelayUs(WRITE_GAP);
974 }
975
976 // Write one card block in page 0, no lock
977 void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
978 {
979 //unsigned int i; //enio adjustment 12/10/14
980 uint32_t i;
981
982 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
983 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
984 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
985
986 // Give it a bit of time for the resonant antenna to settle.
987 // And for the tag to fully power up
988 SpinDelay(150);
989
990 // Now start writting
991 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
992 SpinDelayUs(START_GAP);
993
994 // Opcode
995 T55xxWriteBit(1);
996 T55xxWriteBit(0); //Page 0
997 if (PwdMode == 1){
998 // Pwd
999 for (i = 0x80000000; i != 0; i >>= 1)
1000 T55xxWriteBit(Pwd & i);
1001 }
1002 // Lock bit
1003 T55xxWriteBit(0);
1004
1005 // Data
1006 for (i = 0x80000000; i != 0; i >>= 1)
1007 T55xxWriteBit(Data & i);
1008
1009 // Block
1010 for (i = 0x04; i != 0; i >>= 1)
1011 T55xxWriteBit(Block & i);
1012
1013 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
1014 // so wait a little more)
1015 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1016 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1017 SpinDelay(20);
1018 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1019 }
1020
1021 // Read one card block in page 0
1022 void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1023 {
1024 uint8_t *dest = BigBuf_get_addr();
1025 //int m=0, i=0; //enio adjustment 12/10/14
1026 uint32_t m=0, i=0;
1027 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1028 m = BigBuf_max_traceLen();
1029 // Clear destination buffer before sending the command
1030 memset(dest, 128, m);
1031 // Connect the A/D to the peak-detected low-frequency path.
1032 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1033 // Now set up the SSC to get the ADC samples that are now streaming at us.
1034 FpgaSetupSsc();
1035
1036 LED_D_ON();
1037 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1038 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1039
1040 // Give it a bit of time for the resonant antenna to settle.
1041 // And for the tag to fully power up
1042 SpinDelay(150);
1043
1044 // Now start writting
1045 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1046 SpinDelayUs(START_GAP);
1047
1048 // Opcode
1049 T55xxWriteBit(1);
1050 T55xxWriteBit(0); //Page 0
1051 if (PwdMode == 1){
1052 // Pwd
1053 for (i = 0x80000000; i != 0; i >>= 1)
1054 T55xxWriteBit(Pwd & i);
1055 }
1056 // Lock bit
1057 T55xxWriteBit(0);
1058 // Block
1059 for (i = 0x04; i != 0; i >>= 1)
1060 T55xxWriteBit(Block & i);
1061
1062 // Turn field on to read the response
1063 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1064 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1065
1066 // Now do the acquisition
1067 i = 0;
1068 for(;;) {
1069 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1070 AT91C_BASE_SSC->SSC_THR = 0x43;
1071 }
1072 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1073 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1074 // we don't care about actual value, only if it's more or less than a
1075 // threshold essentially we capture zero crossings for later analysis
1076 // if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
1077 i++;
1078 if (i >= m) break;
1079 }
1080 }
1081
1082 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1083 LED_D_OFF();
1084 DbpString("DONE!");
1085 }
1086
1087 // Read card traceability data (page 1)
1088 void T55xxReadTrace(void){
1089 uint8_t *dest = BigBuf_get_addr();
1090 int m=0, i=0;
1091
1092 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1093 m = BigBuf_max_traceLen();
1094 // Clear destination buffer before sending the command
1095 memset(dest, 128, m);
1096 // Connect the A/D to the peak-detected low-frequency path.
1097 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1098 // Now set up the SSC to get the ADC samples that are now streaming at us.
1099 FpgaSetupSsc();
1100
1101 LED_D_ON();
1102 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1103 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1104
1105 // Give it a bit of time for the resonant antenna to settle.
1106 // And for the tag to fully power up
1107 SpinDelay(150);
1108
1109 // Now start writting
1110 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1111 SpinDelayUs(START_GAP);
1112
1113 // Opcode
1114 T55xxWriteBit(1);
1115 T55xxWriteBit(1); //Page 1
1116
1117 // Turn field on to read the response
1118 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1119 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1120
1121 // Now do the acquisition
1122 i = 0;
1123 for(;;) {
1124 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1125 AT91C_BASE_SSC->SSC_THR = 0x43;
1126 }
1127 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1128 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1129 i++;
1130 if (i >= m) break;
1131 }
1132 }
1133
1134 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1135 LED_D_OFF();
1136 DbpString("DONE!");
1137 }
1138
1139 /*-------------- Cloning routines -----------*/
1140 // Copy HID id to card and setup block 0 config
1141 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1142 {
1143 int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1144 int last_block = 0;
1145
1146 if (longFMT){
1147 // Ensure no more than 84 bits supplied
1148 if (hi2>0xFFFFF) {
1149 DbpString("Tags can only have 84 bits.");
1150 return;
1151 }
1152 // Build the 6 data blocks for supplied 84bit ID
1153 last_block = 6;
1154 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1155 for (int i=0;i<4;i++) {
1156 if (hi2 & (1<<(19-i)))
1157 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1158 else
1159 data1 |= (1<<((3-i)*2)); // 0 -> 01
1160 }
1161
1162 data2 = 0;
1163 for (int i=0;i<16;i++) {
1164 if (hi2 & (1<<(15-i)))
1165 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1166 else
1167 data2 |= (1<<((15-i)*2)); // 0 -> 01
1168 }
1169
1170 data3 = 0;
1171 for (int i=0;i<16;i++) {
1172 if (hi & (1<<(31-i)))
1173 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1174 else
1175 data3 |= (1<<((15-i)*2)); // 0 -> 01
1176 }
1177
1178 data4 = 0;
1179 for (int i=0;i<16;i++) {
1180 if (hi & (1<<(15-i)))
1181 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1182 else
1183 data4 |= (1<<((15-i)*2)); // 0 -> 01
1184 }
1185
1186 data5 = 0;
1187 for (int i=0;i<16;i++) {
1188 if (lo & (1<<(31-i)))
1189 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1190 else
1191 data5 |= (1<<((15-i)*2)); // 0 -> 01
1192 }
1193
1194 data6 = 0;
1195 for (int i=0;i<16;i++) {
1196 if (lo & (1<<(15-i)))
1197 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1198 else
1199 data6 |= (1<<((15-i)*2)); // 0 -> 01
1200 }
1201 }
1202 else {
1203 // Ensure no more than 44 bits supplied
1204 if (hi>0xFFF) {
1205 DbpString("Tags can only have 44 bits.");
1206 return;
1207 }
1208
1209 // Build the 3 data blocks for supplied 44bit ID
1210 last_block = 3;
1211
1212 data1 = 0x1D000000; // load preamble
1213
1214 for (int i=0;i<12;i++) {
1215 if (hi & (1<<(11-i)))
1216 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1217 else
1218 data1 |= (1<<((11-i)*2)); // 0 -> 01
1219 }
1220
1221 data2 = 0;
1222 for (int i=0;i<16;i++) {
1223 if (lo & (1<<(31-i)))
1224 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1225 else
1226 data2 |= (1<<((15-i)*2)); // 0 -> 01
1227 }
1228
1229 data3 = 0;
1230 for (int i=0;i<16;i++) {
1231 if (lo & (1<<(15-i)))
1232 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1233 else
1234 data3 |= (1<<((15-i)*2)); // 0 -> 01
1235 }
1236 }
1237
1238 LED_D_ON();
1239 // Program the data blocks for supplied ID
1240 // and the block 0 for HID format
1241 T55xxWriteBlock(data1,1,0,0);
1242 T55xxWriteBlock(data2,2,0,0);
1243 T55xxWriteBlock(data3,3,0,0);
1244
1245 if (longFMT) { // if long format there are 6 blocks
1246 T55xxWriteBlock(data4,4,0,0);
1247 T55xxWriteBlock(data5,5,0,0);
1248 T55xxWriteBlock(data6,6,0,0);
1249 }
1250
1251 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1252 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1253 T55x7_MODULATION_FSK2a |
1254 last_block << T55x7_MAXBLOCK_SHIFT,
1255 0,0,0);
1256
1257 LED_D_OFF();
1258
1259 DbpString("DONE!");
1260 }
1261
1262 void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1263 {
1264 int data1=0, data2=0; //up to six blocks for long format
1265
1266 data1 = hi; // load preamble
1267 data2 = lo;
1268
1269 LED_D_ON();
1270 // Program the data blocks for supplied ID
1271 // and the block 0 for HID format
1272 T55xxWriteBlock(data1,1,0,0);
1273 T55xxWriteBlock(data2,2,0,0);
1274
1275 //Config Block
1276 T55xxWriteBlock(0x00147040,0,0,0);
1277 LED_D_OFF();
1278
1279 DbpString("DONE!");
1280 }
1281
1282 // Define 9bit header for EM410x tags
1283 #define EM410X_HEADER 0x1FF
1284 #define EM410X_ID_LENGTH 40
1285
1286 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1287 {
1288 int i, id_bit;
1289 uint64_t id = EM410X_HEADER;
1290 uint64_t rev_id = 0; // reversed ID
1291 int c_parity[4]; // column parity
1292 int r_parity = 0; // row parity
1293 uint32_t clock = 0;
1294
1295 // Reverse ID bits given as parameter (for simpler operations)
1296 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1297 if (i < 32) {
1298 rev_id = (rev_id << 1) | (id_lo & 1);
1299 id_lo >>= 1;
1300 } else {
1301 rev_id = (rev_id << 1) | (id_hi & 1);
1302 id_hi >>= 1;
1303 }
1304 }
1305
1306 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1307 id_bit = rev_id & 1;
1308
1309 if (i % 4 == 0) {
1310 // Don't write row parity bit at start of parsing
1311 if (i)
1312 id = (id << 1) | r_parity;
1313 // Start counting parity for new row
1314 r_parity = id_bit;
1315 } else {
1316 // Count row parity
1317 r_parity ^= id_bit;
1318 }
1319
1320 // First elements in column?
1321 if (i < 4)
1322 // Fill out first elements
1323 c_parity[i] = id_bit;
1324 else
1325 // Count column parity
1326 c_parity[i % 4] ^= id_bit;
1327
1328 // Insert ID bit
1329 id = (id << 1) | id_bit;
1330 rev_id >>= 1;
1331 }
1332
1333 // Insert parity bit of last row
1334 id = (id << 1) | r_parity;
1335
1336 // Fill out column parity at the end of tag
1337 for (i = 0; i < 4; ++i)
1338 id = (id << 1) | c_parity[i];
1339
1340 // Add stop bit
1341 id <<= 1;
1342
1343 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1344 LED_D_ON();
1345
1346 // Write EM410x ID
1347 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1348 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1349
1350 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1351 if (card) {
1352 // Clock rate is stored in bits 8-15 of the card value
1353 clock = (card & 0xFF00) >> 8;
1354 Dbprintf("Clock rate: %d", clock);
1355 switch (clock)
1356 {
1357 case 32:
1358 clock = T55x7_BITRATE_RF_32;
1359 break;
1360 case 16:
1361 clock = T55x7_BITRATE_RF_16;
1362 break;
1363 case 0:
1364 // A value of 0 is assumed to be 64 for backwards-compatibility
1365 // Fall through...
1366 case 64:
1367 clock = T55x7_BITRATE_RF_64;
1368 break;
1369 default:
1370 Dbprintf("Invalid clock rate: %d", clock);
1371 return;
1372 }
1373
1374 // Writing configuration for T55x7 tag
1375 T55xxWriteBlock(clock |
1376 T55x7_MODULATION_MANCHESTER |
1377 2 << T55x7_MAXBLOCK_SHIFT,
1378 0, 0, 0);
1379 }
1380 else
1381 // Writing configuration for T5555(Q5) tag
1382 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1383 T5555_MODULATION_MANCHESTER |
1384 2 << T5555_MAXBLOCK_SHIFT,
1385 0, 0, 0);
1386
1387 LED_D_OFF();
1388 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1389 (uint32_t)(id >> 32), (uint32_t)id);
1390 }
1391
1392 // Clone Indala 64-bit tag by UID to T55x7
1393 void CopyIndala64toT55x7(int hi, int lo)
1394 {
1395
1396 //Program the 2 data blocks for supplied 64bit UID
1397 // and the block 0 for Indala64 format
1398 T55xxWriteBlock(hi,1,0,0);
1399 T55xxWriteBlock(lo,2,0,0);
1400 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1401 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1402 T55x7_MODULATION_PSK1 |
1403 2 << T55x7_MAXBLOCK_SHIFT,
1404 0, 0, 0);
1405 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1406 // T5567WriteBlock(0x603E1042,0);
1407
1408 DbpString("DONE!");
1409
1410 }
1411
1412 void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1413 {
1414
1415 //Program the 7 data blocks for supplied 224bit UID
1416 // and the block 0 for Indala224 format
1417 T55xxWriteBlock(uid1,1,0,0);
1418 T55xxWriteBlock(uid2,2,0,0);
1419 T55xxWriteBlock(uid3,3,0,0);
1420 T55xxWriteBlock(uid4,4,0,0);
1421 T55xxWriteBlock(uid5,5,0,0);
1422 T55xxWriteBlock(uid6,6,0,0);
1423 T55xxWriteBlock(uid7,7,0,0);
1424 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1425 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1426 T55x7_MODULATION_PSK1 |
1427 7 << T55x7_MAXBLOCK_SHIFT,
1428 0,0,0);
1429 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1430 // T5567WriteBlock(0x603E10E2,0);
1431
1432 DbpString("DONE!");
1433
1434 }
1435
1436
1437 #define abs(x) ( ((x)<0) ? -(x) : (x) )
1438 #define max(x,y) ( x<y ? y:x)
1439
1440 int DemodPCF7931(uint8_t **outBlocks) {
1441 uint8_t BitStream[256];
1442 uint8_t Blocks[8][16];
1443 uint8_t *GraphBuffer = BigBuf_get_addr();
1444 int GraphTraceLen = BigBuf_max_traceLen();
1445 int i, j, lastval, bitidx, half_switch;
1446 int clock = 64;
1447 int tolerance = clock / 8;
1448 int pmc, block_done;
1449 int lc, warnings = 0;
1450 int num_blocks = 0;
1451 int lmin=128, lmax=128;
1452 uint8_t dir;
1453
1454 LFSetupFPGAForADC(95, true);
1455 DoAcquisition_default(0, 0);
1456
1457
1458 lmin = 64;
1459 lmax = 192;
1460
1461 i = 2;
1462
1463 /* Find first local max/min */
1464 if(GraphBuffer[1] > GraphBuffer[0]) {
1465 while(i < GraphTraceLen) {
1466 if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax)
1467 break;
1468 i++;
1469 }
1470 dir = 0;
1471 }
1472 else {
1473 while(i < GraphTraceLen) {
1474 if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin)
1475 break;
1476 i++;
1477 }
1478 dir = 1;
1479 }
1480
1481 lastval = i++;
1482 half_switch = 0;
1483 pmc = 0;
1484 block_done = 0;
1485
1486 for (bitidx = 0; i < GraphTraceLen; i++)
1487 {
1488 if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin))
1489 {
1490 lc = i - lastval;
1491 lastval = i;
1492
1493 // Switch depending on lc length:
1494 // Tolerance is 1/8 of clock rate (arbitrary)
1495 if (abs(lc-clock/4) < tolerance) {
1496 // 16T0
1497 if((i - pmc) == lc) { /* 16T0 was previous one */
1498 /* It's a PMC ! */
1499 i += (128+127+16+32+33+16)-1;
1500 lastval = i;
1501 pmc = 0;
1502 block_done = 1;
1503 }
1504 else {
1505 pmc = i;
1506 }
1507 } else if (abs(lc-clock/2) < tolerance) {
1508 // 32TO
1509 if((i - pmc) == lc) { /* 16T0 was previous one */
1510 /* It's a PMC ! */
1511 i += (128+127+16+32+33)-1;
1512 lastval = i;
1513 pmc = 0;
1514 block_done = 1;
1515 }
1516 else if(half_switch == 1) {
1517 BitStream[bitidx++] = 0;
1518 half_switch = 0;
1519 }
1520 else
1521 half_switch++;
1522 } else if (abs(lc-clock) < tolerance) {
1523 // 64TO
1524 BitStream[bitidx++] = 1;
1525 } else {
1526 // Error
1527 warnings++;
1528 if (warnings > 10)
1529 {
1530 Dbprintf("Error: too many detection errors, aborting.");
1531 return 0;
1532 }
1533 }
1534
1535 if(block_done == 1) {
1536 if(bitidx == 128) {
1537 for(j=0; j<16; j++) {
1538 Blocks[num_blocks][j] = 128*BitStream[j*8+7]+
1539 64*BitStream[j*8+6]+
1540 32*BitStream[j*8+5]+
1541 16*BitStream[j*8+4]+
1542 8*BitStream[j*8+3]+
1543 4*BitStream[j*8+2]+
1544 2*BitStream[j*8+1]+
1545 BitStream[j*8];
1546 }
1547 num_blocks++;
1548 }
1549 bitidx = 0;
1550 block_done = 0;
1551 half_switch = 0;
1552 }
1553 if(i < GraphTraceLen)
1554 {
1555 if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;
1556 else dir = 1;
1557 }
1558 }
1559 if(bitidx==255)
1560 bitidx=0;
1561 warnings = 0;
1562 if(num_blocks == 4) break;
1563 }
1564 memcpy(outBlocks, Blocks, 16*num_blocks);
1565 return num_blocks;
1566 }
1567
1568 int IsBlock0PCF7931(uint8_t *Block) {
1569 // Assume RFU means 0 :)
1570 if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1571 return 1;
1572 if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1573 return 1;
1574 return 0;
1575 }
1576
1577 int IsBlock1PCF7931(uint8_t *Block) {
1578 // Assume RFU means 0 :)
1579 if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1580 if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1581 return 1;
1582
1583 return 0;
1584 }
1585
1586 #define ALLOC 16
1587
1588 void ReadPCF7931() {
1589 uint8_t Blocks[8][17];
1590 uint8_t tmpBlocks[4][16];
1591 int i, j, ind, ind2, n;
1592 int num_blocks = 0;
1593 int max_blocks = 8;
1594 int ident = 0;
1595 int error = 0;
1596 int tries = 0;
1597
1598 memset(Blocks, 0, 8*17*sizeof(uint8_t));
1599
1600 do {
1601 memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1602 n = DemodPCF7931((uint8_t**)tmpBlocks);
1603 if(!n)
1604 error++;
1605 if(error==10 && num_blocks == 0) {
1606 Dbprintf("Error, no tag or bad tag");
1607 return;
1608 }
1609 else if (tries==20 || error==10) {
1610 Dbprintf("Error reading the tag");
1611 Dbprintf("Here is the partial content");
1612 goto end;
1613 }
1614
1615 for(i=0; i<n; i++)
1616 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1617 tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1618 tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1619 if(!ident) {
1620 for(i=0; i<n; i++) {
1621 if(IsBlock0PCF7931(tmpBlocks[i])) {
1622 // Found block 0 ?
1623 if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1624 // Found block 1!
1625 // \o/
1626 ident = 1;
1627 memcpy(Blocks[0], tmpBlocks[i], 16);
1628 Blocks[0][ALLOC] = 1;
1629 memcpy(Blocks[1], tmpBlocks[i+1], 16);
1630 Blocks[1][ALLOC] = 1;
1631 max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1632 // Debug print
1633 Dbprintf("(dbg) Max blocks: %d", max_blocks);
1634 num_blocks = 2;
1635 // Handle following blocks
1636 for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1637 if(j==n) j=0;
1638 if(j==i) break;
1639 memcpy(Blocks[ind2], tmpBlocks[j], 16);
1640 Blocks[ind2][ALLOC] = 1;
1641 }
1642 break;
1643 }
1644 }
1645 }
1646 }
1647 else {
1648 for(i=0; i<n; i++) { // Look for identical block in known blocks
1649 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1650 for(j=0; j<max_blocks; j++) {
1651 if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1652 // Found an identical block
1653 for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1654 if(ind2 < 0)
1655 ind2 = max_blocks;
1656 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1657 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1658 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1659 Blocks[ind2][ALLOC] = 1;
1660 num_blocks++;
1661 if(num_blocks == max_blocks) goto end;
1662 }
1663 }
1664 for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1665 if(ind2 > max_blocks)
1666 ind2 = 0;
1667 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1668 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1669 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1670 Blocks[ind2][ALLOC] = 1;
1671 num_blocks++;
1672 if(num_blocks == max_blocks) goto end;
1673 }
1674 }
1675 }
1676 }
1677 }
1678 }
1679 }
1680 tries++;
1681 if (BUTTON_PRESS()) return;
1682 } while (num_blocks != max_blocks);
1683 end:
1684 Dbprintf("-----------------------------------------");
1685 Dbprintf("Memory content:");
1686 Dbprintf("-----------------------------------------");
1687 for(i=0; i<max_blocks; i++) {
1688 if(Blocks[i][ALLOC]==1)
1689 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1690 Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1691 Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1692 else
1693 Dbprintf("<missing block %d>", i);
1694 }
1695 Dbprintf("-----------------------------------------");
1696
1697 return ;
1698 }
1699
1700
1701 //-----------------------------------
1702 // EM4469 / EM4305 routines
1703 //-----------------------------------
1704 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1705 #define FWD_CMD_WRITE 0xA
1706 #define FWD_CMD_READ 0x9
1707 #define FWD_CMD_DISABLE 0x5
1708
1709
1710 uint8_t forwardLink_data[64]; //array of forwarded bits
1711 uint8_t * forward_ptr; //ptr for forward message preparation
1712 uint8_t fwd_bit_sz; //forwardlink bit counter
1713 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1714
1715 //====================================================================
1716 // prepares command bits
1717 // see EM4469 spec
1718 //====================================================================
1719 //--------------------------------------------------------------------
1720 uint8_t Prepare_Cmd( uint8_t cmd ) {
1721 //--------------------------------------------------------------------
1722
1723 *forward_ptr++ = 0; //start bit
1724 *forward_ptr++ = 0; //second pause for 4050 code
1725
1726 *forward_ptr++ = cmd;
1727 cmd >>= 1;
1728 *forward_ptr++ = cmd;
1729 cmd >>= 1;
1730 *forward_ptr++ = cmd;
1731 cmd >>= 1;
1732 *forward_ptr++ = cmd;
1733
1734 return 6; //return number of emited bits
1735 }
1736
1737 //====================================================================
1738 // prepares address bits
1739 // see EM4469 spec
1740 //====================================================================
1741
1742 //--------------------------------------------------------------------
1743 uint8_t Prepare_Addr( uint8_t addr ) {
1744 //--------------------------------------------------------------------
1745
1746 register uint8_t line_parity;
1747
1748 uint8_t i;
1749 line_parity = 0;
1750 for(i=0;i<6;i++) {
1751 *forward_ptr++ = addr;
1752 line_parity ^= addr;
1753 addr >>= 1;
1754 }
1755
1756 *forward_ptr++ = (line_parity & 1);
1757
1758 return 7; //return number of emited bits
1759 }
1760
1761 //====================================================================
1762 // prepares data bits intreleaved with parity bits
1763 // see EM4469 spec
1764 //====================================================================
1765
1766 //--------------------------------------------------------------------
1767 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1768 //--------------------------------------------------------------------
1769
1770 register uint8_t line_parity;
1771 register uint8_t column_parity;
1772 register uint8_t i, j;
1773 register uint16_t data;
1774
1775 data = data_low;
1776 column_parity = 0;
1777
1778 for(i=0; i<4; i++) {
1779 line_parity = 0;
1780 for(j=0; j<8; j++) {
1781 line_parity ^= data;
1782 column_parity ^= (data & 1) << j;
1783 *forward_ptr++ = data;
1784 data >>= 1;
1785 }
1786 *forward_ptr++ = line_parity;
1787 if(i == 1)
1788 data = data_hi;
1789 }
1790
1791 for(j=0; j<8; j++) {
1792 *forward_ptr++ = column_parity;
1793 column_parity >>= 1;
1794 }
1795 *forward_ptr = 0;
1796
1797 return 45; //return number of emited bits
1798 }
1799
1800 //====================================================================
1801 // Forward Link send function
1802 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1803 // fwd_bit_count set with number of bits to be sent
1804 //====================================================================
1805 void SendForward(uint8_t fwd_bit_count) {
1806
1807 fwd_write_ptr = forwardLink_data;
1808 fwd_bit_sz = fwd_bit_count;
1809
1810 LED_D_ON();
1811
1812 //Field on
1813 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1814 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1815 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1816
1817 // Give it a bit of time for the resonant antenna to settle.
1818 // And for the tag to fully power up
1819 SpinDelay(150);
1820
1821 // force 1st mod pulse (start gap must be longer for 4305)
1822 fwd_bit_sz--; //prepare next bit modulation
1823 fwd_write_ptr++;
1824 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1825 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1826 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1827 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1828 SpinDelayUs(16*8); //16 cycles on (8us each)
1829
1830 // now start writting
1831 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1832 if(((*fwd_write_ptr++) & 1) == 1)
1833 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1834 else {
1835 //These timings work for 4469/4269/4305 (with the 55*8 above)
1836 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1837 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1838 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1839 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1840 SpinDelayUs(9*8); //16 cycles on (8us each)
1841 }
1842 }
1843 }
1844
1845 void EM4xLogin(uint32_t Password) {
1846
1847 uint8_t fwd_bit_count;
1848
1849 forward_ptr = forwardLink_data;
1850 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1851 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1852
1853 SendForward(fwd_bit_count);
1854
1855 //Wait for command to complete
1856 SpinDelay(20);
1857
1858 }
1859
1860 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1861
1862 uint8_t fwd_bit_count;
1863 uint8_t *dest = BigBuf_get_addr();
1864 int m=0, i=0;
1865
1866 //If password mode do login
1867 if (PwdMode == 1) EM4xLogin(Pwd);
1868
1869 forward_ptr = forwardLink_data;
1870 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1871 fwd_bit_count += Prepare_Addr( Address );
1872
1873 m = BigBuf_max_traceLen();
1874 // Clear destination buffer before sending the command
1875 memset(dest, 128, m);
1876 // Connect the A/D to the peak-detected low-frequency path.
1877 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1878 // Now set up the SSC to get the ADC samples that are now streaming at us.
1879 FpgaSetupSsc();
1880
1881 SendForward(fwd_bit_count);
1882
1883 // Now do the acquisition
1884 i = 0;
1885 for(;;) {
1886 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1887 AT91C_BASE_SSC->SSC_THR = 0x43;
1888 }
1889 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1890 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1891 i++;
1892 if (i >= m) break;
1893 }
1894 }
1895 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1896 LED_D_OFF();
1897 }
1898
1899 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1900
1901 uint8_t fwd_bit_count;
1902
1903 //If password mode do login
1904 if (PwdMode == 1) EM4xLogin(Pwd);
1905
1906 forward_ptr = forwardLink_data;
1907 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1908 fwd_bit_count += Prepare_Addr( Address );
1909 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1910
1911 SendForward(fwd_bit_count);
1912
1913 //Wait for write to complete
1914 SpinDelay(20);
1915 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1916 LED_D_OFF();
1917 }
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