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1 //-----------------------------------------------------------------------------
2 // Miscellaneous routines for low frequency tag operations.
3 // Tags supported here so far are Texas Instruments (TI), HID
4 // Also routines for raw mode reading/simulating of LF waveform
5 //
6 //-----------------------------------------------------------------------------
7 #include <proxmark3.h>
8 #include "apps.h"
9 #include "hitag2.h"
10 #include "../common/crc16.c"
11
12 int sprintf(char *dest, const char *fmt, ...);
13
14 void AcquireRawAdcSamples125k(BOOL at134khz)
15 {
16 if (at134khz)
17 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
18 else
19 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
20
21 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
22
23 // Connect the A/D to the peak-detected low-frequency path.
24 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
25
26 // Give it a bit of time for the resonant antenna to settle.
27 SpinDelay(50);
28
29 // Now set up the SSC to get the ADC samples that are now streaming at us.
30 FpgaSetupSsc();
31
32 // Now call the acquisition routine
33 DoAcquisition125k();
34 }
35
36 // split into two routines so we can avoid timing issues after sending commands //
37 void DoAcquisition125k(void)
38 {
39 BYTE *dest = (BYTE *)BigBuf;
40 int n = sizeof(BigBuf);
41 int i;
42
43 memset(dest, 0, n);
44 i = 0;
45 for(;;) {
46 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
47 AT91C_BASE_SSC->SSC_THR = 0x43;
48 LED_D_ON();
49 }
50 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
51 dest[i] = (BYTE)AT91C_BASE_SSC->SSC_RHR;
52 i++;
53 LED_D_OFF();
54 if (i >= n) break;
55 }
56 }
57 Dbprintf("read samples, dest[0]=%x dest[1]=%x", dest[0], dest[1]);
58 }
59
60 void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, BYTE *command)
61 {
62 BOOL at134khz;
63
64 /* Make sure the tag is reset */
65 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
66 SpinDelay(2500);
67
68 // see if 'h' was specified
69 if (command[strlen((char *) command) - 1] == 'h')
70 at134khz = TRUE;
71 else
72 at134khz = FALSE;
73
74 if (at134khz)
75 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
76 else
77 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
78
79 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
80
81 // Give it a bit of time for the resonant antenna to settle.
82 SpinDelay(50);
83 // And a little more time for the tag to fully power up
84 SpinDelay(2000);
85
86 // Now set up the SSC to get the ADC samples that are now streaming at us.
87 FpgaSetupSsc();
88
89 // now modulate the reader field
90 while(*command != '\0' && *command != ' ') {
91 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
92 LED_D_OFF();
93 SpinDelayUs(delay_off);
94 if (at134khz)
95 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
96 else
97 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
98
99 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
100 LED_D_ON();
101 if(*(command++) == '0')
102 SpinDelayUs(period_0);
103 else
104 SpinDelayUs(period_1);
105 }
106 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
107 LED_D_OFF();
108 SpinDelayUs(delay_off);
109 if (at134khz)
110 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
111 else
112 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
113
114 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
115
116 // now do the read
117 DoAcquisition125k();
118 }
119
120 /* blank r/w tag data stream
121 ...0000000000000000 01111111
122 1010101010101010101010101010101010101010101010101010101010101010
123 0011010010100001
124 01111111
125 101010101010101[0]000...
126
127 [5555fe852c5555555555555555fe0000]
128 */
129 void ReadTItag(void)
130 {
131 // some hardcoded initial params
132 // when we read a TI tag we sample the zerocross line at 2Mhz
133 // TI tags modulate a 1 as 16 cycles of 123.2Khz
134 // TI tags modulate a 0 as 16 cycles of 134.2Khz
135 #define FSAMPLE 2000000
136 #define FREQLO 123200
137 #define FREQHI 134200
138
139 signed char *dest = (signed char *)BigBuf;
140 int n = sizeof(BigBuf);
141 // int *dest = GraphBuffer;
142 // int n = GraphTraceLen;
143
144 // 128 bit shift register [shift3:shift2:shift1:shift0]
145 DWORD shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
146
147 int i, cycles=0, samples=0;
148 // how many sample points fit in 16 cycles of each frequency
149 DWORD sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
150 // when to tell if we're close enough to one freq or another
151 DWORD threshold = (sampleslo - sampleshi + 1)>>1;
152
153 // TI tags charge at 134.2Khz
154 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
155
156 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
157 // connects to SSP_DIN and the SSP_DOUT logic level controls
158 // whether we're modulating the antenna (high)
159 // or listening to the antenna (low)
160 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
161
162 // get TI tag data into the buffer
163 AcquireTiType();
164
165 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
166
167 for (i=0; i<n-1; i++) {
168 // count cycles by looking for lo to hi zero crossings
169 if ( (dest[i]<0) && (dest[i+1]>0) ) {
170 cycles++;
171 // after 16 cycles, measure the frequency
172 if (cycles>15) {
173 cycles=0;
174 samples=i-samples; // number of samples in these 16 cycles
175
176 // TI bits are coming to us lsb first so shift them
177 // right through our 128 bit right shift register
178 shift0 = (shift0>>1) | (shift1 << 31);
179 shift1 = (shift1>>1) | (shift2 << 31);
180 shift2 = (shift2>>1) | (shift3 << 31);
181 shift3 >>= 1;
182
183 // check if the cycles fall close to the number
184 // expected for either the low or high frequency
185 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
186 // low frequency represents a 1
187 shift3 |= (1<<31);
188 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
189 // high frequency represents a 0
190 } else {
191 // probably detected a gay waveform or noise
192 // use this as gaydar or discard shift register and start again
193 shift3 = shift2 = shift1 = shift0 = 0;
194 }
195 samples = i;
196
197 // for each bit we receive, test if we've detected a valid tag
198
199 // if we see 17 zeroes followed by 6 ones, we might have a tag
200 // remember the bits are backwards
201 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
202 // if start and end bytes match, we have a tag so break out of the loop
203 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
204 cycles = 0xF0B; //use this as a flag (ugly but whatever)
205 break;
206 }
207 }
208 }
209 }
210 }
211
212 // if flag is set we have a tag
213 if (cycles!=0xF0B) {
214 DbpString("Info: No valid tag detected.");
215 } else {
216 // put 64 bit data into shift1 and shift0
217 shift0 = (shift0>>24) | (shift1 << 8);
218 shift1 = (shift1>>24) | (shift2 << 8);
219
220 // align 16 bit crc into lower half of shift2
221 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
222
223 // if r/w tag, check ident match
224 if ( shift3&(1<<15) ) {
225 DbpString("Info: TI tag is rewriteable");
226 // only 15 bits compare, last bit of ident is not valid
227 if ( ((shift3>>16)^shift0)&0x7fff ) {
228 DbpString("Error: Ident mismatch!");
229 } else {
230 DbpString("Info: TI tag ident is valid");
231 }
232 } else {
233 DbpString("Info: TI tag is readonly");
234 }
235
236 // WARNING the order of the bytes in which we calc crc below needs checking
237 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
238 // bytes in reverse or something
239 // calculate CRC
240 DWORD crc=0;
241
242 crc = update_crc16(crc, (shift0)&0xff);
243 crc = update_crc16(crc, (shift0>>8)&0xff);
244 crc = update_crc16(crc, (shift0>>16)&0xff);
245 crc = update_crc16(crc, (shift0>>24)&0xff);
246 crc = update_crc16(crc, (shift1)&0xff);
247 crc = update_crc16(crc, (shift1>>8)&0xff);
248 crc = update_crc16(crc, (shift1>>16)&0xff);
249 crc = update_crc16(crc, (shift1>>24)&0xff);
250
251 Dbprintf("Info: Tag data_hi=%x, data_lo=%x, crc=%x",
252 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
253 if (crc != (shift2&0xffff)) {
254 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
255 } else {
256 DbpString("Info: CRC is good");
257 }
258 }
259 }
260
261 void WriteTIbyte(BYTE b)
262 {
263 int i = 0;
264
265 // modulate 8 bits out to the antenna
266 for (i=0; i<8; i++)
267 {
268 if (b&(1<<i)) {
269 // stop modulating antenna
270 LOW(GPIO_SSC_DOUT);
271 SpinDelayUs(1000);
272 // modulate antenna
273 HIGH(GPIO_SSC_DOUT);
274 SpinDelayUs(1000);
275 } else {
276 // stop modulating antenna
277 LOW(GPIO_SSC_DOUT);
278 SpinDelayUs(300);
279 // modulate antenna
280 HIGH(GPIO_SSC_DOUT);
281 SpinDelayUs(1700);
282 }
283 }
284 }
285
286 void AcquireTiType(void)
287 {
288 int i, j, n;
289 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
290 // each sample is 1 bit stuffed into a DWORD so we need 1250 DWORDS
291 #define TIBUFLEN 1250
292
293 // clear buffer
294 memset(BigBuf,0,sizeof(BigBuf));
295
296 // Set up the synchronous serial port
297 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
298 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
299
300 // steal this pin from the SSP and use it to control the modulation
301 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
302 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
303
304 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
305 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
306
307 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
308 // 48/2 = 24 MHz clock must be divided by 12
309 AT91C_BASE_SSC->SSC_CMR = 12;
310
311 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
312 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
313 AT91C_BASE_SSC->SSC_TCMR = 0;
314 AT91C_BASE_SSC->SSC_TFMR = 0;
315
316 LED_D_ON();
317
318 // modulate antenna
319 HIGH(GPIO_SSC_DOUT);
320
321 // Charge TI tag for 50ms.
322 SpinDelay(50);
323
324 // stop modulating antenna and listen
325 LOW(GPIO_SSC_DOUT);
326
327 LED_D_OFF();
328
329 i = 0;
330 for(;;) {
331 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
332 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
333 i++; if(i >= TIBUFLEN) break;
334 }
335 WDT_HIT();
336 }
337
338 // return stolen pin to SSP
339 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
340 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
341
342 char *dest = (char *)BigBuf;
343 n = TIBUFLEN*32;
344 // unpack buffer
345 for (i=TIBUFLEN-1; i>=0; i--) {
346 // DbpIntegers(0, 0, BigBuf[i]);
347 for (j=0; j<32; j++) {
348 if(BigBuf[i] & (1 << j)) {
349 dest[--n] = 1;
350 } else {
351 dest[--n] = -1;
352 }
353 }
354 }
355 }
356
357 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
358 // if crc provided, it will be written with the data verbatim (even if bogus)
359 // if not provided a valid crc will be computed from the data and written.
360 void WriteTItag(DWORD idhi, DWORD idlo, WORD crc)
361 {
362
363 // WARNING the order of the bytes in which we calc crc below needs checking
364 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
365 // bytes in reverse or something
366
367 if(crc == 0) {
368 crc = update_crc16(crc, (idlo)&0xff);
369 crc = update_crc16(crc, (idlo>>8)&0xff);
370 crc = update_crc16(crc, (idlo>>16)&0xff);
371 crc = update_crc16(crc, (idlo>>24)&0xff);
372 crc = update_crc16(crc, (idhi)&0xff);
373 crc = update_crc16(crc, (idhi>>8)&0xff);
374 crc = update_crc16(crc, (idhi>>16)&0xff);
375 crc = update_crc16(crc, (idhi>>24)&0xff);
376 }
377 Dbprintf("Writing the following data to tag: %x, %x, %x",
378 (unsigned int) idhi, (unsigned int) idlo, crc);
379
380 // TI tags charge at 134.2Khz
381 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
382 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
383 // connects to SSP_DIN and the SSP_DOUT logic level controls
384 // whether we're modulating the antenna (high)
385 // or listening to the antenna (low)
386 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
387 LED_A_ON();
388
389 // steal this pin from the SSP and use it to control the modulation
390 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
391 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
392
393 // writing algorithm:
394 // a high bit consists of a field off for 1ms and field on for 1ms
395 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
396 // initiate a charge time of 50ms (field on) then immediately start writing bits
397 // start by writing 0xBB (keyword) and 0xEB (password)
398 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
399 // finally end with 0x0300 (write frame)
400 // all data is sent lsb firts
401 // finish with 15ms programming time
402
403 // modulate antenna
404 HIGH(GPIO_SSC_DOUT);
405 SpinDelay(50); // charge time
406
407 WriteTIbyte(0xbb); // keyword
408 WriteTIbyte(0xeb); // password
409 WriteTIbyte( (idlo )&0xff );
410 WriteTIbyte( (idlo>>8 )&0xff );
411 WriteTIbyte( (idlo>>16)&0xff );
412 WriteTIbyte( (idlo>>24)&0xff );
413 WriteTIbyte( (idhi )&0xff );
414 WriteTIbyte( (idhi>>8 )&0xff );
415 WriteTIbyte( (idhi>>16)&0xff );
416 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
417 WriteTIbyte( (crc )&0xff ); // crc lo
418 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
419 WriteTIbyte(0x00); // write frame lo
420 WriteTIbyte(0x03); // write frame hi
421 HIGH(GPIO_SSC_DOUT);
422 SpinDelay(50); // programming time
423
424 LED_A_OFF();
425
426 // get TI tag data into the buffer
427 AcquireTiType();
428
429 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
430 DbpString("Now use tiread to check");
431 }
432
433 void SimulateTagLowFrequency(int period, int ledcontrol)
434 {
435 int i;
436 BYTE *tab = (BYTE *)BigBuf;
437
438 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_SIMULATOR);
439
440 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
441
442 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
443 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
444
445 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
446 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
447
448 i = 0;
449 for(;;) {
450 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
451 if(BUTTON_PRESS()) {
452 DbpString("Stopped");
453 return;
454 }
455 WDT_HIT();
456 }
457
458 if (ledcontrol)
459 LED_D_ON();
460
461 if(tab[i])
462 OPEN_COIL();
463 else
464 SHORT_COIL();
465
466 if (ledcontrol)
467 LED_D_OFF();
468
469 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
470 if(BUTTON_PRESS()) {
471 DbpString("Stopped");
472 return;
473 }
474 WDT_HIT();
475 }
476
477 i++;
478 if(i == period) i = 0;
479 }
480 }
481
482 /* Provides a framework for bidirectional LF tag communication
483 * Encoding is currently Hitag2, but the general idea can probably
484 * be transferred to other encodings.
485 *
486 * The new FPGA code will, for the LF simulator mode, give on SSC_FRAME
487 * (PA15) a thresholded version of the signal from the ADC. Setting the
488 * ADC path to the low frequency peak detection signal, will enable a
489 * somewhat reasonable receiver for modulation on the carrier signal
490 * that is generated by the reader. The signal is low when the reader
491 * field is switched off, and high when the reader field is active. Due
492 * to the way that the signal looks like, mostly only the rising edge is
493 * useful, your mileage may vary.
494 *
495 * Neat perk: PA15 can not only be used as a bit-banging GPIO, but is also
496 * TIOA1, which can be used as the capture input for timer 1. This should
497 * make it possible to measure the exact edge-to-edge time, without processor
498 * intervention.
499 *
500 * Arguments: divisor is the divisor to be sent to the FPGA (e.g. 95 for 125kHz)
501 * t0 is the carrier frequency cycle duration in terms of MCK (384 for 125kHz)
502 *
503 * The following defines are in carrier periods:
504 */
505 #define HITAG_T_0_MIN 15 /* T[0] should be 18..22 */
506 #define HITAG_T_1_MIN 24 /* T[1] should be 26..30 */
507 #define HITAG_T_EOF 40 /* T_EOF should be > 36 */
508 #define HITAG_T_WRESP 208 /* T_wresp should be 204..212 */
509
510 static void hitag_handle_frame(int t0, int frame_len, char *frame);
511 //#define DEBUG_RA_VALUES 1
512 #define DEBUG_FRAME_CONTENTS 1
513 void SimulateTagLowFrequencyBidir(int divisor, int t0)
514 {
515 #if DEBUG_RA_VALUES || DEBUG_FRAME_CONTENTS
516 int i = 0;
517 #endif
518 char frame[10];
519 int frame_pos=0;
520
521 DbpString("Starting Hitag2 emulator, press button to end");
522 hitag2_init();
523
524 /* Set up simulator mode, frequency divisor which will drive the FPGA
525 * and analog mux selection.
526 */
527 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_SIMULATOR);
528 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
529 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
530 RELAY_OFF();
531
532 /* Set up Timer 1:
533 * Capture mode, timer source MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
534 * external trigger rising edge, load RA on rising edge of TIOA, load RB on rising
535 * edge of TIOA. Assign PA15 to TIOA1 (peripheral B)
536 */
537
538 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
539 AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME;
540 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
541 AT91C_BASE_TC1->TC_CMR = TC_CMR_TCCLKS_TIMER_CLOCK1 |
542 AT91C_TC_ETRGEDG_RISING |
543 AT91C_TC_ABETRG |
544 AT91C_TC_LDRA_RISING |
545 AT91C_TC_LDRB_RISING;
546 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN |
547 AT91C_TC_SWTRG;
548
549 /* calculate the new value for the carrier period in terms of TC1 values */
550 t0 = t0/2;
551
552 int overflow = 0;
553 while(!BUTTON_PRESS()) {
554 WDT_HIT();
555 if(AT91C_BASE_TC1->TC_SR & AT91C_TC_LDRAS) {
556 int ra = AT91C_BASE_TC1->TC_RA;
557 if((ra > t0*HITAG_T_EOF) | overflow) ra = t0*HITAG_T_EOF+1;
558 #if DEBUG_RA_VALUES
559 if(ra > 255 || overflow) ra = 255;
560 ((char*)BigBuf)[i] = ra;
561 i = (i+1) % 8000;
562 #endif
563
564 if(overflow || (ra > t0*HITAG_T_EOF) || (ra < t0*HITAG_T_0_MIN)) {
565 /* Ignore */
566 } else if(ra >= t0*HITAG_T_1_MIN ) {
567 /* '1' bit */
568 if(frame_pos < 8*sizeof(frame)) {
569 frame[frame_pos / 8] |= 1<<( 7-(frame_pos%8) );
570 frame_pos++;
571 }
572 } else if(ra >= t0*HITAG_T_0_MIN) {
573 /* '0' bit */
574 if(frame_pos < 8*sizeof(frame)) {
575 frame[frame_pos / 8] |= 0<<( 7-(frame_pos%8) );
576 frame_pos++;
577 }
578 }
579
580 overflow = 0;
581 LED_D_ON();
582 } else {
583 if(AT91C_BASE_TC1->TC_CV > t0*HITAG_T_EOF) {
584 /* Minor nuisance: In Capture mode, the timer can not be
585 * stopped by a Compare C. There's no way to stop the clock
586 * in software, so we'll just have to note the fact that an
587 * overflow happened and the next loaded timer value might
588 * have wrapped. Also, this marks the end of frame, and the
589 * still running counter can be used to determine the correct
590 * time for the start of the reply.
591 */
592 overflow = 1;
593
594 if(frame_pos > 0) {
595 /* Have a frame, do something with it */
596 #if DEBUG_FRAME_CONTENTS
597 ((char*)BigBuf)[i++] = frame_pos;
598 memcpy( ((char*)BigBuf)+i, frame, 7);
599 i+=7;
600 i = i % sizeof(BigBuf);
601 #endif
602 hitag_handle_frame(t0, frame_pos, frame);
603 memset(frame, 0, sizeof(frame));
604 }
605 frame_pos = 0;
606
607 }
608 LED_D_OFF();
609 }
610 }
611 DbpString("All done");
612 }
613
614 static void hitag_send_bit(int t0, int bit) {
615 if(bit == 1) {
616 /* Manchester: Loaded, then unloaded */
617 LED_A_ON();
618 SHORT_COIL();
619 while(AT91C_BASE_TC1->TC_CV < t0*15);
620 OPEN_COIL();
621 while(AT91C_BASE_TC1->TC_CV < t0*31);
622 LED_A_OFF();
623 } else if(bit == 0) {
624 /* Manchester: Unloaded, then loaded */
625 LED_B_ON();
626 OPEN_COIL();
627 while(AT91C_BASE_TC1->TC_CV < t0*15);
628 SHORT_COIL();
629 while(AT91C_BASE_TC1->TC_CV < t0*31);
630 LED_B_OFF();
631 }
632 AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG; /* Reset clock for the next bit */
633
634 }
635 static void hitag_send_frame(int t0, int frame_len, const char const * frame, int fdt)
636 {
637 OPEN_COIL();
638 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
639
640 /* Wait for HITAG_T_WRESP carrier periods after the last reader bit,
641 * not that since the clock counts since the rising edge, but T_wresp is
642 * with respect to the falling edge, we need to wait actually (T_wresp - T_g)
643 * periods. The gap time T_g varies (4..10).
644 */
645 while(AT91C_BASE_TC1->TC_CV < t0*(fdt-8));
646
647 int saved_cmr = AT91C_BASE_TC1->TC_CMR;
648 AT91C_BASE_TC1->TC_CMR &= ~AT91C_TC_ETRGEDG; /* Disable external trigger for the clock */
649 AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG; /* Reset the clock and use it for response timing */
650
651 int i;
652 for(i=0; i<5; i++)
653 hitag_send_bit(t0, 1); /* Start of frame */
654
655 for(i=0; i<frame_len; i++) {
656 hitag_send_bit(t0, !!(frame[i/ 8] & (1<<( 7-(i%8) ))) );
657 }
658
659 OPEN_COIL();
660 AT91C_BASE_TC1->TC_CMR = saved_cmr;
661 }
662
663 /* Callback structure to cleanly separate tag emulation code from the radio layer. */
664 static int hitag_cb(const char* response_data, const int response_length, const int fdt, void *cb_cookie)
665 {
666 hitag_send_frame(*(int*)cb_cookie, response_length, response_data, fdt);
667 return 0;
668 }
669 /* Frame length in bits, frame contents in MSBit first format */
670 static void hitag_handle_frame(int t0, int frame_len, char *frame)
671 {
672 hitag2_handle_command(frame, frame_len, hitag_cb, &t0);
673 }
674
675 // compose fc/8 fc/10 waveform
676 static void fc(int c, int *n) {
677 BYTE *dest = (BYTE *)BigBuf;
678 int idx;
679
680 // for when we want an fc8 pattern every 4 logical bits
681 if(c==0) {
682 dest[((*n)++)]=1;
683 dest[((*n)++)]=1;
684 dest[((*n)++)]=0;
685 dest[((*n)++)]=0;
686 dest[((*n)++)]=0;
687 dest[((*n)++)]=0;
688 dest[((*n)++)]=0;
689 dest[((*n)++)]=0;
690 }
691 // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples
692 if(c==8) {
693 for (idx=0; idx<6; idx++) {
694 dest[((*n)++)]=1;
695 dest[((*n)++)]=1;
696 dest[((*n)++)]=0;
697 dest[((*n)++)]=0;
698 dest[((*n)++)]=0;
699 dest[((*n)++)]=0;
700 dest[((*n)++)]=0;
701 dest[((*n)++)]=0;
702 }
703 }
704
705 // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples
706 if(c==10) {
707 for (idx=0; idx<5; idx++) {
708 dest[((*n)++)]=1;
709 dest[((*n)++)]=1;
710 dest[((*n)++)]=1;
711 dest[((*n)++)]=0;
712 dest[((*n)++)]=0;
713 dest[((*n)++)]=0;
714 dest[((*n)++)]=0;
715 dest[((*n)++)]=0;
716 dest[((*n)++)]=0;
717 dest[((*n)++)]=0;
718 }
719 }
720 }
721
722 // prepare a waveform pattern in the buffer based on the ID given then
723 // simulate a HID tag until the button is pressed
724 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
725 {
726 int n=0, i=0;
727 /*
728 HID tag bitstream format
729 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
730 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
731 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
732 A fc8 is inserted before every 4 bits
733 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
734 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
735 */
736
737 if (hi>0xFFF) {
738 DbpString("Tags can only have 44 bits.");
739 return;
740 }
741 fc(0,&n);
742 // special start of frame marker containing invalid bit sequences
743 fc(8, &n); fc(8, &n); // invalid
744 fc(8, &n); fc(10, &n); // logical 0
745 fc(10, &n); fc(10, &n); // invalid
746 fc(8, &n); fc(10, &n); // logical 0
747
748 WDT_HIT();
749 // manchester encode bits 43 to 32
750 for (i=11; i>=0; i--) {
751 if ((i%4)==3) fc(0,&n);
752 if ((hi>>i)&1) {
753 fc(10, &n); fc(8, &n); // low-high transition
754 } else {
755 fc(8, &n); fc(10, &n); // high-low transition
756 }
757 }
758
759 WDT_HIT();
760 // manchester encode bits 31 to 0
761 for (i=31; i>=0; i--) {
762 if ((i%4)==3) fc(0,&n);
763 if ((lo>>i)&1) {
764 fc(10, &n); fc(8, &n); // low-high transition
765 } else {
766 fc(8, &n); fc(10, &n); // high-low transition
767 }
768 }
769
770 if (ledcontrol)
771 LED_A_ON();
772 SimulateTagLowFrequency(n, ledcontrol);
773
774 if (ledcontrol)
775 LED_A_OFF();
776 }
777
778
779 // loop to capture raw HID waveform then FSK demodulate the TAG ID from it
780 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
781 {
782 BYTE *dest = (BYTE *)BigBuf;
783 int m=0, n=0, i=0, idx=0, found=0, lastval=0;
784 DWORD hi=0, lo=0;
785
786 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
787 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
788
789 // Connect the A/D to the peak-detected low-frequency path.
790 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
791
792 // Give it a bit of time for the resonant antenna to settle.
793 SpinDelay(50);
794
795 // Now set up the SSC to get the ADC samples that are now streaming at us.
796 FpgaSetupSsc();
797
798 for(;;) {
799 WDT_HIT();
800 if (ledcontrol)
801 LED_A_ON();
802 if(BUTTON_PRESS()) {
803 DbpString("Stopped");
804 if (ledcontrol)
805 LED_A_OFF();
806 return;
807 }
808
809 i = 0;
810 m = sizeof(BigBuf);
811 memset(dest,128,m);
812 for(;;) {
813 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
814 AT91C_BASE_SSC->SSC_THR = 0x43;
815 if (ledcontrol)
816 LED_D_ON();
817 }
818 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
819 dest[i] = (BYTE)AT91C_BASE_SSC->SSC_RHR;
820 // we don't care about actual value, only if it's more or less than a
821 // threshold essentially we capture zero crossings for later analysis
822 if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
823 i++;
824 if (ledcontrol)
825 LED_D_OFF();
826 if(i >= m) {
827 break;
828 }
829 }
830 }
831
832 // FSK demodulator
833
834 // sync to first lo-hi transition
835 for( idx=1; idx<m; idx++) {
836 if (dest[idx-1]<dest[idx])
837 lastval=idx;
838 break;
839 }
840 WDT_HIT();
841
842 // count cycles between consecutive lo-hi transitions, there should be either 8 (fc/8)
843 // or 10 (fc/10) cycles but in practice due to noise etc we may end up with with anywhere
844 // between 7 to 11 cycles so fuzz it by treat anything <9 as 8 and anything else as 10
845 for( i=0; idx<m; idx++) {
846 if (dest[idx-1]<dest[idx]) {
847 dest[i]=idx-lastval;
848 if (dest[i] <= 8) {
849 dest[i]=1;
850 } else {
851 dest[i]=0;
852 }
853
854 lastval=idx;
855 i++;
856 }
857 }
858 m=i;
859 WDT_HIT();
860
861 // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
862 lastval=dest[0];
863 idx=0;
864 i=0;
865 n=0;
866 for( idx=0; idx<m; idx++) {
867 if (dest[idx]==lastval) {
868 n++;
869 } else {
870 // a bit time is five fc/10 or six fc/8 cycles so figure out how many bits a pattern width represents,
871 // an extra fc/8 pattern preceeds every 4 bits (about 200 cycles) just to complicate things but it gets
872 // swallowed up by rounding
873 // expected results are 1 or 2 bits, any more and it's an invalid manchester encoding
874 // special start of frame markers use invalid manchester states (no transitions) by using sequences
875 // like 111000
876 if (dest[idx-1]) {
877 n=(n+1)/6; // fc/8 in sets of 6
878 } else {
879 n=(n+1)/5; // fc/10 in sets of 5
880 }
881 switch (n) { // stuff appropriate bits in buffer
882 case 0:
883 case 1: // one bit
884 dest[i++]=dest[idx-1];
885 break;
886 case 2: // two bits
887 dest[i++]=dest[idx-1];
888 dest[i++]=dest[idx-1];
889 break;
890 case 3: // 3 bit start of frame markers
891 dest[i++]=dest[idx-1];
892 dest[i++]=dest[idx-1];
893 dest[i++]=dest[idx-1];
894 break;
895 // When a logic 0 is immediately followed by the start of the next transmisson
896 // (special pattern) a pattern of 4 bit duration lengths is created.
897 case 4:
898 dest[i++]=dest[idx-1];
899 dest[i++]=dest[idx-1];
900 dest[i++]=dest[idx-1];
901 dest[i++]=dest[idx-1];
902 break;
903 default: // this shouldn't happen, don't stuff any bits
904 break;
905 }
906 n=0;
907 lastval=dest[idx];
908 }
909 }
910 m=i;
911 WDT_HIT();
912
913 // final loop, go over previously decoded manchester data and decode into usable tag ID
914 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
915 for( idx=0; idx<m-6; idx++) {
916 // search for a start of frame marker
917 if ( dest[idx] && dest[idx+1] && dest[idx+2] && (!dest[idx+3]) && (!dest[idx+4]) && (!dest[idx+5]) )
918 {
919 found=1;
920 idx+=6;
921 if (found && (hi|lo)) {
922 Dbprintf("TAG ID: %x %x %x",
923 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
924 /* if we're only looking for one tag */
925 if (findone)
926 {
927 *high = hi;
928 *low = lo;
929 return;
930 }
931 hi=0;
932 lo=0;
933 found=0;
934 }
935 }
936 if (found) {
937 if (dest[idx] && (!dest[idx+1]) ) {
938 hi=(hi<<1)|(lo>>31);
939 lo=(lo<<1)|0;
940 } else if ( (!dest[idx]) && dest[idx+1]) {
941 hi=(hi<<1)|(lo>>31);
942 lo=(lo<<1)|1;
943 } else {
944 found=0;
945 hi=0;
946 lo=0;
947 }
948 idx++;
949 }
950 if ( dest[idx] && dest[idx+1] && dest[idx+2] && (!dest[idx+3]) && (!dest[idx+4]) && (!dest[idx+5]) )
951 {
952 found=1;
953 idx+=6;
954 if (found && (hi|lo)) {
955 Dbprintf("TAG ID: %x %x %x",
956 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
957 /* if we're only looking for one tag */
958 if (findone)
959 {
960 *high = hi;
961 *low = lo;
962 return;
963 }
964 hi=0;
965 lo=0;
966 found=0;
967 }
968 }
969 }
970 WDT_HIT();
971 }
972 }
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