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1 //-----------------------------------------------------------------------------
2 // (c) 2009 Henryk Plötz <henryk@ploetzli.ch>
3 //
4 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
5 // at your option, any later version. See the LICENSE.txt file for the text of
6 // the license.
7 //-----------------------------------------------------------------------------
8 // LEGIC RF simulation code
9 //-----------------------------------------------------------------------------
10 #include "legicrf.h"
11
12 static struct legic_frame {
13 uint8_t bits;
14 uint32_t data;
15 } current_frame;
16
17 static enum {
18 STATE_DISCON,
19 STATE_IV,
20 STATE_CON,
21 } legic_state;
22
23 static crc_t legic_crc;
24 static int legic_read_count;
25 static uint32_t legic_prng_bc;
26 static uint32_t legic_prng_iv;
27
28 static int legic_phase_drift;
29 static int legic_frame_drift;
30 static int legic_reqresp_drift;
31
32 AT91PS_TC timer;
33 AT91PS_TC prng_timer;
34
35 /*
36 static void setup_timer(void) {
37 // Set up Timer 1 to use for measuring time between pulses. Since we're bit-banging
38 // this it won't be terribly accurate but should be good enough.
39 //
40 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
41 timer = AT91C_BASE_TC1;
42 timer->TC_CCR = AT91C_TC_CLKDIS;
43 timer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK;
44 timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
45
46 //
47 // Set up Timer 2 to use for measuring time between frames in
48 // tag simulation mode. Runs 4x faster as Timer 1
49 //
50 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC2);
51 prng_timer = AT91C_BASE_TC2;
52 prng_timer->TC_CCR = AT91C_TC_CLKDIS;
53 prng_timer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV2_CLOCK;
54 prng_timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
55 }
56
57 AT91C_BASE_PMC->PMC_PCER |= (0x1 << 12) | (0x1 << 13) | (0x1 << 14);
58 AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
59
60 // fast clock
61 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable
62 AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz)/32 -- tick=1.5mks
63 AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR |
64 AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;
65 AT91C_BASE_TC0->TC_RA = 1;
66 AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000
67
68 */
69
70 // At TIMER_CLOCK3 (MCK/32)
71 // testing calculating in (us) microseconds.
72 #define RWD_TIME_1 120 // READER_TIME_PAUSE 20us off, 80us on = 100us 80 * 1.5 == 120ticks
73 #define RWD_TIME_0 60 // READER_TIME_PAUSE 20us off, 40us on = 60us 40 * 1.5 == 60ticks
74 #define RWD_TIME_PAUSE 30 // 20us == 20 * 1.5 == 30ticks */
75 #define TAG_BIT_PERIOD 142 // 100us == 100 * 1.5 == 150ticks
76 #define TAG_FRAME_WAIT 495 // 330us from READER frame end to TAG frame start. 330 * 1.5 == 495
77
78 #define RWD_TIME_FUZZ 20 // rather generous 13us, since the peak detector + hysteresis fuzz quite a bit
79
80 #define SIM_DIVISOR 586 /* prng_time/SIM_DIVISOR count prng needs to be forwared */
81 #define SIM_SHIFT 900 /* prng_time+SIM_SHIFT shift of delayed start */
82
83 #define OFFSET_LOG 1024
84
85 #define FUZZ_EQUAL(value, target, fuzz) ((value) > ((target)-(fuzz)) && (value) < ((target)+(fuzz)))
86
87 #ifndef SHORT_COIL
88 # define SHORT_COIL LOW(GPIO_SSC_DOUT);
89 #endif
90 #ifndef OPEN_COIL
91 # define OPEN_COIL HIGH(GPIO_SSC_DOUT);
92 #endif
93
94 // Pause pulse, off in 20us / 30ticks,
95 // ONE / ZERO bit pulse,
96 // one == 80us / 120ticks
97 // zero == 40us / 60ticks
98 #ifndef COIL_PULSE
99 # define COIL_PULSE(x) \
100 do { \
101 SHORT_COIL; \
102 WaitTicks( (RWD_TIME_PAUSE) ); \
103 OPEN_COIL; \
104 WaitTicks((x)); \
105 } while (0)
106 #endif
107
108 // ToDo: define a meaningful maximum size for auth_table. The bigger this is, the lower will be the available memory for traces.
109 // Historically it used to be FREE_BUFFER_SIZE, which was 2744.
110 #define LEGIC_CARD_MEMSIZE 1024
111 static uint8_t* cardmem;
112
113 static void frame_append_bit(struct legic_frame * const f, uint8_t bit) {
114 // Overflow, won't happen
115 if (f->bits >= 31) return;
116
117 f->data |= (bit << f->bits);
118 f->bits++;
119 }
120
121 static void frame_clean(struct legic_frame * const f) {
122 f->data = 0;
123 f->bits = 0;
124 }
125
126 // Prng works when waiting in 99.1us cycles.
127 // and while sending/receiving in bit frames (100, 60)
128 /*static void CalibratePrng( uint32_t time){
129 // Calculate Cycles based on timer 100us
130 uint32_t i = (time - sendFrameStop) / 100 ;
131
132 // substract cycles of finished frames
133 int k = i - legic_prng_count()+1;
134
135 // substract current frame length, rewind to beginning
136 if ( k > 0 )
137 legic_prng_forward(k);
138 }
139 */
140
141 /* Generate Keystream */
142 uint32_t get_key_stream(int skip, int count) {
143 uint32_t key = 0;
144 int i;
145
146 // Use int to enlarge timer tc to 32bit
147 legic_prng_bc += prng_timer->TC_CV;
148
149 // reset the prng timer.
150 ResetTimer(prng_timer);
151
152 /* If skip == -1, forward prng time based */
153 if(skip == -1) {
154 i = (legic_prng_bc + SIM_SHIFT)/SIM_DIVISOR; /* Calculate Cycles based on timer */
155 i -= legic_prng_count(); /* substract cycles of finished frames */
156 i -= count; /* substract current frame length, rewind to beginning */
157 legic_prng_forward(i);
158 } else {
159 legic_prng_forward(skip);
160 }
161
162 i = (count == 6) ? -1 : legic_read_count;
163
164 /* Write Time Data into LOG */
165 // uint8_t *BigBuf = BigBuf_get_addr();
166 // BigBuf[OFFSET_LOG+128+i] = legic_prng_count();
167 // BigBuf[OFFSET_LOG+256+i*4] = (legic_prng_bc >> 0) & 0xff;
168 // BigBuf[OFFSET_LOG+256+i*4+1] = (legic_prng_bc >> 8) & 0xff;
169 // BigBuf[OFFSET_LOG+256+i*4+2] = (legic_prng_bc >>16) & 0xff;
170 // BigBuf[OFFSET_LOG+256+i*4+3] = (legic_prng_bc >>24) & 0xff;
171 // BigBuf[OFFSET_LOG+384+i] = count;
172
173 /* Generate KeyStream */
174 for(i=0; i<count; i++) {
175 key |= legic_prng_get_bit() << i;
176 legic_prng_forward(1);
177 }
178 return key;
179 }
180
181 /* Send a frame in tag mode, the FPGA must have been set up by
182 * LegicRfSimulate
183 */
184 void frame_send_tag(uint16_t response, uint8_t bits, uint8_t crypt) {
185 /* Bitbang the response */
186 LOW(GPIO_SSC_DOUT);
187 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
188 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
189
190 /* Use time to crypt frame */
191 if(crypt) {
192 legic_prng_forward(2); /* TAG_FRAME_WAIT -> shift by 2 */
193 response ^= legic_prng_get_bits(bits);
194 }
195
196 /* Wait for the frame start */
197 WaitUS( TAG_FRAME_WAIT );
198
199 uint8_t bit = 0;
200 for(int i = 0; i < bits; i++) {
201
202 bit = response & 1;
203 response >>= 1;
204
205 if (bit)
206 HIGH(GPIO_SSC_DOUT);
207 else
208 LOW(GPIO_SSC_DOUT);
209
210 WaitUS(100);
211 }
212 LOW(GPIO_SSC_DOUT);
213 }
214
215 /* Send a frame in reader mode, the FPGA must have been set up by
216 * LegicRfReader
217 */
218 void frame_sendAsReader(uint32_t data, uint8_t bits){
219
220 uint32_t starttime = GET_TICKS, send = 0;
221 uint16_t mask = 1;
222
223 // xor lsfr onto data.
224 send = data ^ legic_prng_get_bits(bits);
225
226 for (; mask < BITMASK(bits); mask <<= 1) {
227 if (send & mask)
228 COIL_PULSE(RWD_TIME_1);
229 else
230 COIL_PULSE(RWD_TIME_0);
231 }
232
233 // Final pause to mark the end of the frame
234 COIL_PULSE(0);
235
236 // log
237 uint8_t cmdbytes[] = {bits, BYTEx(data, 0), BYTEx(data, 1), BYTEx(send, 0), BYTEx(send, 1)};
238 LogTrace(cmdbytes, sizeof(cmdbytes), starttime, GET_TICKS, NULL, TRUE);
239 }
240
241 /* Receive a frame from the card in reader emulation mode, the FPGA and
242 * timer must have been set up by LegicRfReader and frame_sendAsReader.
243 *
244 * The LEGIC RF protocol from card to reader does not include explicit
245 * frame start/stop information or length information. The reader must
246 * know beforehand how many bits it wants to receive. (Notably: a card
247 * sending a stream of 0-bits is indistinguishable from no card present.)
248 *
249 * Receive methodology: There is a fancy correlator in hi_read_rx_xcorr, but
250 * I'm not smart enough to use it. Instead I have patched hi_read_tx to output
251 * the ADC signal with hysteresis on SSP_DIN. Bit-bang that signal and look
252 * for edges. Count the edges in each bit interval. If they are approximately
253 * 0 this was a 0-bit, if they are approximately equal to the number of edges
254 * expected for a 212kHz subcarrier, this was a 1-bit. For timing we use the
255 * timer that's still running from frame_sendAsReader in order to get a synchronization
256 * with the frame that we just sent.
257 *
258 * FIXME: Because we're relying on the hysteresis to just do the right thing
259 * the range is severely reduced (and you'll probably also need a good antenna).
260 * So this should be fixed some time in the future for a proper receiver.
261 */
262 static void frame_receiveAsReader(struct legic_frame * const f, uint8_t bits) {
263
264 if ( bits > 32 ) return;
265
266 uint8_t i = bits, edges = 0;
267 uint32_t the_bit = 1, next_bit_at = 0, data = 0;
268 uint32_t old_level = 0;
269 volatile uint32_t level = 0;
270
271 frame_clean(f);
272
273 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
274 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
275
276 // calibrate the prng.
277 legic_prng_forward(2);
278 data = legic_prng_get_bits(bits);
279
280 //FIXED time between sending frame and now listening frame. 330us
281 uint32_t starttime = GET_TICKS;
282 // its about 9+9 ticks delay from end-send to here.
283 WaitTicks( 477 );
284
285 next_bit_at = GET_TICKS + TAG_BIT_PERIOD;
286
287 while ( i-- ){
288 edges = 0;
289 while ( GET_TICKS < next_bit_at) {
290
291 level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
292
293 if (level != old_level)
294 ++edges;
295
296 old_level = level;
297 }
298
299 next_bit_at += TAG_BIT_PERIOD;
300
301 // We expect 42 edges (ONE)
302 if ( edges > 20 )
303 data ^= the_bit;
304
305 the_bit <<= 1;
306 }
307
308 // output
309 f->data = data;
310 f->bits = bits;
311
312 // log
313 uint8_t cmdbytes[] = {bits, BYTEx(data, 0), BYTEx(data, 1)};
314 LogTrace(cmdbytes, sizeof(cmdbytes), starttime, GET_TICKS, NULL, FALSE);
315 }
316
317 // Setup pm3 as a Legic Reader
318 static uint32_t setup_phase_reader(uint8_t iv) {
319
320 // Switch on carrier and let the tag charge for 1ms
321 HIGH(GPIO_SSC_DOUT);
322 WaitUS(5000);
323
324 ResetTicks();
325
326 // no keystream yet
327 legic_prng_init(0);
328
329 // send IV handshake
330 frame_sendAsReader(iv, 7);
331
332 // Now both tag and reader has same IV. Prng can start.
333 legic_prng_init(iv);
334
335 frame_receiveAsReader(&current_frame, 6);
336
337 // 292us (438t) - fixed delay before sending ack.
338 // minus log and stuff 100tick?
339 WaitTicks(338);
340 legic_prng_forward(3);
341
342 // Send obsfuscated acknowledgment frame.
343 // 0x19 = 0x18 MIM22, 0x01 LSB READCMD
344 // 0x39 = 0x38 MIM256, MIM1024 0x01 LSB READCMD
345 switch ( current_frame.data ) {
346 case 0x0D: frame_sendAsReader(0x19, 6); break;
347 case 0x1D:
348 case 0x3D: frame_sendAsReader(0x39, 6); break;
349 default: break;
350 }
351
352 legic_prng_forward(2);
353 return current_frame.data;
354 }
355
356 static void LegicCommonInit(void) {
357
358 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
359 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX);
360 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
361
362 /* Bitbang the transmitter */
363 LOW(GPIO_SSC_DOUT);
364 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
365 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
366
367 // reserve a cardmem, meaning we can use the tracelog function in bigbuff easier.
368 cardmem = BigBuf_get_EM_addr();
369 memset(cardmem, 0x00, LEGIC_CARD_MEMSIZE);
370
371 clear_trace();
372 set_tracing(TRUE);
373 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
374
375 StartTicks();
376 }
377
378 // Switch off carrier, make sure tag is reset
379 static void switch_off_tag_rwd(void) {
380 LOW(GPIO_SSC_DOUT);
381 WaitUS(20);
382 WDT_HIT();
383 }
384
385 // calculate crc4 for a legic READ command
386 static uint32_t legic4Crc(uint8_t cmd, uint16_t byte_index, uint8_t value, uint8_t cmd_sz) {
387 crc_clear(&legic_crc);
388 uint32_t temp = (value << cmd_sz) | (byte_index << 1) | cmd;
389 crc_update(&legic_crc, temp, cmd_sz + 8 );
390 return crc_finish(&legic_crc);
391 }
392
393 int legic_read_byte( uint16_t index, uint8_t cmd_sz) {
394
395 uint8_t byte, crc, calcCrc = 0;
396 uint32_t cmd = (index << 1) | LEGIC_READ;
397
398 // 90ticks = 60us (should be 100us but crc calc takes time.)
399 //WaitTicks(330); // 330ticks prng(4) - works
400 WaitTicks(240); // 240ticks prng(3) - works
401
402 frame_sendAsReader(cmd, cmd_sz);
403 frame_receiveAsReader(&current_frame, 12);
404
405 // CRC check.
406 byte = BYTEx(current_frame.data, 0);
407 crc = BYTEx(current_frame.data, 1);
408 calcCrc = legic4Crc(LEGIC_READ, index, byte, cmd_sz);
409
410 if( calcCrc != crc ) {
411 Dbprintf("!!! crc mismatch: expected %x but got %x !!!", calcCrc, crc);
412 return -1;
413 }
414
415 legic_prng_forward(3);
416 return byte;
417 }
418
419 /*
420 * - assemble a write_cmd_frame with crc and send it
421 * - wait until the tag sends back an ACK ('1' bit unencrypted)
422 * - forward the prng based on the timing
423 */
424 //int legic_write_byte(int byte, int addr, int addr_sz, int PrngCorrection) {
425 int legic_write_byte(uint8_t byte, uint16_t addr, uint8_t addr_sz) {
426
427 //do not write UID, CRC at offset 0-4.
428 if (addr <= 4) return 0;
429
430 // crc
431 crc_clear(&legic_crc);
432 crc_update(&legic_crc, 0, 1); /* CMD_WRITE */
433 crc_update(&legic_crc, addr, addr_sz);
434 crc_update(&legic_crc, byte, 8);
435 uint32_t crc = crc_finish(&legic_crc);
436 uint32_t crc2 = legic4Crc(LEGIC_WRITE, addr, byte, addr_sz+1);
437 if ( crc != crc2 ) {
438 Dbprintf("crc is missmatch");
439 return 1;
440 }
441 // send write command
442 uint32_t cmd = ((crc <<(addr_sz+1+8)) //CRC
443 |(byte <<(addr_sz+1)) //Data
444 |(addr <<1) //Address
445 | LEGIC_WRITE); //CMD = Write
446
447 uint32_t cmd_sz = addr_sz+1+8+4; //crc+data+cmd
448
449 legic_prng_forward(2); /* we wait anyways */
450
451 WaitTicks(330);
452
453 frame_sendAsReader(cmd, cmd_sz);
454
455 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
456 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
457
458 // wait for ack
459 int t, old_level = 0, edges = 0;
460 int next_bit_at = 0;
461
462 WaitUS(TAG_FRAME_WAIT);
463
464 for( t = 0; t < 80; ++t) {
465 edges = 0;
466 next_bit_at += TAG_BIT_PERIOD;
467 while(timer->TC_CV < next_bit_at) {
468 volatile uint32_t level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
469 if(level != old_level)
470 edges++;
471
472 old_level = level;
473 }
474 if(edges > 20 ) { /* expected are 42 edges */
475 int t = timer->TC_CV;
476 int c = t / TAG_BIT_PERIOD;
477
478 ResetTimer(timer);
479 legic_prng_forward(c);
480 return 0;
481 }
482 }
483
484 ResetTimer(timer);
485 return -1;
486 }
487
488 int LegicRfReader(uint16_t offset, uint16_t len, uint8_t iv) {
489
490 uint16_t i = 0;
491 uint8_t isOK = 1;
492 legic_card_select_t card;
493
494 LegicCommonInit();
495
496 if ( legic_select_card_iv(&card, iv) ) {
497 isOK = 0;
498 goto OUT;
499 }
500
501 switch_off_tag_rwd();
502
503 if (len + offset >= card.cardsize)
504 len = card.cardsize - offset;
505
506 setup_phase_reader(iv);
507
508 LED_B_ON();
509 while (i < len) {
510 int r = legic_read_byte(offset + i, card.cmdsize);
511
512 if (r == -1 || BUTTON_PRESS()) {
513 if ( MF_DBGLEVEL >= 2) DbpString("operation aborted");
514 isOK = 0;
515 goto OUT;
516 }
517 cardmem[i++] = r;
518 WDT_HIT();
519 }
520
521 OUT:
522 WDT_HIT();
523 switch_off_tag_rwd();
524 LEDsoff();
525 cmd_send(CMD_ACK, isOK, len, 0, cardmem, len);
526 return 0;
527 }
528
529 /*int _LegicRfWriter(int offset, int bytes, int addr_sz, uint8_t *BigBuf, int RoundBruteforceValue) {
530 int byte_index=0;
531
532 LED_B_ON();
533 setup_phase_reader(iv);
534 //legic_prng_forward(2);
535 while(byte_index < bytes) {
536 int r;
537
538 //check if the DCF should be changed
539 if ( (offset == 0x05) && (bytes == 0x02) ) {
540 //write DCF in reverse order (addr 0x06 before 0x05)
541 r = legic_write_byte(BigBuf[(0x06-byte_index)], (0x06-byte_index), addr_sz, RoundBruteforceValue);
542 //legic_prng_forward(1);
543 if(r == 0) {
544 byte_index++;
545 r = legic_write_byte(BigBuf[(0x06-byte_index)], (0x06-byte_index), addr_sz, RoundBruteforceValue);
546 }
547 //legic_prng_forward(1);
548 }
549 else {
550 r = legic_write_byte(BigBuf[byte_index+offset], byte_index+offset, addr_sz, RoundBruteforceValue);
551 }
552 if((r != 0) || BUTTON_PRESS()) {
553 Dbprintf("operation aborted @ 0x%03.3x", byte_index);
554 switch_off_tag_rwd();
555 LED_B_OFF();
556 LED_C_OFF();
557 return -1;
558 }
559
560 WDT_HIT();
561 byte_index++;
562 if(byte_index & 0x10) LED_C_ON(); else LED_C_OFF();
563 }
564 LED_B_OFF();
565 LED_C_OFF();
566 DbpString("write successful");
567 return 0;
568 }*/
569
570 void LegicRfWriter(uint16_t offset, uint16_t bytes, uint8_t iv) {
571
572 int byte_index = 0;
573 uint8_t isOK = 1;
574 legic_card_select_t card;
575
576 LegicCommonInit();
577
578 if ( legic_select_card_iv(&card, iv) ) {
579 isOK = 0;
580 goto OUT;
581 }
582
583 switch_off_tag_rwd();
584
585 switch(card.tagtype) {
586 case 0x0d:
587 if(offset+bytes > 22) {
588 Dbprintf("Error: can not write to 0x%03.3x on MIM22", offset + bytes);
589 return;
590 }
591 if ( MF_DBGLEVEL >= 2) Dbprintf("MIM22 card found, writing 0x%02.2x - 0x%02.2x ...", offset, offset + bytes);
592 break;
593 case 0x1d:
594 if(offset+bytes > 0x100) {
595 Dbprintf("Error: can not write to 0x%03.3x on MIM256", offset + bytes);
596 return;
597 }
598 if ( MF_DBGLEVEL >= 2) Dbprintf("MIM256 card found, writing 0x%02.2x - 0x%02.2x ...", offset, offset + bytes);
599 break;
600 case 0x3d:
601 if(offset+bytes > 0x400) {
602 Dbprintf("Error: can not write to 0x%03.3x on MIM1024", offset + bytes);
603 return;
604 }
605 if ( MF_DBGLEVEL >= 2) Dbprintf("MIM1024 card found, writing 0x%03.3x - 0x%03.3x ...", offset, offset + bytes);
606 break;
607 default:
608 return;
609 }
610
611 LED_B_ON();
612 setup_phase_reader(iv);
613
614 int r = 0;
615 while(byte_index < bytes) {
616
617 //check if the DCF should be changed
618 if ( ((byte_index+offset) == 0x05) && (bytes >= 0x02) ) {
619 //write DCF in reverse order (addr 0x06 before 0x05)
620 r = legic_write_byte(cardmem[(0x06-byte_index)], (0x06-byte_index), card.addrsize);
621
622 // write second byte on success
623 if(r == 0) {
624 byte_index++;
625 r = legic_write_byte(cardmem[(0x06-byte_index)], (0x06-byte_index), card.addrsize);
626 }
627 }
628 else {
629 r = legic_write_byte(cardmem[byte_index+offset], byte_index+offset, card.addrsize);
630 }
631
632 if ((r != 0) || BUTTON_PRESS()) {
633 Dbprintf("operation aborted @ 0x%03.3x", byte_index);
634 isOK = 0;
635 goto OUT;
636 }
637
638 WDT_HIT();
639 byte_index++;
640 }
641
642 OUT:
643 cmd_send(CMD_ACK, isOK, 0,0,0,0);
644 switch_off_tag_rwd();
645 LEDsoff();
646 }
647
648 void LegicRfRawWriter(int address, int byte, uint8_t iv) {
649
650 int byte_index = 0, addr_sz = 0;
651
652 LegicCommonInit();
653
654 if ( MF_DBGLEVEL >= 2) DbpString("setting up legic card");
655
656 uint32_t tag_type = setup_phase_reader(iv);
657
658 switch_off_tag_rwd();
659
660 switch(tag_type) {
661 case 0x0d:
662 if(address > 22) {
663 Dbprintf("Error: can not write to 0x%03.3x on MIM22", address);
664 return;
665 }
666 addr_sz = 5;
667 if ( MF_DBGLEVEL >= 2) Dbprintf("MIM22 card found, writing at addr 0x%02.2x - value 0x%02.2x ...", address, byte);
668 break;
669 case 0x1d:
670 if(address > 0x100) {
671 Dbprintf("Error: can not write to 0x%03.3x on MIM256", address);
672 return;
673 }
674 addr_sz = 8;
675 if ( MF_DBGLEVEL >= 2) Dbprintf("MIM256 card found, writing at addr 0x%02.2x - value 0x%02.2x ...", address, byte);
676 break;
677 case 0x3d:
678 if(address > 0x400) {
679 Dbprintf("Error: can not write to 0x%03.3x on MIM1024", address);
680 return;
681 }
682 addr_sz = 10;
683 if ( MF_DBGLEVEL >= 2) Dbprintf("MIM1024 card found, writing at addr 0x%03.3x - value 0x%03.3x ...", address, byte);
684 break;
685 default:
686 Dbprintf("No or unknown card found, aborting");
687 return;
688 }
689
690 Dbprintf("integer value: %d address: %d addr_sz: %d", byte, address, addr_sz);
691 LED_B_ON();
692
693 setup_phase_reader(iv);
694
695 int r = legic_write_byte(byte, address, addr_sz);
696
697 if((r != 0) || BUTTON_PRESS()) {
698 Dbprintf("operation aborted @ 0x%03.3x (%1d)", byte_index, r);
699 switch_off_tag_rwd();
700 LEDsoff();
701 return;
702 }
703
704 LEDsoff();
705 if ( MF_DBGLEVEL >= 1) DbpString("write successful");
706 }
707
708 int legic_select_card_iv(legic_card_select_t *p_card, uint8_t iv){
709
710 if ( p_card == NULL ) return 1;
711
712 p_card->tagtype = setup_phase_reader(iv);
713
714 switch(p_card->tagtype) {
715 case 0x0d:
716 p_card->cmdsize = 6;
717 p_card->addrsize = 5;
718 p_card->cardsize = 22;
719 break;
720 case 0x1d:
721 p_card->cmdsize = 9;
722 p_card->addrsize = 8;
723 p_card->cardsize = 256;
724 break;
725 case 0x3d:
726 p_card->cmdsize = 11;
727 p_card->addrsize = 10;
728 p_card->cardsize = 1024;
729 break;
730 default:
731 p_card->cmdsize = 0;
732 p_card->addrsize = 0;
733 p_card->cardsize = 0;
734 return 2;
735 }
736 return 0;
737 }
738 int legic_select_card(legic_card_select_t *p_card){
739 return legic_select_card_iv(p_card, 0x01);
740 }
741
742 void LegicRfInfo(void){
743
744 uint8_t buf[sizeof(legic_card_select_t)] = {0x00};
745 legic_card_select_t *card = (legic_card_select_t*) buf;
746
747 LegicCommonInit();
748
749 if ( legic_select_card(card) ) {
750 cmd_send(CMD_ACK,0,0,0,0,0);
751 goto OUT;
752 }
753
754 // read UID bytes
755 for ( uint8_t i = 0; i < sizeof(card->uid); ++i) {
756 int r = legic_read_byte(i, card->cmdsize);
757 if ( r == -1 ) {
758 cmd_send(CMD_ACK,0,0,0,0,0);
759 goto OUT;
760 }
761 card->uid[i] = r & 0xFF;
762 }
763
764 cmd_send(CMD_ACK, 1, 0, 0, buf, sizeof(legic_card_select_t));
765
766 OUT:
767 switch_off_tag_rwd();
768 LEDsoff();
769 }
770
771 /* Handle (whether to respond) a frame in tag mode
772 * Only called when simulating a tag.
773 */
774 static void frame_handle_tag(struct legic_frame const * const f)
775 {
776 uint8_t *BigBuf = BigBuf_get_addr();
777
778 /* First Part of Handshake (IV) */
779 if(f->bits == 7) {
780
781 LED_C_ON();
782
783 // Reset prng timer
784 ResetTimer(prng_timer);
785
786 legic_prng_init(f->data);
787 frame_send_tag(0x3d, 6, 1); /* 0x3d^0x26 = 0x1B */
788 legic_state = STATE_IV;
789 legic_read_count = 0;
790 legic_prng_bc = 0;
791 legic_prng_iv = f->data;
792
793
794 ResetTimer(timer);
795 WaitUS(280);
796 return;
797 }
798
799 /* 0x19==??? */
800 if(legic_state == STATE_IV) {
801 int local_key = get_key_stream(3, 6);
802 int xored = 0x39 ^ local_key;
803 if((f->bits == 6) && (f->data == xored)) {
804 legic_state = STATE_CON;
805
806 ResetTimer(timer);
807 WaitUS(200);
808 return;
809
810 } else {
811 legic_state = STATE_DISCON;
812 LED_C_OFF();
813 Dbprintf("iv: %02x frame: %02x key: %02x xored: %02x", legic_prng_iv, f->data, local_key, xored);
814 return;
815 }
816 }
817
818 /* Read */
819 if(f->bits == 11) {
820 if(legic_state == STATE_CON) {
821 int key = get_key_stream(2, 11); //legic_phase_drift, 11);
822 int addr = f->data ^ key; addr = addr >> 1;
823 int data = BigBuf[addr];
824 int hash = legic4Crc(LEGIC_READ, addr, data, 11) << 8;
825 BigBuf[OFFSET_LOG+legic_read_count] = (uint8_t)addr;
826 legic_read_count++;
827
828 //Dbprintf("Data:%03.3x, key:%03.3x, addr: %03.3x, read_c:%u", f->data, key, addr, read_c);
829 legic_prng_forward(legic_reqresp_drift);
830
831 frame_send_tag(hash | data, 12, 1);
832
833 ResetTimer(timer);
834 legic_prng_forward(2);
835 WaitUS(180);
836 return;
837 }
838 }
839
840 /* Write */
841 if(f->bits == 23) {
842 int key = get_key_stream(-1, 23); //legic_frame_drift, 23);
843 int addr = f->data ^ key; addr = addr >> 1; addr = addr & 0x3ff;
844 int data = f->data ^ key; data = data >> 11; data = data & 0xff;
845
846 /* write command */
847 legic_state = STATE_DISCON;
848 LED_C_OFF();
849 Dbprintf("write - addr: %x, data: %x", addr, data);
850 return;
851 }
852
853 if(legic_state != STATE_DISCON) {
854 Dbprintf("Unexpected: sz:%u, Data:%03.3x, State:%u, Count:%u", f->bits, f->data, legic_state, legic_read_count);
855 int i;
856 Dbprintf("IV: %03.3x", legic_prng_iv);
857 for(i = 0; i<legic_read_count; i++) {
858 Dbprintf("Read Nb: %u, Addr: %u", i, BigBuf[OFFSET_LOG+i]);
859 }
860
861 for(i = -1; i<legic_read_count; i++) {
862 uint32_t t;
863 t = BigBuf[OFFSET_LOG+256+i*4];
864 t |= BigBuf[OFFSET_LOG+256+i*4+1] << 8;
865 t |= BigBuf[OFFSET_LOG+256+i*4+2] <<16;
866 t |= BigBuf[OFFSET_LOG+256+i*4+3] <<24;
867
868 Dbprintf("Cycles: %u, Frame Length: %u, Time: %u",
869 BigBuf[OFFSET_LOG+128+i],
870 BigBuf[OFFSET_LOG+384+i],
871 t);
872 }
873 }
874 legic_state = STATE_DISCON;
875 legic_read_count = 0;
876 SpinDelay(10);
877 LED_C_OFF();
878 return;
879 }
880
881 /* Read bit by bit untill full frame is received
882 * Call to process frame end answer
883 */
884 static void emit(int bit) {
885
886 switch (bit) {
887 case 1:
888 frame_append_bit(&current_frame, 1);
889 break;
890 case 0:
891 frame_append_bit(&current_frame, 0);
892 break;
893 default:
894 if(current_frame.bits <= 4) {
895 frame_clean(&current_frame);
896 } else {
897 frame_handle_tag(&current_frame);
898 frame_clean(&current_frame);
899 }
900 WDT_HIT();
901 break;
902 }
903 }
904
905 void LegicRfSimulate(int phase, int frame, int reqresp)
906 {
907 /* ADC path high-frequency peak detector, FPGA in high-frequency simulator mode,
908 * modulation mode set to 212kHz subcarrier. We are getting the incoming raw
909 * envelope waveform on DIN and should send our response on DOUT.
910 *
911 * The LEGIC RF protocol is pulse-pause-encoding from reader to card, so we'll
912 * measure the time between two rising edges on DIN, and no encoding on the
913 * subcarrier from card to reader, so we'll just shift out our verbatim data
914 * on DOUT, 1 bit is 100us. The time from reader to card frame is still unclear,
915 * seems to be 300us-ish.
916 */
917
918 legic_phase_drift = phase;
919 legic_frame_drift = frame;
920 legic_reqresp_drift = reqresp;
921
922 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
923 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
924 FpgaSetupSsc();
925 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_212K);
926
927 /* Bitbang the receiver */
928 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
929 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
930
931 //setup_timer();
932 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
933
934 int old_level = 0;
935 int active = 0;
936 legic_state = STATE_DISCON;
937
938 LED_B_ON();
939 DbpString("Starting Legic emulator, press button to end");
940
941 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
942 int level = !!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
943 int time = timer->TC_CV;
944
945 if(level != old_level) {
946 if(level == 1) {
947 timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
948
949 if (FUZZ_EQUAL(time, RWD_TIME_1, RWD_TIME_FUZZ)) {
950 /* 1 bit */
951 emit(1);
952 active = 1;
953 LED_A_ON();
954 } else if (FUZZ_EQUAL(time, RWD_TIME_0, RWD_TIME_FUZZ)) {
955 /* 0 bit */
956 emit(0);
957 active = 1;
958 LED_A_ON();
959 } else if (active) {
960 /* invalid */
961 emit(-1);
962 active = 0;
963 LED_A_OFF();
964 }
965 }
966 }
967
968 /* Frame end */
969 if(time >= (RWD_TIME_1+RWD_TIME_FUZZ) && active) {
970 emit(-1);
971 active = 0;
972 LED_A_OFF();
973 }
974
975 if(time >= (20*RWD_TIME_1) && (timer->TC_SR & AT91C_TC_CLKSTA)) {
976 timer->TC_CCR = AT91C_TC_CLKDIS;
977 }
978
979 old_level = level;
980 WDT_HIT();
981 }
982 if ( MF_DBGLEVEL >= 1) DbpString("Stopped");
983 LEDsoff();
984 }
985
986 //-----------------------------------------------------------------------------
987 // Code up a string of octets at layer 2 (including CRC, we don't generate
988 // that here) so that they can be transmitted to the reader. Doesn't transmit
989 // them yet, just leaves them ready to send in ToSend[].
990 //-----------------------------------------------------------------------------
991 // static void CodeLegicAsTag(const uint8_t *cmd, int len)
992 // {
993 // int i;
994
995 // ToSendReset();
996
997 // // Transmit a burst of ones, as the initial thing that lets the
998 // // reader get phase sync. This (TR1) must be > 80/fs, per spec,
999 // // but tag that I've tried (a Paypass) exceeds that by a fair bit,
1000 // // so I will too.
1001 // for(i = 0; i < 20; i++) {
1002 // ToSendStuffBit(1);
1003 // ToSendStuffBit(1);
1004 // ToSendStuffBit(1);
1005 // ToSendStuffBit(1);
1006 // }
1007
1008 // // Send SOF.
1009 // for(i = 0; i < 10; i++) {
1010 // ToSendStuffBit(0);
1011 // ToSendStuffBit(0);
1012 // ToSendStuffBit(0);
1013 // ToSendStuffBit(0);
1014 // }
1015 // for(i = 0; i < 2; i++) {
1016 // ToSendStuffBit(1);
1017 // ToSendStuffBit(1);
1018 // ToSendStuffBit(1);
1019 // ToSendStuffBit(1);
1020 // }
1021
1022 // for(i = 0; i < len; i++) {
1023 // int j;
1024 // uint8_t b = cmd[i];
1025
1026 // // Start bit
1027 // ToSendStuffBit(0);
1028 // ToSendStuffBit(0);
1029 // ToSendStuffBit(0);
1030 // ToSendStuffBit(0);
1031
1032 // // Data bits
1033 // for(j = 0; j < 8; j++) {
1034 // if(b & 1) {
1035 // ToSendStuffBit(1);
1036 // ToSendStuffBit(1);
1037 // ToSendStuffBit(1);
1038 // ToSendStuffBit(1);
1039 // } else {
1040 // ToSendStuffBit(0);
1041 // ToSendStuffBit(0);
1042 // ToSendStuffBit(0);
1043 // ToSendStuffBit(0);
1044 // }
1045 // b >>= 1;
1046 // }
1047
1048 // // Stop bit
1049 // ToSendStuffBit(1);
1050 // ToSendStuffBit(1);
1051 // ToSendStuffBit(1);
1052 // ToSendStuffBit(1);
1053 // }
1054
1055 // // Send EOF.
1056 // for(i = 0; i < 10; i++) {
1057 // ToSendStuffBit(0);
1058 // ToSendStuffBit(0);
1059 // ToSendStuffBit(0);
1060 // ToSendStuffBit(0);
1061 // }
1062 // for(i = 0; i < 2; i++) {
1063 // ToSendStuffBit(1);
1064 // ToSendStuffBit(1);
1065 // ToSendStuffBit(1);
1066 // ToSendStuffBit(1);
1067 // }
1068
1069 // // Convert from last byte pos to length
1070 // ToSendMax++;
1071 // }
1072
1073 //-----------------------------------------------------------------------------
1074 // The software UART that receives commands from the reader, and its state
1075 // variables.
1076 //-----------------------------------------------------------------------------
1077 /*
1078 static struct {
1079 enum {
1080 STATE_UNSYNCD,
1081 STATE_GOT_FALLING_EDGE_OF_SOF,
1082 STATE_AWAITING_START_BIT,
1083 STATE_RECEIVING_DATA
1084 } state;
1085 uint16_t shiftReg;
1086 int bitCnt;
1087 int byteCnt;
1088 int byteCntMax;
1089 int posCnt;
1090 uint8_t *output;
1091 } Uart;
1092 */
1093 /* Receive & handle a bit coming from the reader.
1094 *
1095 * This function is called 4 times per bit (every 2 subcarrier cycles).
1096 * Subcarrier frequency fs is 212kHz, 1/fs = 4,72us, i.e. function is called every 9,44us
1097 *
1098 * LED handling:
1099 * LED A -> ON once we have received the SOF and are expecting the rest.
1100 * LED A -> OFF once we have received EOF or are in error state or unsynced
1101 *
1102 * Returns: true if we received a EOF
1103 * false if we are still waiting for some more
1104 */
1105 // static RAMFUNC int HandleLegicUartBit(uint8_t bit)
1106 // {
1107 // switch(Uart.state) {
1108 // case STATE_UNSYNCD:
1109 // if(!bit) {
1110 // // we went low, so this could be the beginning of an SOF
1111 // Uart.state = STATE_GOT_FALLING_EDGE_OF_SOF;
1112 // Uart.posCnt = 0;
1113 // Uart.bitCnt = 0;
1114 // }
1115 // break;
1116
1117 // case STATE_GOT_FALLING_EDGE_OF_SOF:
1118 // Uart.posCnt++;
1119 // if(Uart.posCnt == 2) { // sample every 4 1/fs in the middle of a bit
1120 // if(bit) {
1121 // if(Uart.bitCnt > 9) {
1122 // // we've seen enough consecutive
1123 // // zeros that it's a valid SOF
1124 // Uart.posCnt = 0;
1125 // Uart.byteCnt = 0;
1126 // Uart.state = STATE_AWAITING_START_BIT;
1127 // LED_A_ON(); // Indicate we got a valid SOF
1128 // } else {
1129 // // didn't stay down long enough
1130 // // before going high, error
1131 // Uart.state = STATE_UNSYNCD;
1132 // }
1133 // } else {
1134 // // do nothing, keep waiting
1135 // }
1136 // Uart.bitCnt++;
1137 // }
1138 // if(Uart.posCnt >= 4) Uart.posCnt = 0;
1139 // if(Uart.bitCnt > 12) {
1140 // // Give up if we see too many zeros without
1141 // // a one, too.
1142 // LED_A_OFF();
1143 // Uart.state = STATE_UNSYNCD;
1144 // }
1145 // break;
1146
1147 // case STATE_AWAITING_START_BIT:
1148 // Uart.posCnt++;
1149 // if(bit) {
1150 // if(Uart.posCnt > 50/2) { // max 57us between characters = 49 1/fs, max 3 etus after low phase of SOF = 24 1/fs
1151 // // stayed high for too long between
1152 // // characters, error
1153 // Uart.state = STATE_UNSYNCD;
1154 // }
1155 // } else {
1156 // // falling edge, this starts the data byte
1157 // Uart.posCnt = 0;
1158 // Uart.bitCnt = 0;
1159 // Uart.shiftReg = 0;
1160 // Uart.state = STATE_RECEIVING_DATA;
1161 // }
1162 // break;
1163
1164 // case STATE_RECEIVING_DATA:
1165 // Uart.posCnt++;
1166 // if(Uart.posCnt == 2) {
1167 // // time to sample a bit
1168 // Uart.shiftReg >>= 1;
1169 // if(bit) {
1170 // Uart.shiftReg |= 0x200;
1171 // }
1172 // Uart.bitCnt++;
1173 // }
1174 // if(Uart.posCnt >= 4) {
1175 // Uart.posCnt = 0;
1176 // }
1177 // if(Uart.bitCnt == 10) {
1178 // if((Uart.shiftReg & 0x200) && !(Uart.shiftReg & 0x001))
1179 // {
1180 // // this is a data byte, with correct
1181 // // start and stop bits
1182 // Uart.output[Uart.byteCnt] = (Uart.shiftReg >> 1) & 0xff;
1183 // Uart.byteCnt++;
1184
1185 // if(Uart.byteCnt >= Uart.byteCntMax) {
1186 // // Buffer overflowed, give up
1187 // LED_A_OFF();
1188 // Uart.state = STATE_UNSYNCD;
1189 // } else {
1190 // // so get the next byte now
1191 // Uart.posCnt = 0;
1192 // Uart.state = STATE_AWAITING_START_BIT;
1193 // }
1194 // } else if (Uart.shiftReg == 0x000) {
1195 // // this is an EOF byte
1196 // LED_A_OFF(); // Finished receiving
1197 // Uart.state = STATE_UNSYNCD;
1198 // if (Uart.byteCnt != 0) {
1199 // return TRUE;
1200 // }
1201 // } else {
1202 // // this is an error
1203 // LED_A_OFF();
1204 // Uart.state = STATE_UNSYNCD;
1205 // }
1206 // }
1207 // break;
1208
1209 // default:
1210 // LED_A_OFF();
1211 // Uart.state = STATE_UNSYNCD;
1212 // break;
1213 // }
1214
1215 // return FALSE;
1216 // }
1217 /*
1218
1219 static void UartReset() {
1220 Uart.byteCntMax = 3;
1221 Uart.state = STATE_UNSYNCD;
1222 Uart.byteCnt = 0;
1223 Uart.bitCnt = 0;
1224 Uart.posCnt = 0;
1225 memset(Uart.output, 0x00, 3);
1226 }
1227 */
1228 // static void UartInit(uint8_t *data) {
1229 // Uart.output = data;
1230 // UartReset();
1231 // }
1232
1233 //=============================================================================
1234 // An LEGIC reader. We take layer two commands, code them
1235 // appropriately, and then send them to the tag. We then listen for the
1236 // tag's response, which we leave in the buffer to be demodulated on the
1237 // PC side.
1238 //=============================================================================
1239 /*
1240 static struct {
1241 enum {
1242 DEMOD_UNSYNCD,
1243 DEMOD_PHASE_REF_TRAINING,
1244 DEMOD_AWAITING_FALLING_EDGE_OF_SOF,
1245 DEMOD_GOT_FALLING_EDGE_OF_SOF,
1246 DEMOD_AWAITING_START_BIT,
1247 DEMOD_RECEIVING_DATA
1248 } state;
1249 int bitCount;
1250 int posCount;
1251 int thisBit;
1252 uint16_t shiftReg;
1253 uint8_t *output;
1254 int len;
1255 int sumI;
1256 int sumQ;
1257 } Demod;
1258 */
1259 /*
1260 * Handles reception of a bit from the tag
1261 *
1262 * This function is called 2 times per bit (every 4 subcarrier cycles).
1263 * Subcarrier frequency fs is 212kHz, 1/fs = 4,72us, i.e. function is called every 9,44us
1264 *
1265 * LED handling:
1266 * LED C -> ON once we have received the SOF and are expecting the rest.
1267 * LED C -> OFF once we have received EOF or are unsynced
1268 *
1269 * Returns: true if we received a EOF
1270 * false if we are still waiting for some more
1271 *
1272 */
1273
1274 /*
1275 static RAMFUNC int HandleLegicSamplesDemod(int ci, int cq)
1276 {
1277 int v = 0;
1278 int ai = ABS(ci);
1279 int aq = ABS(cq);
1280 int halfci = (ai >> 1);
1281 int halfcq = (aq >> 1);
1282
1283 switch(Demod.state) {
1284 case DEMOD_UNSYNCD:
1285
1286 CHECK_FOR_SUBCARRIER()
1287
1288 if(v > SUBCARRIER_DETECT_THRESHOLD) { // subcarrier detected
1289 Demod.state = DEMOD_PHASE_REF_TRAINING;
1290 Demod.sumI = ci;
1291 Demod.sumQ = cq;
1292 Demod.posCount = 1;
1293 }
1294 break;
1295
1296 case DEMOD_PHASE_REF_TRAINING:
1297 if(Demod.posCount < 8) {
1298
1299 CHECK_FOR_SUBCARRIER()
1300
1301 if (v > SUBCARRIER_DETECT_THRESHOLD) {
1302 // set the reference phase (will code a logic '1') by averaging over 32 1/fs.
1303 // note: synchronization time > 80 1/fs
1304 Demod.sumI += ci;
1305 Demod.sumQ += cq;
1306 ++Demod.posCount;
1307 } else {
1308 // subcarrier lost
1309 Demod.state = DEMOD_UNSYNCD;
1310 }
1311 } else {
1312 Demod.state = DEMOD_AWAITING_FALLING_EDGE_OF_SOF;
1313 }
1314 break;
1315
1316 case DEMOD_AWAITING_FALLING_EDGE_OF_SOF:
1317
1318 MAKE_SOFT_DECISION()
1319
1320 //Dbprintf("ICE: %d %d %d %d %d", v, Demod.sumI, Demod.sumQ, ci, cq );
1321 // logic '0' detected
1322 if (v <= 0) {
1323
1324 Demod.state = DEMOD_GOT_FALLING_EDGE_OF_SOF;
1325
1326 // start of SOF sequence
1327 Demod.posCount = 0;
1328 } else {
1329 // maximum length of TR1 = 200 1/fs
1330 if(Demod.posCount > 25*2) Demod.state = DEMOD_UNSYNCD;
1331 }
1332 ++Demod.posCount;
1333 break;
1334
1335 case DEMOD_GOT_FALLING_EDGE_OF_SOF:
1336 ++Demod.posCount;
1337
1338 MAKE_SOFT_DECISION()
1339
1340 if(v > 0) {
1341 // low phase of SOF too short (< 9 etu). Note: spec is >= 10, but FPGA tends to "smear" edges
1342 if(Demod.posCount < 10*2) {
1343 Demod.state = DEMOD_UNSYNCD;
1344 } else {
1345 LED_C_ON(); // Got SOF
1346 Demod.state = DEMOD_AWAITING_START_BIT;
1347 Demod.posCount = 0;
1348 Demod.len = 0;
1349 }
1350 } else {
1351 // low phase of SOF too long (> 12 etu)
1352 if(Demod.posCount > 13*2) {
1353 Demod.state = DEMOD_UNSYNCD;
1354 LED_C_OFF();
1355 }
1356 }
1357 break;
1358
1359 case DEMOD_AWAITING_START_BIT:
1360 ++Demod.posCount;
1361
1362 MAKE_SOFT_DECISION()
1363
1364 if(v > 0) {
1365 // max 19us between characters = 16 1/fs, max 3 etu after low phase of SOF = 24 1/fs
1366 if(Demod.posCount > 3*2) {
1367 Demod.state = DEMOD_UNSYNCD;
1368 LED_C_OFF();
1369 }
1370 } else {
1371 // start bit detected
1372 Demod.bitCount = 0;
1373 Demod.posCount = 1; // this was the first half
1374 Demod.thisBit = v;
1375 Demod.shiftReg = 0;
1376 Demod.state = DEMOD_RECEIVING_DATA;
1377 }
1378 break;
1379
1380 case DEMOD_RECEIVING_DATA:
1381
1382 MAKE_SOFT_DECISION()
1383
1384 if(Demod.posCount == 0) {
1385 // first half of bit
1386 Demod.thisBit = v;
1387 Demod.posCount = 1;
1388 } else {
1389 // second half of bit
1390 Demod.thisBit += v;
1391 Demod.shiftReg >>= 1;
1392 // logic '1'
1393 if(Demod.thisBit > 0)
1394 Demod.shiftReg |= 0x200;
1395
1396 ++Demod.bitCount;
1397
1398 if(Demod.bitCount == 10) {
1399
1400 uint16_t s = Demod.shiftReg;
1401
1402 if((s & 0x200) && !(s & 0x001)) {
1403 // stop bit == '1', start bit == '0'
1404 uint8_t b = (s >> 1);
1405 Demod.output[Demod.len] = b;
1406 ++Demod.len;
1407 Demod.state = DEMOD_AWAITING_START_BIT;
1408 } else {
1409 Demod.state = DEMOD_UNSYNCD;
1410 LED_C_OFF();
1411
1412 if(s == 0x000) {
1413 // This is EOF (start, stop and all data bits == '0'
1414 return TRUE;
1415 }
1416 }
1417 }
1418 Demod.posCount = 0;
1419 }
1420 break;
1421
1422 default:
1423 Demod.state = DEMOD_UNSYNCD;
1424 LED_C_OFF();
1425 break;
1426 }
1427 return FALSE;
1428 }
1429 */
1430 /*
1431 // Clear out the state of the "UART" that receives from the tag.
1432 static void DemodReset() {
1433 Demod.len = 0;
1434 Demod.state = DEMOD_UNSYNCD;
1435 Demod.posCount = 0;
1436 Demod.sumI = 0;
1437 Demod.sumQ = 0;
1438 Demod.bitCount = 0;
1439 Demod.thisBit = 0;
1440 Demod.shiftReg = 0;
1441 memset(Demod.output, 0x00, 3);
1442 }
1443
1444 static void DemodInit(uint8_t *data) {
1445 Demod.output = data;
1446 DemodReset();
1447 }
1448 */
1449
1450 /*
1451 * Demodulate the samples we received from the tag, also log to tracebuffer
1452 * quiet: set to 'TRUE' to disable debug output
1453 */
1454
1455 /*
1456 #define LEGIC_DMA_BUFFER_SIZE 256
1457
1458 static void GetSamplesForLegicDemod(int n, bool quiet)
1459 {
1460 int max = 0;
1461 bool gotFrame = FALSE;
1462 int lastRxCounter = LEGIC_DMA_BUFFER_SIZE;
1463 int ci, cq, samples = 0;
1464
1465 BigBuf_free();
1466
1467 // And put the FPGA in the appropriate mode
1468 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_QUARTER_FREQ);
1469
1470 // The response (tag -> reader) that we're receiving.
1471 // Set up the demodulator for tag -> reader responses.
1472 DemodInit(BigBuf_malloc(MAX_FRAME_SIZE));
1473
1474 // The DMA buffer, used to stream samples from the FPGA
1475 int8_t *dmaBuf = (int8_t*) BigBuf_malloc(LEGIC_DMA_BUFFER_SIZE);
1476 int8_t *upTo = dmaBuf;
1477
1478 // Setup and start DMA.
1479 if ( !FpgaSetupSscDma((uint8_t*) dmaBuf, LEGIC_DMA_BUFFER_SIZE) ){
1480 if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting");
1481 return;
1482 }
1483
1484 // Signal field is ON with the appropriate LED:
1485 LED_D_ON();
1486 for(;;) {
1487 int behindBy = lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR;
1488 if(behindBy > max) max = behindBy;
1489
1490 while(((lastRxCounter-AT91C_BASE_PDC_SSC->PDC_RCR) & (LEGIC_DMA_BUFFER_SIZE-1)) > 2) {
1491 ci = upTo[0];
1492 cq = upTo[1];
1493 upTo += 2;
1494 if(upTo >= dmaBuf + LEGIC_DMA_BUFFER_SIZE) {
1495 upTo = dmaBuf;
1496 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo;
1497 AT91C_BASE_PDC_SSC->PDC_RNCR = LEGIC_DMA_BUFFER_SIZE;
1498 }
1499 lastRxCounter -= 2;
1500 if(lastRxCounter <= 0)
1501 lastRxCounter = LEGIC_DMA_BUFFER_SIZE;
1502
1503 samples += 2;
1504
1505 gotFrame = HandleLegicSamplesDemod(ci , cq );
1506 if ( gotFrame )
1507 break;
1508 }
1509
1510 if(samples > n || gotFrame)
1511 break;
1512 }
1513
1514 FpgaDisableSscDma();
1515
1516 if (!quiet && Demod.len == 0) {
1517 Dbprintf("max behindby = %d, samples = %d, gotFrame = %d, Demod.len = %d, Demod.sumI = %d, Demod.sumQ = %d",
1518 max,
1519 samples,
1520 gotFrame,
1521 Demod.len,
1522 Demod.sumI,
1523 Demod.sumQ
1524 );
1525 }
1526
1527 //Tracing
1528 if (Demod.len > 0) {
1529 uint8_t parity[MAX_PARITY_SIZE] = {0x00};
1530 LogTrace(Demod.output, Demod.len, 0, 0, parity, FALSE);
1531 }
1532 }
1533
1534 */
1535
1536 //-----------------------------------------------------------------------------
1537 // Transmit the command (to the tag) that was placed in ToSend[].
1538 //-----------------------------------------------------------------------------
1539 /*
1540 static void TransmitForLegic(void)
1541 {
1542 int c;
1543
1544 FpgaSetupSsc();
1545
1546 while(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY))
1547 AT91C_BASE_SSC->SSC_THR = 0xff;
1548
1549 // Signal field is ON with the appropriate Red LED
1550 LED_D_ON();
1551
1552 // Signal we are transmitting with the Green LED
1553 LED_B_ON();
1554 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
1555
1556 for(c = 0; c < 10;) {
1557 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1558 AT91C_BASE_SSC->SSC_THR = 0xff;
1559 c++;
1560 }
1561 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1562 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
1563 (void)r;
1564 }
1565 WDT_HIT();
1566 }
1567
1568 c = 0;
1569 for(;;) {
1570 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1571 AT91C_BASE_SSC->SSC_THR = ToSend[c];
1572 legic_prng_forward(1); // forward the lfsr
1573 c++;
1574 if(c >= ToSendMax) {
1575 break;
1576 }
1577 }
1578 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1579 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
1580 (void)r;
1581 }
1582 WDT_HIT();
1583 }
1584 LED_B_OFF();
1585 }
1586 */
1587
1588 //-----------------------------------------------------------------------------
1589 // Code a layer 2 command (string of octets, including CRC) into ToSend[],
1590 // so that it is ready to transmit to the tag using TransmitForLegic().
1591 //-----------------------------------------------------------------------------
1592 /*
1593 static void CodeLegicBitsAsReader(const uint8_t *cmd, uint8_t cmdlen, int bits)
1594 {
1595 int i, j;
1596 uint8_t b;
1597
1598 ToSendReset();
1599
1600 // Send SOF
1601 for(i = 0; i < 7; i++)
1602 ToSendStuffBit(1);
1603
1604
1605 for(i = 0; i < cmdlen; i++) {
1606 // Start bit
1607 ToSendStuffBit(0);
1608
1609 // Data bits
1610 b = cmd[i];
1611 for(j = 0; j < bits; j++) {
1612 if(b & 1) {
1613 ToSendStuffBit(1);
1614 } else {
1615 ToSendStuffBit(0);
1616 }
1617 b >>= 1;
1618 }
1619 }
1620
1621 // Convert from last character reference to length
1622 ++ToSendMax;
1623 }
1624 */
1625 /**
1626 Convenience function to encode, transmit and trace Legic comms
1627 **/
1628 /*
1629 static void CodeAndTransmitLegicAsReader(const uint8_t *cmd, uint8_t cmdlen, int bits)
1630 {
1631 CodeLegicBitsAsReader(cmd, cmdlen, bits);
1632 TransmitForLegic();
1633 if (tracing) {
1634 uint8_t parity[1] = {0x00};
1635 LogTrace(cmd, cmdlen, 0, 0, parity, TRUE);
1636 }
1637 }
1638
1639 */
1640 // Set up LEGIC communication
1641 /*
1642 void ice_legic_setup() {
1643
1644 // standard things.
1645 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1646 BigBuf_free(); BigBuf_Clear_ext(false);
1647 clear_trace();
1648 set_tracing(TRUE);
1649 DemodReset();
1650 UartReset();
1651
1652 // Set up the synchronous serial port
1653 FpgaSetupSsc();
1654
1655 // connect Demodulated Signal to ADC:
1656 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1657
1658 // Signal field is on with the appropriate LED
1659 LED_D_ON();
1660 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
1661 SpinDelay(20);
1662 // Start the timer
1663 //StartCountSspClk();
1664
1665 // initalize CRC
1666 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
1667
1668 // initalize prng
1669 legic_prng_init(0);
1670 }
1671 */
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