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1 //-----------------------------------------------------------------------------
2 // The way that we connect things in low-frequency read mode. In this case
3 // we are generating the 134 kHz or 125 kHz carrier, and running the
4 // unmodulated carrier at that frequency. The A/D samples at that same rate,
5 // and the result is serialized.
6 //
7 // Jonathan Westhues, April 2006
8 //-----------------------------------------------------------------------------
9
10 module lo_read(
11 pck0, ck_1356meg, ck_1356megb,
12 pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
13 adc_d, adc_clk,
14 ssp_frame, ssp_din, ssp_dout, ssp_clk,
15 cross_hi, cross_lo,
16 dbg,
17 lo_is_125khz
18 );
19 input pck0, ck_1356meg, ck_1356megb;
20 output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
21 input [7:0] adc_d;
22 output adc_clk;
23 input ssp_dout;
24 output ssp_frame, ssp_din, ssp_clk;
25 input cross_hi, cross_lo;
26 output dbg;
27 input lo_is_125khz;
28
29 // The low-frequency RFID stuff. This is relatively simple, because most
30 // of the work happens on the ARM, and we just pass samples through. The
31 // PCK0 must be divided down to generate the A/D clock, and from there by
32 // a factor of 8 to generate the carrier (that we apply to the coil drivers).
33 //
34 // This is also where we decode the received synchronous serial port words,
35 // to determine how to drive the output enables.
36
37 // PCK0 will run at (PLL clock) / 4, or 24 MHz. That means that we can do
38 // 125 kHz by dividing by a further factor of (8*12*2), or ~134 kHz by
39 // dividing by a factor of (8*11*2) (for 136 kHz, ~2% error, tolerable).
40
41 reg [3:0] pck_divider;
42 reg clk_lo;
43
44 always @(posedge pck0)
45 begin
46 if(lo_is_125khz)
47 begin
48 if(pck_divider == 4'd11)
49 begin
50 pck_divider <= 4'd0;
51 clk_lo = !clk_lo;
52 end
53 else
54 pck_divider <= pck_divider + 1;
55 end
56 else
57 begin
58 if(pck_divider == 4'd10)
59 begin
60 pck_divider <= 4'd0;
61 clk_lo = !clk_lo;
62 end
63 else
64 pck_divider <= pck_divider + 1;
65 end
66 end
67
68 reg [2:0] carrier_divider_lo;
69
70 always @(posedge clk_lo)
71 begin
72 carrier_divider_lo <= carrier_divider_lo + 1;
73 end
74
75 assign pwr_lo = carrier_divider_lo[2];
76
77 // This serializes the values returned from the A/D, and sends them out
78 // over the SSP.
79
80 reg [7:0] to_arm_shiftreg;
81
82 always @(posedge clk_lo)
83 begin
84 if(carrier_divider_lo == 3'b000)
85 to_arm_shiftreg <= adc_d;
86 else
87 to_arm_shiftreg[7:1] <= to_arm_shiftreg[6:0];
88 end
89
90 assign ssp_clk = clk_lo;
91 assign ssp_frame = (carrier_divider_lo == 3'b001);
92 assign ssp_din = to_arm_shiftreg[7];
93
94 // The ADC converts on the falling edge, and our serializer loads when
95 // carrier_divider_lo == 3'b000.
96 assign adc_clk = ~carrier_divider_lo[2];
97
98 assign pwr_hi = 1'b0;
99
100 assign dbg = adc_clk;
101
102 endmodule
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