]> cvs.zerfleddert.de Git - proxmark3-svn/blob - armsrc/fpgaloader.c
a719f5edf2fa5f9906f54a067ac57fcf513cbd1f
[proxmark3-svn] / armsrc / fpgaloader.c
1 //-----------------------------------------------------------------------------
2 // Jonathan Westhues, April 2006
3 //
4 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
5 // at your option, any later version. See the LICENSE.txt file for the text of
6 // the license.
7 //-----------------------------------------------------------------------------
8 // Routines to load the FPGA image, and then to configure the FPGA's major
9 // mode once it is configured.
10 //-----------------------------------------------------------------------------
11
12 #include "proxmark3.h"
13 #include "apps.h"
14 #include "util.h"
15 #include "string.h"
16
17 //-----------------------------------------------------------------------------
18 // Set up the Serial Peripheral Interface as master
19 // Used to write the FPGA config word
20 // May also be used to write to other SPI attached devices like an LCD
21 //-----------------------------------------------------------------------------
22 void SetupSpi(int mode)
23 {
24 // PA10 -> SPI_NCS2 chip select (LCD)
25 // PA11 -> SPI_NCS0 chip select (FPGA)
26 // PA12 -> SPI_MISO Master-In Slave-Out
27 // PA13 -> SPI_MOSI Master-Out Slave-In
28 // PA14 -> SPI_SPCK Serial Clock
29
30 // Disable PIO control of the following pins, allows use by the SPI peripheral
31 AT91C_BASE_PIOA->PIO_PDR =
32 GPIO_NCS0 |
33 GPIO_NCS2 |
34 GPIO_MISO |
35 GPIO_MOSI |
36 GPIO_SPCK;
37
38 AT91C_BASE_PIOA->PIO_ASR =
39 GPIO_NCS0 |
40 GPIO_MISO |
41 GPIO_MOSI |
42 GPIO_SPCK;
43
44 AT91C_BASE_PIOA->PIO_BSR = GPIO_NCS2;
45
46 //enable the SPI Peripheral clock
47 AT91C_BASE_PMC->PMC_PCER = (1<<AT91C_ID_SPI);
48 // Enable SPI
49 AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN;
50
51 switch (mode) {
52 case SPI_FPGA_MODE:
53 AT91C_BASE_SPI->SPI_MR =
54 ( 0 << 24) | // Delay between chip selects (take default: 6 MCK periods)
55 (14 << 16) | // Peripheral Chip Select (selects FPGA SPI_NCS0 or PA11)
56 ( 0 << 7) | // Local Loopback Disabled
57 ( 1 << 4) | // Mode Fault Detection disabled
58 ( 0 << 2) | // Chip selects connected directly to peripheral
59 ( 0 << 1) | // Fixed Peripheral Select
60 ( 1 << 0); // Master Mode
61 AT91C_BASE_SPI->SPI_CSR[0] =
62 ( 1 << 24) | // Delay between Consecutive Transfers (32 MCK periods)
63 ( 1 << 16) | // Delay Before SPCK (1 MCK period)
64 ( 6 << 8) | // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud
65 ( 8 << 4) | // Bits per Transfer (16 bits)
66 ( 0 << 3) | // Chip Select inactive after transfer
67 ( 1 << 1) | // Clock Phase data captured on leading edge, changes on following edge
68 ( 0 << 0); // Clock Polarity inactive state is logic 0
69 break;
70 case SPI_LCD_MODE:
71 AT91C_BASE_SPI->SPI_MR =
72 ( 0 << 24) | // Delay between chip selects (take default: 6 MCK periods)
73 (11 << 16) | // Peripheral Chip Select (selects LCD SPI_NCS2 or PA10)
74 ( 0 << 7) | // Local Loopback Disabled
75 ( 1 << 4) | // Mode Fault Detection disabled
76 ( 0 << 2) | // Chip selects connected directly to peripheral
77 ( 0 << 1) | // Fixed Peripheral Select
78 ( 1 << 0); // Master Mode
79 AT91C_BASE_SPI->SPI_CSR[2] =
80 ( 1 << 24) | // Delay between Consecutive Transfers (32 MCK periods)
81 ( 1 << 16) | // Delay Before SPCK (1 MCK period)
82 ( 6 << 8) | // Serial Clock Baud Rate (baudrate = MCK/6 = 24Mhz/6 = 4M baud
83 ( 1 << 4) | // Bits per Transfer (9 bits)
84 ( 0 << 3) | // Chip Select inactive after transfer
85 ( 1 << 1) | // Clock Phase data captured on leading edge, changes on following edge
86 ( 0 << 0); // Clock Polarity inactive state is logic 0
87 break;
88 default: // Disable SPI
89 AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIDIS;
90 break;
91 }
92 }
93
94 //-----------------------------------------------------------------------------
95 // Set up the synchronous serial port, with the one set of options that we
96 // always use when we are talking to the FPGA. Both RX and TX are enabled.
97 //-----------------------------------------------------------------------------
98 void FpgaSetupSsc(void)
99 {
100 // First configure the GPIOs, and get ourselves a clock.
101 AT91C_BASE_PIOA->PIO_ASR =
102 GPIO_SSC_FRAME |
103 GPIO_SSC_DIN |
104 GPIO_SSC_DOUT |
105 GPIO_SSC_CLK;
106 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
107
108 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_SSC);
109
110 // Now set up the SSC proper, starting from a known state.
111 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
112
113 // RX clock comes from TX clock, RX starts when TX starts, data changes
114 // on RX clock rising edge, sampled on falling edge
115 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(1) | SSC_CLOCK_MODE_START(1);
116
117 // 8 bits per transfer, no loopback, MSB first, 1 transfer per sync
118 // pulse, no output sync, start on positive-going edge of sync
119 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(8) |
120 AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);
121
122 // clock comes from TK pin, no clock output, outputs change on falling
123 // edge of TK, start on rising edge of TF
124 AT91C_BASE_SSC->SSC_TCMR = SSC_CLOCK_MODE_SELECT(2) |
125 SSC_CLOCK_MODE_START(5);
126
127 // tx framing is the same as the rx framing
128 AT91C_BASE_SSC->SSC_TFMR = AT91C_BASE_SSC->SSC_RFMR;
129
130 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
131 }
132
133 //-----------------------------------------------------------------------------
134 // Set up DMA to receive samples from the FPGA. We will use the PDC, with
135 // a single buffer as a circular buffer (so that we just chain back to
136 // ourselves, not to another buffer). The stuff to manipulate those buffers
137 // is in apps.h, because it should be inlined, for speed.
138 //-----------------------------------------------------------------------------
139 bool FpgaSetupSscDma(uint8_t *buf, int len)
140 {
141 if (buf == NULL) {
142 return false;
143 }
144
145 AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;
146 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) buf;
147 AT91C_BASE_PDC_SSC->PDC_RCR = len;
148 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) buf;
149 AT91C_BASE_PDC_SSC->PDC_RNCR = len;
150 AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN;
151
152 return true;
153 }
154
155 static void DownloadFPGA_byte(unsigned char w)
156 {
157 #define SEND_BIT(x) { if(w & (1<<x) ) HIGH(GPIO_FPGA_DIN); else LOW(GPIO_FPGA_DIN); HIGH(GPIO_FPGA_CCLK); LOW(GPIO_FPGA_CCLK); }
158 SEND_BIT(7);
159 SEND_BIT(6);
160 SEND_BIT(5);
161 SEND_BIT(4);
162 SEND_BIT(3);
163 SEND_BIT(2);
164 SEND_BIT(1);
165 SEND_BIT(0);
166 }
167
168 // Download the fpga image starting at FpgaImage and with length FpgaImageLen bytes
169 // If bytereversal is set: reverse the byte order in each 4-byte word
170 static void DownloadFPGA(const char *FpgaImage, int FpgaImageLen, int bytereversal)
171 {
172 int i=0;
173
174 AT91C_BASE_PIOA->PIO_OER = GPIO_FPGA_ON;
175 AT91C_BASE_PIOA->PIO_PER = GPIO_FPGA_ON;
176 HIGH(GPIO_FPGA_ON); // ensure everything is powered on
177
178 SpinDelay(50);
179
180 LED_D_ON();
181
182 // These pins are inputs
183 AT91C_BASE_PIOA->PIO_ODR =
184 GPIO_FPGA_NINIT |
185 GPIO_FPGA_DONE;
186 // PIO controls the following pins
187 AT91C_BASE_PIOA->PIO_PER =
188 GPIO_FPGA_NINIT |
189 GPIO_FPGA_DONE;
190 // Enable pull-ups
191 AT91C_BASE_PIOA->PIO_PPUER =
192 GPIO_FPGA_NINIT |
193 GPIO_FPGA_DONE;
194
195 // setup initial logic state
196 HIGH(GPIO_FPGA_NPROGRAM);
197 LOW(GPIO_FPGA_CCLK);
198 LOW(GPIO_FPGA_DIN);
199 // These pins are outputs
200 AT91C_BASE_PIOA->PIO_OER =
201 GPIO_FPGA_NPROGRAM |
202 GPIO_FPGA_CCLK |
203 GPIO_FPGA_DIN;
204
205 // enter FPGA configuration mode
206 LOW(GPIO_FPGA_NPROGRAM);
207 SpinDelay(50);
208 HIGH(GPIO_FPGA_NPROGRAM);
209
210 i=100000;
211 // wait for FPGA ready to accept data signal
212 while ((i) && ( !(AT91C_BASE_PIOA->PIO_PDSR & GPIO_FPGA_NINIT ) ) ) {
213 i--;
214 }
215
216 // crude error indicator, leave both red LEDs on and return
217 if (i==0){
218 LED_C_ON();
219 LED_D_ON();
220 return;
221 }
222
223 if(bytereversal) {
224 /* This is only supported for uint32_t aligned images */
225 if( ((int)FpgaImage % sizeof(uint32_t)) == 0 ) {
226 i=0;
227 while(FpgaImageLen-->0)
228 DownloadFPGA_byte(FpgaImage[(i++)^0x3]);
229 /* Explanation of the magic in the above line:
230 * i^0x3 inverts the lower two bits of the integer i, counting backwards
231 * for each 4 byte increment. The generated sequence of (i++)^3 is
232 * 3 2 1 0 7 6 5 4 11 10 9 8 15 14 13 12 etc. pp.
233 */
234 }
235 } else {
236 while(FpgaImageLen-->0)
237 DownloadFPGA_byte(*FpgaImage++);
238 }
239
240 // continue to clock FPGA until ready signal goes high
241 i=100000;
242 while ( (i--) && ( !(AT91C_BASE_PIOA->PIO_PDSR & GPIO_FPGA_DONE ) ) ) {
243 HIGH(GPIO_FPGA_CCLK);
244 LOW(GPIO_FPGA_CCLK);
245 }
246 // crude error indicator, leave both red LEDs on and return
247 if (i==0){
248 LED_C_ON();
249 LED_D_ON();
250 return;
251 }
252 LED_D_OFF();
253 }
254
255 static char *bitparse_headers_start;
256 static char *bitparse_bitstream_end;
257 static int bitparse_initialized;
258 /* Simple Xilinx .bit parser. The file starts with the fixed opaque byte sequence
259 * 00 09 0f f0 0f f0 0f f0 0f f0 00 00 01
260 * After that the format is 1 byte section type (ASCII character), 2 byte length
261 * (big endian), <length> bytes content. Except for section 'e' which has 4 bytes
262 * length.
263 */
264 static const char _bitparse_fixed_header[] = {0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, 0x00, 0x00, 0x01};
265 static int bitparse_init(void * start_address, void *end_address)
266 {
267 bitparse_initialized = 0;
268
269 if(memcmp(_bitparse_fixed_header, start_address, sizeof(_bitparse_fixed_header)) != 0) {
270 return 0; /* Not matched */
271 } else {
272 bitparse_headers_start= ((char*)start_address) + sizeof(_bitparse_fixed_header);
273 bitparse_bitstream_end= (char*)end_address;
274 bitparse_initialized = 1;
275 return 1;
276 }
277 }
278
279 int bitparse_find_section(char section_name, char **section_start, unsigned int *section_length)
280 {
281 char *pos = bitparse_headers_start;
282 int result = 0;
283
284 if(!bitparse_initialized) return 0;
285
286 while(pos < bitparse_bitstream_end) {
287 char current_name = *pos++;
288 unsigned int current_length = 0;
289 if(current_name < 'a' || current_name > 'e') {
290 /* Strange section name, abort */
291 break;
292 }
293 current_length = 0;
294 switch(current_name) {
295 case 'e':
296 /* Four byte length field */
297 current_length += (*pos++) << 24;
298 current_length += (*pos++) << 16;
299 default: /* Fall through, two byte length field */
300 current_length += (*pos++) << 8;
301 current_length += (*pos++) << 0;
302 }
303
304 if(current_name != 'e' && current_length > 255) {
305 /* Maybe a parse error */
306 break;
307 }
308
309 if(current_name == section_name) {
310 /* Found it */
311 *section_start = pos;
312 *section_length = current_length;
313 result = 1;
314 break;
315 }
316
317 pos += current_length; /* Skip section */
318 }
319
320 return result;
321 }
322
323 //-----------------------------------------------------------------------------
324 // Find out which FPGA image format is stored in flash, then call DownloadFPGA
325 // with the right parameters to download the image
326 //-----------------------------------------------------------------------------
327 extern char _binary_fpga_bit_start, _binary_fpga_bit_end;
328 void FpgaDownloadAndGo(void)
329 {
330 /* Check for the new flash image format: Should have the .bit file at &_binary_fpga_bit_start
331 */
332 if(bitparse_init(&_binary_fpga_bit_start, &_binary_fpga_bit_end)) {
333 /* Successfully initialized the .bit parser. Find the 'e' section and
334 * send its contents to the FPGA.
335 */
336 char *bitstream_start;
337 unsigned int bitstream_length;
338 if(bitparse_find_section('e', &bitstream_start, &bitstream_length)) {
339 DownloadFPGA(bitstream_start, bitstream_length, 0);
340
341 return; /* All done */
342 }
343 }
344
345 /* Fallback for the old flash image format: Check for the magic marker 0xFFFFFFFF
346 * 0xAA995566 at address 0x102000. This is raw bitstream with a size of 336,768 bits
347 * = 10,524 uint32_t, stored as uint32_t e.g. little-endian in memory, but each DWORD
348 * is still to be transmitted in MSBit first order. Set the invert flag to indicate
349 * that the DownloadFPGA function should invert every 4 byte sequence when doing
350 * the bytewise download.
351 */
352 if( *(uint32_t*)0x102000 == 0xFFFFFFFF && *(uint32_t*)0x102004 == 0xAA995566 )
353 DownloadFPGA((char*)0x102000, 10524*4, 1);
354 }
355
356 void FpgaGatherVersion(char *dst, int len)
357 {
358 char *fpga_info;
359 unsigned int fpga_info_len;
360 dst[0] = 0;
361 if(!bitparse_find_section('e', &fpga_info, &fpga_info_len)) {
362 strncat(dst, "FPGA image: legacy image without version information", len-1);
363 } else {
364 strncat(dst, "FPGA image built", len-1);
365 /* USB packets only have 48 bytes data payload, so be terse */
366 #if 0
367 if(bitparse_find_section('a', &fpga_info, &fpga_info_len) && fpga_info[fpga_info_len-1] == 0 ) {
368 strncat(dst, " from ", len-1);
369 strncat(dst, fpga_info, len-1);
370 }
371 if(bitparse_find_section('b', &fpga_info, &fpga_info_len) && fpga_info[fpga_info_len-1] == 0 ) {
372 strncat(dst, " for ", len-1);
373 strncat(dst, fpga_info, len-1);
374 }
375 #endif
376 if(bitparse_find_section('c', &fpga_info, &fpga_info_len) && fpga_info[fpga_info_len-1] == 0 ) {
377 strncat(dst, " on ", len-1);
378 strncat(dst, fpga_info, len-1);
379 }
380 if(bitparse_find_section('d', &fpga_info, &fpga_info_len) && fpga_info[fpga_info_len-1] == 0 ) {
381 strncat(dst, " at ", len-1);
382 strncat(dst, fpga_info, len-1);
383 }
384 }
385 }
386
387 //-----------------------------------------------------------------------------
388 // Send a 16 bit command/data pair to the FPGA.
389 // The bit format is: C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
390 // where C is the 4 bit command and D is the 12 bit data
391 //-----------------------------------------------------------------------------
392 void FpgaSendCommand(uint16_t cmd, uint16_t v)
393 {
394 SetupSpi(SPI_FPGA_MODE);
395 while ((AT91C_BASE_SPI->SPI_SR & AT91C_SPI_TXEMPTY) == 0); // wait for the transfer to complete
396 AT91C_BASE_SPI->SPI_TDR = AT91C_SPI_LASTXFER | cmd | v; // send the data
397 }
398 //-----------------------------------------------------------------------------
399 // Write the FPGA setup word (that determines what mode the logic is in, read
400 // vs. clone vs. etc.). This is now a special case of FpgaSendCommand() to
401 // avoid changing this function's occurence everywhere in the source code.
402 //-----------------------------------------------------------------------------
403 void FpgaWriteConfWord(uint8_t v)
404 {
405 FpgaSendCommand(FPGA_CMD_SET_CONFREG, v);
406 }
407
408 //-----------------------------------------------------------------------------
409 // Set up the CMOS switches that mux the ADC: four switches, independently
410 // closable, but should only close one at a time. Not an FPGA thing, but
411 // the samples from the ADC always flow through the FPGA.
412 //-----------------------------------------------------------------------------
413 void SetAdcMuxFor(uint32_t whichGpio)
414 {
415 AT91C_BASE_PIOA->PIO_OER =
416 GPIO_MUXSEL_HIPKD |
417 GPIO_MUXSEL_LOPKD |
418 GPIO_MUXSEL_LORAW |
419 GPIO_MUXSEL_HIRAW;
420
421 AT91C_BASE_PIOA->PIO_PER =
422 GPIO_MUXSEL_HIPKD |
423 GPIO_MUXSEL_LOPKD |
424 GPIO_MUXSEL_LORAW |
425 GPIO_MUXSEL_HIRAW;
426
427 LOW(GPIO_MUXSEL_HIPKD);
428 LOW(GPIO_MUXSEL_HIRAW);
429 LOW(GPIO_MUXSEL_LORAW);
430 LOW(GPIO_MUXSEL_LOPKD);
431
432 HIGH(whichGpio);
433 }
Impressum, Datenschutz