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1 //-----------------------------------------------------------------------------
2 // Merlok - June 2011, 2012
3 // Gerhard de Koning Gans - May 2008
4 // Hagen Fritsch - June 2010
5 //
6 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
7 // at your option, any later version. See the LICENSE.txt file for the text of
8 // the license.
9 //-----------------------------------------------------------------------------
10 // Routines to support ISO 14443 type A.
11 //-----------------------------------------------------------------------------
12
13 #include "proxmark3.h"
14 #include "apps.h"
15 #include "util.h"
16 #include "string.h"
17 #include "cmd.h"
18 #include "iso14443crc.h"
19 #include "iso14443a.h"
20 #include "crapto1.h"
21 #include "mifareutil.h"
22 #include "BigBuf.h"
23 static uint32_t iso14a_timeout;
24 int rsamples = 0;
25 uint8_t trigger = 0;
26 // the block number for the ISO14443-4 PCB
27 static uint8_t iso14_pcb_blocknum = 0;
28
29 //
30 // ISO14443 timing:
31 //
32 // minimum time between the start bits of consecutive transfers from reader to tag: 7000 carrier (13.56Mhz) cycles
33 #define REQUEST_GUARD_TIME (7000/16 + 1)
34 // minimum time between last modulation of tag and next start bit from reader to tag: 1172 carrier cycles
35 #define FRAME_DELAY_TIME_PICC_TO_PCD (1172/16 + 1)
36 // bool LastCommandWasRequest = FALSE;
37
38 //
39 // Total delays including SSC-Transfers between ARM and FPGA. These are in carrier clock cycles (1/13,56MHz)
40 //
41 // When the PM acts as reader and is receiving tag data, it takes
42 // 3 ticks delay in the AD converter
43 // 16 ticks until the modulation detector completes and sets curbit
44 // 8 ticks until bit_to_arm is assigned from curbit
45 // 8*16 ticks for the transfer from FPGA to ARM
46 // 4*16 ticks until we measure the time
47 // - 8*16 ticks because we measure the time of the previous transfer
48 #define DELAY_AIR2ARM_AS_READER (3 + 16 + 8 + 8*16 + 4*16 - 8*16)
49
50 // When the PM acts as a reader and is sending, it takes
51 // 4*16 ticks until we can write data to the sending hold register
52 // 8*16 ticks until the SHR is transferred to the Sending Shift Register
53 // 8 ticks until the first transfer starts
54 // 8 ticks later the FPGA samples the data
55 // 1 tick to assign mod_sig_coil
56 #define DELAY_ARM2AIR_AS_READER (4*16 + 8*16 + 8 + 8 + 1)
57
58 // When the PM acts as tag and is receiving it takes
59 // 2 ticks delay in the RF part (for the first falling edge),
60 // 3 ticks for the A/D conversion,
61 // 8 ticks on average until the start of the SSC transfer,
62 // 8 ticks until the SSC samples the first data
63 // 7*16 ticks to complete the transfer from FPGA to ARM
64 // 8 ticks until the next ssp_clk rising edge
65 // 4*16 ticks until we measure the time
66 // - 8*16 ticks because we measure the time of the previous transfer
67 #define DELAY_AIR2ARM_AS_TAG (2 + 3 + 8 + 8 + 7*16 + 8 + 4*16 - 8*16)
68
69 // The FPGA will report its internal sending delay in
70 uint16_t FpgaSendQueueDelay;
71 // the 5 first bits are the number of bits buffered in mod_sig_buf
72 // the last three bits are the remaining ticks/2 after the mod_sig_buf shift
73 #define DELAY_FPGA_QUEUE (FpgaSendQueueDelay<<1)
74
75 // When the PM acts as tag and is sending, it takes
76 // 4*16 ticks until we can write data to the sending hold register
77 // 8*16 ticks until the SHR is transferred to the Sending Shift Register
78 // 8 ticks until the first transfer starts
79 // 8 ticks later the FPGA samples the data
80 // + a varying number of ticks in the FPGA Delay Queue (mod_sig_buf)
81 // + 1 tick to assign mod_sig_coil
82 #define DELAY_ARM2AIR_AS_TAG (4*16 + 8*16 + 8 + 8 + DELAY_FPGA_QUEUE + 1)
83
84 // When the PM acts as sniffer and is receiving tag data, it takes
85 // 3 ticks A/D conversion
86 // 14 ticks to complete the modulation detection
87 // 8 ticks (on average) until the result is stored in to_arm
88 // + the delays in transferring data - which is the same for
89 // sniffing reader and tag data and therefore not relevant
90 #define DELAY_TAG_AIR2ARM_AS_SNIFFER (3 + 14 + 8)
91
92 // When the PM acts as sniffer and is receiving reader data, it takes
93 // 2 ticks delay in analogue RF receiver (for the falling edge of the
94 // start bit, which marks the start of the communication)
95 // 3 ticks A/D conversion
96 // 8 ticks on average until the data is stored in to_arm.
97 // + the delays in transferring data - which is the same for
98 // sniffing reader and tag data and therefore not relevant
99 #define DELAY_READER_AIR2ARM_AS_SNIFFER (2 + 3 + 8)
100
101 //variables used for timing purposes:
102 //these are in ssp_clk cycles:
103 static uint32_t NextTransferTime;
104 static uint32_t LastTimeProxToAirStart;
105 static uint32_t LastProxToAirDuration;
106
107
108
109 // CARD TO READER - manchester
110 // Sequence D: 11110000 modulation with subcarrier during first half
111 // Sequence E: 00001111 modulation with subcarrier during second half
112 // Sequence F: 00000000 no modulation with subcarrier
113 // READER TO CARD - miller
114 // Sequence X: 00001100 drop after half a period
115 // Sequence Y: 00000000 no drop
116 // Sequence Z: 11000000 drop at start
117 #define SEC_D 0xf0
118 #define SEC_E 0x0f
119 #define SEC_F 0x00
120 #define SEC_X 0x0c
121 #define SEC_Y 0x00
122 #define SEC_Z 0xc0
123
124 const uint8_t OddByteParity[256] = {
125 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
126 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
127 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
128 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
129 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
130 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
131 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
132 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
133 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
134 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
135 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
136 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
137 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
138 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
139 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
140 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1
141 };
142
143
144 void iso14a_set_trigger(bool enable) {
145 trigger = enable;
146 }
147
148
149 void iso14a_set_timeout(uint32_t timeout) {
150 iso14a_timeout = timeout;
151 if(MF_DBGLEVEL >= 3) Dbprintf("ISO14443A Timeout set to %ld (%dms)", iso14a_timeout, iso14a_timeout / 106);
152 }
153
154
155 void iso14a_set_ATS_timeout(uint8_t *ats) {
156
157 uint8_t tb1;
158 uint8_t fwi;
159 uint32_t fwt;
160
161 if (ats[0] > 1) { // there is a format byte T0
162 if ((ats[1] & 0x20) == 0x20) { // there is an interface byte TB(1)
163 if ((ats[1] & 0x10) == 0x10) { // there is an interface byte TA(1) preceding TB(1)
164 tb1 = ats[3];
165 } else {
166 tb1 = ats[2];
167 }
168 fwi = (tb1 & 0xf0) >> 4; // frame waiting indicator (FWI)
169 fwt = 256 * 16 * (1 << fwi); // frame waiting time (FWT) in 1/fc
170
171 iso14a_set_timeout(fwt/(8*16));
172 }
173 }
174 }
175
176
177 //-----------------------------------------------------------------------------
178 // Generate the parity value for a byte sequence
179 //
180 //-----------------------------------------------------------------------------
181 byte_t oddparity (const byte_t bt)
182 {
183 return OddByteParity[bt];
184 }
185
186 void GetParity(const uint8_t *pbtCmd, uint16_t iLen, uint8_t *par)
187 {
188 uint16_t paritybit_cnt = 0;
189 uint16_t paritybyte_cnt = 0;
190 uint8_t parityBits = 0;
191
192 for (uint16_t i = 0; i < iLen; i++) {
193 // Generate the parity bits
194 parityBits |= ((OddByteParity[pbtCmd[i]]) << (7-paritybit_cnt));
195 if (paritybit_cnt == 7) {
196 par[paritybyte_cnt] = parityBits; // save 8 Bits parity
197 parityBits = 0; // and advance to next Parity Byte
198 paritybyte_cnt++;
199 paritybit_cnt = 0;
200 } else {
201 paritybit_cnt++;
202 }
203 }
204
205 // save remaining parity bits
206 par[paritybyte_cnt] = parityBits;
207
208 }
209
210 void AppendCrc14443a(uint8_t* data, int len)
211 {
212 ComputeCrc14443(CRC_14443_A,data,len,data+len,data+len+1);
213 }
214
215 void AppendCrc14443b(uint8_t* data, int len)
216 {
217 ComputeCrc14443(CRC_14443_B,data,len,data+len,data+len+1);
218 }
219
220
221 //=============================================================================
222 // ISO 14443 Type A - Miller decoder
223 //=============================================================================
224 // Basics:
225 // This decoder is used when the PM3 acts as a tag.
226 // The reader will generate "pauses" by temporarily switching of the field.
227 // At the PM3 antenna we will therefore measure a modulated antenna voltage.
228 // The FPGA does a comparison with a threshold and would deliver e.g.:
229 // ........ 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 .......
230 // The Miller decoder needs to identify the following sequences:
231 // 2 (or 3) ticks pause followed by 6 (or 5) ticks unmodulated: pause at beginning - Sequence Z ("start of communication" or a "0")
232 // 8 ticks without a modulation: no pause - Sequence Y (a "0" or "end of communication" or "no information")
233 // 4 ticks unmodulated followed by 2 (or 3) ticks pause: pause in second half - Sequence X (a "1")
234 // Note 1: the bitstream may start at any time. We therefore need to sync.
235 // Note 2: the interpretation of Sequence Y and Z depends on the preceding sequence.
236 //-----------------------------------------------------------------------------
237 static tUart Uart;
238
239 // Lookup-Table to decide if 4 raw bits are a modulation.
240 // We accept the following:
241 // 0001 - a 3 tick wide pause
242 // 0011 - a 2 tick wide pause, or a three tick wide pause shifted left
243 // 0111 - a 2 tick wide pause shifted left
244 // 1001 - a 2 tick wide pause shifted right
245 const bool Mod_Miller_LUT[] = {
246 FALSE, TRUE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE,
247 FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE
248 };
249 #define IsMillerModulationNibble1(b) (Mod_Miller_LUT[(b & 0x000000F0) >> 4])
250 #define IsMillerModulationNibble2(b) (Mod_Miller_LUT[(b & 0x0000000F)])
251
252 void UartReset()
253 {
254 Uart.state = STATE_UNSYNCD;
255 Uart.bitCount = 0;
256 Uart.len = 0; // number of decoded data bytes
257 Uart.parityLen = 0; // number of decoded parity bytes
258 Uart.shiftReg = 0; // shiftreg to hold decoded data bits
259 Uart.parityBits = 0; // holds 8 parity bits
260 Uart.startTime = 0;
261 Uart.endTime = 0;
262
263 Uart.byteCntMax = 0;
264 Uart.posCnt = 0;
265 Uart.syncBit = 9999;
266 }
267
268 void UartInit(uint8_t *data, uint8_t *parity)
269 {
270 Uart.output = data;
271 Uart.parity = parity;
272 Uart.fourBits = 0x00000000; // clear the buffer for 4 Bits
273 UartReset();
274 }
275
276 // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
277 static RAMFUNC bool MillerDecoding(uint8_t bit, uint32_t non_real_time)
278 {
279
280 Uart.fourBits = (Uart.fourBits << 8) | bit;
281
282 if (Uart.state == STATE_UNSYNCD) { // not yet synced
283
284 Uart.syncBit = 9999; // not set
285
286 // 00x11111 2|3 ticks pause followed by 6|5 ticks unmodulated Sequence Z (a "0" or "start of communication")
287 // 11111111 8 ticks unmodulation Sequence Y (a "0" or "end of communication" or "no information")
288 // 111100x1 4 ticks unmodulated followed by 2|3 ticks pause Sequence X (a "1")
289
290 // The start bit is one ore more Sequence Y followed by a Sequence Z (... 11111111 00x11111). We need to distinguish from
291 // Sequence X followed by Sequence Y followed by Sequence Z (111100x1 11111111 00x11111)
292 // we therefore look for a ...xx1111 11111111 00x11111xxxxxx... pattern
293 // (12 '1's followed by 2 '0's, eventually followed by another '0', followed by 5 '1's)
294 //
295 #define ISO14443A_STARTBIT_MASK 0x07FFEF80 // mask is 00001111 11111111 1110 1111 10000000
296 #define ISO14443A_STARTBIT_PATTERN 0x07FF8F80 // pattern is 00001111 11111111 1000 1111 10000000
297
298 if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 0)) == ISO14443A_STARTBIT_PATTERN >> 0) Uart.syncBit = 7;
299 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 1)) == ISO14443A_STARTBIT_PATTERN >> 1) Uart.syncBit = 6;
300 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 2)) == ISO14443A_STARTBIT_PATTERN >> 2) Uart.syncBit = 5;
301 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 3)) == ISO14443A_STARTBIT_PATTERN >> 3) Uart.syncBit = 4;
302 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 4)) == ISO14443A_STARTBIT_PATTERN >> 4) Uart.syncBit = 3;
303 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 5)) == ISO14443A_STARTBIT_PATTERN >> 5) Uart.syncBit = 2;
304 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 6)) == ISO14443A_STARTBIT_PATTERN >> 6) Uart.syncBit = 1;
305 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 7)) == ISO14443A_STARTBIT_PATTERN >> 7) Uart.syncBit = 0;
306
307 if (Uart.syncBit != 9999) { // found a sync bit
308 Uart.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
309 Uart.startTime -= Uart.syncBit;
310 Uart.endTime = Uart.startTime;
311 Uart.state = STATE_START_OF_COMMUNICATION;
312 }
313
314 } else {
315
316 if (IsMillerModulationNibble1(Uart.fourBits >> Uart.syncBit)) {
317 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation in both halves - error
318 UartReset();
319 } else { // Modulation in first half = Sequence Z = logic "0"
320 if (Uart.state == STATE_MILLER_X) { // error - must not follow after X
321 UartReset();
322 } else {
323 Uart.bitCount++;
324 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
325 Uart.state = STATE_MILLER_Z;
326 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 6;
327 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
328 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
329 Uart.parityBits <<= 1; // make room for the parity bit
330 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
331 Uart.bitCount = 0;
332 Uart.shiftReg = 0;
333 if((Uart.len&0x0007) == 0) { // every 8 data bytes
334 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
335 Uart.parityBits = 0;
336 }
337 }
338 }
339 }
340 } else {
341 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation second half = Sequence X = logic "1"
342 Uart.bitCount++;
343 Uart.shiftReg = (Uart.shiftReg >> 1) | 0x100; // add a 1 to the shiftreg
344 Uart.state = STATE_MILLER_X;
345 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 2;
346 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
347 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
348 Uart.parityBits <<= 1; // make room for the new parity bit
349 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
350 Uart.bitCount = 0;
351 Uart.shiftReg = 0;
352 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
353 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
354 Uart.parityBits = 0;
355 }
356 }
357 } else { // no modulation in both halves - Sequence Y
358 if (Uart.state == STATE_MILLER_Z || Uart.state == STATE_MILLER_Y) { // Y after logic "0" - End of Communication
359 Uart.state = STATE_UNSYNCD;
360 Uart.bitCount--; // last "0" was part of EOC sequence
361 Uart.shiftReg <<= 1; // drop it
362 if(Uart.bitCount > 0) { // if we decoded some bits
363 Uart.shiftReg >>= (9 - Uart.bitCount); // right align them
364 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff); // add last byte to the output
365 Uart.parityBits <<= 1; // add a (void) parity bit
366 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align parity bits
367 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store it
368 return TRUE;
369 } else if (Uart.len & 0x0007) { // there are some parity bits to store
370 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align remaining parity bits
371 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store them
372 }
373 if (Uart.len) {
374 return TRUE; // we are finished with decoding the raw data sequence
375 } else {
376 UartReset(); // Nothing received - start over
377 }
378 }
379 if (Uart.state == STATE_START_OF_COMMUNICATION) { // error - must not follow directly after SOC
380 UartReset();
381 } else { // a logic "0"
382 Uart.bitCount++;
383 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
384 Uart.state = STATE_MILLER_Y;
385 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
386 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
387 Uart.parityBits <<= 1; // make room for the parity bit
388 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
389 Uart.bitCount = 0;
390 Uart.shiftReg = 0;
391 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
392 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
393 Uart.parityBits = 0;
394 }
395 }
396 }
397 }
398 }
399
400 }
401
402 return FALSE; // not finished yet, need more data
403 }
404
405
406
407 //=============================================================================
408 // ISO 14443 Type A - Manchester decoder
409 //=============================================================================
410 // Basics:
411 // This decoder is used when the PM3 acts as a reader.
412 // The tag will modulate the reader field by asserting different loads to it. As a consequence, the voltage
413 // at the reader antenna will be modulated as well. The FPGA detects the modulation for us and would deliver e.g. the following:
414 // ........ 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .......
415 // The Manchester decoder needs to identify the following sequences:
416 // 4 ticks modulated followed by 4 ticks unmodulated: Sequence D = 1 (also used as "start of communication")
417 // 4 ticks unmodulated followed by 4 ticks modulated: Sequence E = 0
418 // 8 ticks unmodulated: Sequence F = end of communication
419 // 8 ticks modulated: A collision. Save the collision position and treat as Sequence D
420 // Note 1: the bitstream may start at any time. We therefore need to sync.
421 // Note 2: parameter offset is used to determine the position of the parity bits (required for the anticollision command only)
422 static tDemod Demod;
423
424 // Lookup-Table to decide if 4 raw bits are a modulation.
425 // We accept three or four "1" in any position
426 const bool Mod_Manchester_LUT[] = {
427 FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE,
428 FALSE, FALSE, FALSE, TRUE, FALSE, TRUE, TRUE, TRUE
429 };
430
431 #define IsManchesterModulationNibble1(b) (Mod_Manchester_LUT[(b & 0x00F0) >> 4])
432 #define IsManchesterModulationNibble2(b) (Mod_Manchester_LUT[(b & 0x000F)])
433
434
435 void DemodReset()
436 {
437 Demod.state = DEMOD_UNSYNCD;
438 Demod.len = 0; // number of decoded data bytes
439 Demod.parityLen = 0;
440 Demod.shiftReg = 0; // shiftreg to hold decoded data bits
441 Demod.parityBits = 0; //
442 Demod.collisionPos = 0; // Position of collision bit
443 Demod.twoBits = 0xffff; // buffer for 2 Bits
444 Demod.highCnt = 0;
445 Demod.startTime = 0;
446 Demod.endTime = 0;
447
448 //
449 Demod.bitCount = 0;
450 Demod.syncBit = 0xFFFF;
451 Demod.samples = 0;
452 }
453
454 void DemodInit(uint8_t *data, uint8_t *parity)
455 {
456 Demod.output = data;
457 Demod.parity = parity;
458 DemodReset();
459 }
460
461 // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
462 static RAMFUNC int ManchesterDecoding(uint8_t bit, uint16_t offset, uint32_t non_real_time)
463 {
464
465 Demod.twoBits = (Demod.twoBits << 8) | bit;
466
467 if (Demod.state == DEMOD_UNSYNCD) {
468
469 if (Demod.highCnt < 2) { // wait for a stable unmodulated signal
470 if (Demod.twoBits == 0x0000) {
471 Demod.highCnt++;
472 } else {
473 Demod.highCnt = 0;
474 }
475 } else {
476 Demod.syncBit = 0xFFFF; // not set
477 if ((Demod.twoBits & 0x7700) == 0x7000) Demod.syncBit = 7;
478 else if ((Demod.twoBits & 0x3B80) == 0x3800) Demod.syncBit = 6;
479 else if ((Demod.twoBits & 0x1DC0) == 0x1C00) Demod.syncBit = 5;
480 else if ((Demod.twoBits & 0x0EE0) == 0x0E00) Demod.syncBit = 4;
481 else if ((Demod.twoBits & 0x0770) == 0x0700) Demod.syncBit = 3;
482 else if ((Demod.twoBits & 0x03B8) == 0x0380) Demod.syncBit = 2;
483 else if ((Demod.twoBits & 0x01DC) == 0x01C0) Demod.syncBit = 1;
484 else if ((Demod.twoBits & 0x00EE) == 0x00E0) Demod.syncBit = 0;
485 if (Demod.syncBit != 0xFFFF) {
486 Demod.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
487 Demod.startTime -= Demod.syncBit;
488 Demod.bitCount = offset; // number of decoded data bits
489 Demod.state = DEMOD_MANCHESTER_DATA;
490 }
491 }
492
493 } else {
494
495 if (IsManchesterModulationNibble1(Demod.twoBits >> Demod.syncBit)) { // modulation in first half
496 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // ... and in second half = collision
497 if (!Demod.collisionPos) {
498 Demod.collisionPos = (Demod.len << 3) + Demod.bitCount;
499 }
500 } // modulation in first half only - Sequence D = 1
501 Demod.bitCount++;
502 Demod.shiftReg = (Demod.shiftReg >> 1) | 0x100; // in both cases, add a 1 to the shiftreg
503 if(Demod.bitCount == 9) { // if we decoded a full byte (including parity)
504 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
505 Demod.parityBits <<= 1; // make room for the parity bit
506 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
507 Demod.bitCount = 0;
508 Demod.shiftReg = 0;
509 if((Demod.len&0x0007) == 0) { // every 8 data bytes
510 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits
511 Demod.parityBits = 0;
512 }
513 }
514 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1) - 4;
515 } else { // no modulation in first half
516 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // and modulation in second half = Sequence E = 0
517 Demod.bitCount++;
518 Demod.shiftReg = (Demod.shiftReg >> 1); // add a 0 to the shiftreg
519 if(Demod.bitCount >= 9) { // if we decoded a full byte (including parity)
520 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
521 Demod.parityBits <<= 1; // make room for the new parity bit
522 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
523 Demod.bitCount = 0;
524 Demod.shiftReg = 0;
525 if ((Demod.len&0x0007) == 0) { // every 8 data bytes
526 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits1
527 Demod.parityBits = 0;
528 }
529 }
530 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1);
531 } else { // no modulation in both halves - End of communication
532 if(Demod.bitCount > 0) { // there are some remaining data bits
533 Demod.shiftReg >>= (9 - Demod.bitCount); // right align the decoded bits
534 Demod.output[Demod.len++] = Demod.shiftReg & 0xff; // and add them to the output
535 Demod.parityBits <<= 1; // add a (void) parity bit
536 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
537 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
538 return TRUE;
539 } else if (Demod.len & 0x0007) { // there are some parity bits to store
540 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
541 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
542 }
543 if (Demod.len) {
544 return TRUE; // we are finished with decoding the raw data sequence
545 } else { // nothing received. Start over
546 DemodReset();
547 }
548 }
549 }
550 }
551 return FALSE; // not finished yet, need more data
552 }
553
554 //=============================================================================
555 // Finally, a `sniffer' for ISO 14443 Type A
556 // Both sides of communication!
557 //=============================================================================
558
559 //-----------------------------------------------------------------------------
560 // Record the sequence of commands sent by the reader to the tag, with
561 // triggering so that we start recording at the point that the tag is moved
562 // near the reader.
563 //-----------------------------------------------------------------------------
564 void RAMFUNC SniffIso14443a(uint8_t param) {
565 // param:
566 // bit 0 - trigger from first card answer
567 // bit 1 - trigger from first reader 7-bit request
568 LEDsoff();
569
570 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
571
572 // Allocate memory from BigBuf for some buffers
573 // free all previous allocations first
574 BigBuf_free();
575
576 // init trace buffer
577 clear_trace();
578 set_tracing(TRUE);
579
580 // The command (reader -> tag) that we're receiving.
581 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
582 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
583
584 // The response (tag -> reader) that we're receiving.
585 uint8_t *receivedResponse = BigBuf_malloc(MAX_FRAME_SIZE);
586 uint8_t *receivedResponsePar = BigBuf_malloc(MAX_PARITY_SIZE);
587
588 // The DMA buffer, used to stream samples from the FPGA
589 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
590
591 uint8_t *data = dmaBuf;
592 uint8_t previous_data = 0;
593 int maxDataLen = 0;
594 int dataLen = 0;
595 bool TagIsActive = FALSE;
596 bool ReaderIsActive = FALSE;
597
598 // Set up the demodulator for tag -> reader responses.
599 DemodInit(receivedResponse, receivedResponsePar);
600
601 // Set up the demodulator for the reader -> tag commands
602 UartInit(receivedCmd, receivedCmdPar);
603
604 // Setup and start DMA.
605 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE);
606
607 // We won't start recording the frames that we acquire until we trigger;
608 // a good trigger condition to get started is probably when we see a
609 // response from the tag.
610 // triggered == FALSE -- to wait first for card
611 bool triggered = !(param & 0x03);
612
613 // And now we loop, receiving samples.
614 for(uint32_t rsamples = 0; TRUE; ) {
615
616 if(BUTTON_PRESS()) {
617 DbpString("cancelled by button");
618 break;
619 }
620
621 LED_A_ON();
622 WDT_HIT();
623
624 int register readBufDataP = data - dmaBuf;
625 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR;
626 if (readBufDataP <= dmaBufDataP){
627 dataLen = dmaBufDataP - readBufDataP;
628 } else {
629 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP;
630 }
631 // test for length of buffer
632 if(dataLen > maxDataLen) {
633 maxDataLen = dataLen;
634 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
635 Dbprintf("blew circular buffer! dataLen=%d", dataLen);
636 break;
637 }
638 }
639 if(dataLen < 1) continue;
640
641 // primary buffer was stopped( <-- we lost data!
642 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
643 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
644 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
645 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
646 }
647 // secondary buffer sets as primary, secondary buffer was stopped
648 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
649 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
650 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
651 }
652
653 LED_A_OFF();
654
655 if (rsamples & 0x01) { // Need two samples to feed Miller and Manchester-Decoder
656
657 if(!TagIsActive) { // no need to try decoding reader data if the tag is sending
658 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
659 if (MillerDecoding(readerdata, (rsamples-1)*4)) {
660 LED_C_ON();
661
662 // check - if there is a short 7bit request from reader
663 if ((!triggered) && (param & 0x02) && (Uart.len == 1) && (Uart.bitCount == 7)) triggered = TRUE;
664
665 if(triggered) {
666 if (!LogTrace(receivedCmd,
667 Uart.len,
668 Uart.startTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
669 Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
670 Uart.parity,
671 TRUE)) break;
672 }
673 /* And ready to receive another command. */
674 UartReset();
675 /* And also reset the demod code, which might have been */
676 /* false-triggered by the commands from the reader. */
677 DemodReset();
678 LED_B_OFF();
679 }
680 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
681 }
682
683 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
684 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
685 if(ManchesterDecoding(tagdata, 0, (rsamples-1)*4)) {
686 LED_B_ON();
687
688 if (!LogTrace(receivedResponse,
689 Demod.len,
690 Demod.startTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
691 Demod.endTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
692 Demod.parity,
693 FALSE)) break;
694
695 if ((!triggered) && (param & 0x01)) triggered = TRUE;
696
697 // And ready to receive another response.
698 DemodReset();
699 // And reset the Miller decoder including itS (now outdated) input buffer
700 UartInit(receivedCmd, receivedCmdPar);
701
702 LED_C_OFF();
703 }
704 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
705 }
706 }
707
708 previous_data = *data;
709 rsamples++;
710 data++;
711 if(data == dmaBuf + DMA_BUFFER_SIZE) {
712 data = dmaBuf;
713 }
714 } // main cycle
715
716 FpgaDisableSscDma();
717 LEDsoff();
718
719 Dbprintf("maxDataLen=%d, Uart.state=%x, Uart.len=%d", maxDataLen, Uart.state, Uart.len);
720 Dbprintf("traceLen=%d, Uart.output[0]=%08x", BigBuf_get_traceLen(), (uint32_t)Uart.output[0]);
721 }
722
723 //-----------------------------------------------------------------------------
724 // Prepare tag messages
725 //-----------------------------------------------------------------------------
726 static void CodeIso14443aAsTagPar(const uint8_t *cmd, uint16_t len, uint8_t *parity)
727 {
728 ToSendReset();
729
730 // Correction bit, might be removed when not needed
731 ToSendStuffBit(0);
732 ToSendStuffBit(0);
733 ToSendStuffBit(0);
734 ToSendStuffBit(0);
735 ToSendStuffBit(1); // 1
736 ToSendStuffBit(0);
737 ToSendStuffBit(0);
738 ToSendStuffBit(0);
739
740 // Send startbit
741 ToSend[++ToSendMax] = SEC_D;
742 LastProxToAirDuration = 8 * ToSendMax - 4;
743
744 for(uint16_t i = 0; i < len; i++) {
745 uint8_t b = cmd[i];
746
747 // Data bits
748 for(uint16_t j = 0; j < 8; j++) {
749 if(b & 1) {
750 ToSend[++ToSendMax] = SEC_D;
751 } else {
752 ToSend[++ToSendMax] = SEC_E;
753 }
754 b >>= 1;
755 }
756
757 // Get the parity bit
758 if (parity[i>>3] & (0x80>>(i&0x0007))) {
759 ToSend[++ToSendMax] = SEC_D;
760 LastProxToAirDuration = 8 * ToSendMax - 4;
761 } else {
762 ToSend[++ToSendMax] = SEC_E;
763 LastProxToAirDuration = 8 * ToSendMax;
764 }
765 }
766
767 // Send stopbit
768 ToSend[++ToSendMax] = SEC_F;
769
770 // Convert from last byte pos to length
771 ToSendMax++;
772 }
773
774 static void CodeIso14443aAsTag(const uint8_t *cmd, uint16_t len)
775 {
776 uint8_t par[MAX_PARITY_SIZE];
777
778 GetParity(cmd, len, par);
779 CodeIso14443aAsTagPar(cmd, len, par);
780 }
781
782
783 static void Code4bitAnswerAsTag(uint8_t cmd)
784 {
785 int i;
786
787 ToSendReset();
788
789 // Correction bit, might be removed when not needed
790 ToSendStuffBit(0);
791 ToSendStuffBit(0);
792 ToSendStuffBit(0);
793 ToSendStuffBit(0);
794 ToSendStuffBit(1); // 1
795 ToSendStuffBit(0);
796 ToSendStuffBit(0);
797 ToSendStuffBit(0);
798
799 // Send startbit
800 ToSend[++ToSendMax] = SEC_D;
801
802 uint8_t b = cmd;
803 for(i = 0; i < 4; i++) {
804 if(b & 1) {
805 ToSend[++ToSendMax] = SEC_D;
806 LastProxToAirDuration = 8 * ToSendMax - 4;
807 } else {
808 ToSend[++ToSendMax] = SEC_E;
809 LastProxToAirDuration = 8 * ToSendMax;
810 }
811 b >>= 1;
812 }
813
814 // Send stopbit
815 ToSend[++ToSendMax] = SEC_F;
816
817 // Convert from last byte pos to length
818 ToSendMax++;
819 }
820
821 //-----------------------------------------------------------------------------
822 // Wait for commands from reader
823 // Stop when button is pressed
824 // Or return TRUE when command is captured
825 //-----------------------------------------------------------------------------
826 static int GetIso14443aCommandFromReader(uint8_t *received, uint8_t *parity, int *len)
827 {
828 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
829 // only, since we are receiving, not transmitting).
830 // Signal field is off with the appropriate LED
831 LED_D_OFF();
832 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
833
834 // Now run a `software UART' on the stream of incoming samples.
835 UartInit(received, parity);
836
837 // clear RXRDY:
838 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
839
840 for(;;) {
841 WDT_HIT();
842
843 if(BUTTON_PRESS()) return FALSE;
844
845 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
846 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
847 if(MillerDecoding(b, 0)) {
848 *len = Uart.len;
849 return TRUE;
850 }
851 }
852 }
853 }
854
855 static int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded);
856 int EmSend4bitEx(uint8_t resp, bool correctionNeeded);
857 int EmSend4bit(uint8_t resp);
858 int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par);
859 int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded);
860 int EmSendCmd(uint8_t *resp, uint16_t respLen);
861 int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par);
862 bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint8_t *reader_Parity,
863 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint8_t *tag_Parity);
864
865 static uint8_t* free_buffer_pointer;
866
867 typedef struct {
868 uint8_t* response;
869 size_t response_n;
870 uint8_t* modulation;
871 size_t modulation_n;
872 uint32_t ProxToAirDuration;
873 } tag_response_info_t;
874
875 bool prepare_tag_modulation(tag_response_info_t* response_info, size_t max_buffer_size) {
876 // Example response, answer to MIFARE Classic read block will be 16 bytes + 2 CRC = 18 bytes
877 // This will need the following byte array for a modulation sequence
878 // 144 data bits (18 * 8)
879 // 18 parity bits
880 // 2 Start and stop
881 // 1 Correction bit (Answer in 1172 or 1236 periods, see FPGA)
882 // 1 just for the case
883 // ----------- +
884 // 166 bytes, since every bit that needs to be send costs us a byte
885 //
886
887
888 // Prepare the tag modulation bits from the message
889 CodeIso14443aAsTag(response_info->response,response_info->response_n);
890
891 // Make sure we do not exceed the free buffer space
892 if (ToSendMax > max_buffer_size) {
893 Dbprintf("Out of memory, when modulating bits for tag answer:");
894 Dbhexdump(response_info->response_n,response_info->response,false);
895 return false;
896 }
897
898 // Copy the byte array, used for this modulation to the buffer position
899 memcpy(response_info->modulation,ToSend,ToSendMax);
900
901 // Store the number of bytes that were used for encoding/modulation and the time needed to transfer them
902 response_info->modulation_n = ToSendMax;
903 response_info->ProxToAirDuration = LastProxToAirDuration;
904
905 return true;
906 }
907
908
909 // "precompile" responses. There are 7 predefined responses with a total of 28 bytes data to transmit.
910 // Coded responses need one byte per bit to transfer (data, parity, start, stop, correction)
911 // 28 * 8 data bits, 28 * 1 parity bits, 7 start bits, 7 stop bits, 7 correction bits
912 // -> need 273 bytes buffer
913 // 44 * 8 data bits, 44 * 1 parity bits, 9 start bits, 9 stop bits, 9 correction bits --370
914 // 47 * 8 data bits, 47 * 1 parity bits, 10 start bits, 10 stop bits, 10 correction bits
915 #define ALLOCATED_TAG_MODULATION_BUFFER_SIZE 453
916
917 bool prepare_allocated_tag_modulation(tag_response_info_t* response_info) {
918 // Retrieve and store the current buffer index
919 response_info->modulation = free_buffer_pointer;
920
921 // Determine the maximum size we can use from our buffer
922 size_t max_buffer_size = ALLOCATED_TAG_MODULATION_BUFFER_SIZE;
923
924 // Forward the prepare tag modulation function to the inner function
925 if (prepare_tag_modulation(response_info, max_buffer_size)) {
926 // Update the free buffer offset
927 free_buffer_pointer += ToSendMax;
928 return true;
929 } else {
930 return false;
931 }
932 }
933
934 //-----------------------------------------------------------------------------
935 // Main loop of simulated tag: receive commands from reader, decide what
936 // response to send, and send it.
937 //-----------------------------------------------------------------------------
938 void SimulateIso14443aTag(int tagType, int flags, byte_t* data)
939 {
940
941 //Here, we collect UID,NT,AR,NR,UID2,NT2,AR2,NR2
942 // This can be used in a reader-only attack.
943 // (it can also be retrieved via 'hf 14a list', but hey...
944 uint32_t ar_nr_responses[] = {0,0,0,0,0,0,0,0,0,0};
945 uint8_t ar_nr_collected = 0;
946
947 uint8_t sak;
948
949 // PACK response to PWD AUTH for EV1/NTAG
950 uint8_t response8[4];
951
952 // The first response contains the ATQA (note: bytes are transmitted in reverse order).
953 uint8_t response1[2];
954
955 switch (tagType) {
956 case 1: { // MIFARE Classic
957 // Says: I am Mifare 1k - original line
958 response1[0] = 0x04;
959 response1[1] = 0x00;
960 sak = 0x08;
961 } break;
962 case 2: { // MIFARE Ultralight
963 // Says: I am a stupid memory tag, no crypto
964 response1[0] = 0x44;
965 response1[1] = 0x00;
966 sak = 0x00;
967 } break;
968 case 3: { // MIFARE DESFire
969 // Says: I am a DESFire tag, ph33r me
970 response1[0] = 0x04;
971 response1[1] = 0x03;
972 sak = 0x20;
973 } break;
974 case 4: { // ISO/IEC 14443-4
975 // Says: I am a javacard (JCOP)
976 response1[0] = 0x04;
977 response1[1] = 0x00;
978 sak = 0x28;
979 } break;
980 case 5: { // MIFARE TNP3XXX
981 // Says: I am a toy
982 response1[0] = 0x01;
983 response1[1] = 0x0f;
984 sak = 0x01;
985 } break;
986 case 6: { // MIFARE Mini
987 // Says: I am a Mifare Mini, 320b
988 response1[0] = 0x44;
989 response1[1] = 0x00;
990 sak = 0x09;
991 } break;
992 case 7: { // NTAG?
993 // Says: I am a NTAG,
994 response1[0] = 0x44;
995 response1[1] = 0x00;
996 sak = 0x00;
997 // PACK
998 response8[0] = 0x80;
999 response8[1] = 0x80;
1000 ComputeCrc14443(CRC_14443_A, response8, 2, &response8[2], &response8[3]);
1001 } break;
1002 default: {
1003 Dbprintf("Error: unkown tagtype (%d)",tagType);
1004 return;
1005 } break;
1006 }
1007
1008 // The second response contains the (mandatory) first 24 bits of the UID
1009 uint8_t response2[5] = {0x00};
1010
1011 // Check if the uid uses the (optional) part
1012 uint8_t response2a[5] = {0x00};
1013
1014 if (flags & FLAG_7B_UID_IN_DATA) {
1015 response2[0] = 0x88;
1016 response2[1] = data[0];
1017 response2[2] = data[1];
1018 response2[3] = data[2];
1019
1020 response2a[0] = data[3];
1021 response2a[1] = data[4];
1022 response2a[2] = data[5];
1023 response2a[3] = data[6]; //??
1024 response2a[4] = response2a[0] ^ response2a[1] ^ response2a[2] ^ response2a[3];
1025
1026 // Configure the ATQA and SAK accordingly
1027 response1[0] |= 0x40;
1028 sak |= 0x04;
1029 } else {
1030 memcpy(response2, data, 4);
1031 //num_to_bytes(uid_1st,4,response2);
1032 // Configure the ATQA and SAK accordingly
1033 response1[0] &= 0xBF;
1034 sak &= 0xFB;
1035 }
1036
1037 // Calculate the BitCountCheck (BCC) for the first 4 bytes of the UID.
1038 response2[4] = response2[0] ^ response2[1] ^ response2[2] ^ response2[3];
1039
1040 // Prepare the mandatory SAK (for 4 and 7 byte UID)
1041 uint8_t response3[3] = {0x00};
1042 response3[0] = sak;
1043 ComputeCrc14443(CRC_14443_A, response3, 1, &response3[1], &response3[2]);
1044
1045 // Prepare the optional second SAK (for 7 byte UID), drop the cascade bit
1046 uint8_t response3a[3] = {0x00};
1047 response3a[0] = sak & 0xFB;
1048 ComputeCrc14443(CRC_14443_A, response3a, 1, &response3a[1], &response3a[2]);
1049
1050 uint8_t response5[] = { 0x00, 0x00, 0x00, 0x00 }; // Very random tag nonce
1051 uint8_t response6[] = { 0x04, 0x58, 0x80, 0x02, 0x00, 0x00 }; // dummy ATS (pseudo-ATR), answer to RATS:
1052 // Format byte = 0x58: FSCI=0x08 (FSC=256), TA(1) and TC(1) present,
1053 // TA(1) = 0x80: different divisors not supported, DR = 1, DS = 1
1054 // TB(1) = not present. Defaults: FWI = 4 (FWT = 256 * 16 * 2^4 * 1/fc = 4833us), SFGI = 0 (SFG = 256 * 16 * 2^0 * 1/fc = 302us)
1055 // TC(1) = 0x02: CID supported, NAD not supported
1056 ComputeCrc14443(CRC_14443_A, response6, 4, &response6[4], &response6[5]);
1057
1058 // Prepare GET_VERSION (different for EV-1 / NTAG)
1059 //uint8_t response7_EV1[] = {0x00, 0x04, 0x03, 0x01, 0x01, 0x00, 0x0b, 0x03, 0xfd, 0xf7}; //EV1 48bytes VERSION.
1060 uint8_t response7_NTAG[] = {0x00, 0x04, 0x04, 0x02, 0x01, 0x00, 0x11, 0x03, 0x01, 0x9e}; //NTAG 215
1061
1062 // Prepare CHK_TEARING
1063 uint8_t response9[] = {0xBD,0x90,0x3f};
1064
1065 #define TAG_RESPONSE_COUNT 10
1066 tag_response_info_t responses[TAG_RESPONSE_COUNT] = {
1067 { .response = response1, .response_n = sizeof(response1) }, // Answer to request - respond with card type
1068 { .response = response2, .response_n = sizeof(response2) }, // Anticollision cascade1 - respond with uid
1069 { .response = response2a, .response_n = sizeof(response2a) }, // Anticollision cascade2 - respond with 2nd half of uid if asked
1070 { .response = response3, .response_n = sizeof(response3) }, // Acknowledge select - cascade 1
1071 { .response = response3a, .response_n = sizeof(response3a) }, // Acknowledge select - cascade 2
1072 { .response = response5, .response_n = sizeof(response5) }, // Authentication answer (random nonce)
1073 { .response = response6, .response_n = sizeof(response6) }, // dummy ATS (pseudo-ATR), answer to RATS
1074 { .response = response7_NTAG, .response_n = sizeof(response7_NTAG) }, // EV1/NTAG GET_VERSION response
1075 { .response = response8, .response_n = sizeof(response8) }, // EV1/NTAG PACK response
1076 { .response = response9, .response_n = sizeof(response9) } // EV1/NTAG CHK_TEAR response
1077 };
1078
1079 // Allocate 512 bytes for the dynamic modulation, created when the reader queries for it
1080 // Such a response is less time critical, so we can prepare them on the fly
1081 #define DYNAMIC_RESPONSE_BUFFER_SIZE 64
1082 #define DYNAMIC_MODULATION_BUFFER_SIZE 512
1083 uint8_t dynamic_response_buffer[DYNAMIC_RESPONSE_BUFFER_SIZE];
1084 uint8_t dynamic_modulation_buffer[DYNAMIC_MODULATION_BUFFER_SIZE];
1085 tag_response_info_t dynamic_response_info = {
1086 .response = dynamic_response_buffer,
1087 .response_n = 0,
1088 .modulation = dynamic_modulation_buffer,
1089 .modulation_n = 0
1090 };
1091
1092 // We need to listen to the high-frequency, peak-detected path.
1093 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1094
1095 BigBuf_free_keep_EM();
1096
1097 // allocate buffers:
1098 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
1099 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
1100 free_buffer_pointer = BigBuf_malloc(ALLOCATED_TAG_MODULATION_BUFFER_SIZE);
1101
1102 // clear trace
1103 clear_trace();
1104 set_tracing(TRUE);
1105
1106 // Prepare the responses of the anticollision phase
1107 // there will be not enough time to do this at the moment the reader sends it REQA
1108 for (size_t i=0; i<TAG_RESPONSE_COUNT; i++) {
1109 prepare_allocated_tag_modulation(&responses[i]);
1110 }
1111
1112 int len = 0;
1113
1114 // To control where we are in the protocol
1115 int order = 0;
1116 int lastorder;
1117
1118 // Just to allow some checks
1119 int happened = 0;
1120 int happened2 = 0;
1121 int cmdsRecvd = 0;
1122
1123 cmdsRecvd = 0;
1124 tag_response_info_t* p_response;
1125
1126 LED_A_ON();
1127 for(;;) {
1128 // Clean receive command buffer
1129
1130 if(!GetIso14443aCommandFromReader(receivedCmd, receivedCmdPar, &len)) {
1131 DbpString("Button press");
1132 break;
1133 }
1134
1135 p_response = NULL;
1136
1137 // Okay, look at the command now.
1138 lastorder = order;
1139 if(receivedCmd[0] == 0x26) { // Received a REQUEST
1140 p_response = &responses[0]; order = 1;
1141 } else if(receivedCmd[0] == 0x52) { // Received a WAKEUP
1142 p_response = &responses[0]; order = 6;
1143 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x93) { // Received request for UID (cascade 1)
1144 p_response = &responses[1]; order = 2;
1145 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x95) { // Received request for UID (cascade 2)
1146 p_response = &responses[2]; order = 20;
1147 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x93) { // Received a SELECT (cascade 1)
1148 p_response = &responses[3]; order = 3;
1149 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x95) { // Received a SELECT (cascade 2)
1150 p_response = &responses[4]; order = 30;
1151 } else if(receivedCmd[0] == 0x30) { // Received a (plain) READ
1152 uint8_t block = receivedCmd[1];
1153 if ( tagType == 7 ) {
1154 uint16_t start = 4 * block;
1155
1156 /*if ( block < 4 ) {
1157 //NTAG 215
1158 uint8_t blockdata[50] = {
1159 data[0],data[1],data[2], 0x88 ^ data[0] ^ data[1] ^ data[2],
1160 data[3],data[4],data[5],data[6],
1161 data[3] ^ data[4] ^ data[5] ^ data[6],0x48,0x0f,0xe0,
1162 0xe1,0x10,0x12,0x00,
1163 0x03,0x00,0xfe,0x00,
1164 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
1165 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
1166 0x00,0x00,0x00,0x00,
1167 0x00,0x00};
1168 AppendCrc14443a(blockdata+start, 16);
1169 EmSendCmdEx( blockdata+start, MAX_MIFARE_FRAME_SIZE, false);
1170 } else {*/
1171 uint8_t emdata[MAX_MIFARE_FRAME_SIZE];
1172 emlGetMemBt( emdata, start, 16);
1173 AppendCrc14443a(emdata, 16);
1174 EmSendCmdEx(emdata, sizeof(emdata), false);
1175 //}
1176 p_response = NULL;
1177
1178 } else {
1179 EmSendCmdEx(data+(4*block),16,false);
1180 // Dbprintf("Read request from reader: %x %x",receivedCmd[0],receivedCmd[1]);
1181 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
1182 p_response = NULL;
1183 }
1184 } else if(receivedCmd[0] == 0x3A) { // Received a FAST READ (ranged read) -- just returns all zeros.
1185
1186 uint8_t emdata[MAX_FRAME_SIZE];
1187 int start = receivedCmd[1] * 4;
1188 int len = (receivedCmd[2] - receivedCmd[1] + 1) * 4;
1189 emlGetMemBt( emdata, start, len);
1190 AppendCrc14443a(emdata, len);
1191 EmSendCmdEx(emdata, len+2, false);
1192 p_response = NULL;
1193
1194 } else if(receivedCmd[0] == 0x3C && tagType == 7) { // Received a READ SIGNATURE --
1195 // ECC data, taken from a NTAG215 amiibo token. might work. LEN: 32, + 2 crc
1196 uint8_t data[] = {0x56,0x06,0xa6,0x4f,0x43,0x32,0x53,0x6f,
1197 0x43,0xda,0x45,0xd6,0x61,0x38,0xaa,0x1e,
1198 0xcf,0xd3,0x61,0x36,0xca,0x5f,0xbb,0x05,
1199 0xce,0x21,0x24,0x5b,0xa6,0x7a,0x79,0x07,
1200 0x00,0x00};
1201 AppendCrc14443a(data, sizeof(data)-2);
1202 EmSendCmdEx(data,sizeof(data),false);
1203 p_response = NULL;
1204 } else if(receivedCmd[0] == 0x39 && tagType == 7) { // Received a READ COUNTER --
1205 uint8_t data[] = {0x00,0x00,0x00,0x14,0xa5};
1206 EmSendCmdEx(data,sizeof(data),false);
1207 p_response = NULL;
1208 } else if(receivedCmd[0] == 0xA5 && tagType == 7) { // Received a INC COUNTER --
1209 // number of counter
1210 //uint8_t counter = receivedCmd[1];
1211 //uint32_t val = bytes_to_num(receivedCmd+2,4);
1212
1213 // send ACK
1214 uint8_t ack[] = {0x0a};
1215 EmSendCmdEx(ack,sizeof(ack),false);
1216 p_response = NULL;
1217
1218 } else if(receivedCmd[0] == 0x3E && tagType == 7) { // Received a CHECK_TEARING_EVENT --
1219 p_response = &responses[9];
1220 } else if(receivedCmd[0] == 0x50) { // Received a HALT
1221
1222 if (tracing) {
1223 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1224 }
1225 p_response = NULL;
1226 } else if(receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61) { // Received an authentication request
1227
1228 if ( tagType == 7 ) { // IF NTAG /EV1 0x60 == GET_VERSION, not a authentication request.
1229 p_response = &responses[7];
1230 } else {
1231 p_response = &responses[5]; order = 7;
1232 }
1233 } else if(receivedCmd[0] == 0xE0) { // Received a RATS request
1234 if (tagType == 1 || tagType == 2) { // RATS not supported
1235 EmSend4bit(CARD_NACK_NA);
1236 p_response = NULL;
1237 } else {
1238 p_response = &responses[6]; order = 70;
1239 }
1240 } else if (order == 7 && len == 8) { // Received {nr] and {ar} (part of authentication)
1241 if (tracing) {
1242 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1243 }
1244 uint32_t nonce = bytes_to_num(response5,4);
1245 uint32_t nr = bytes_to_num(receivedCmd,4);
1246 uint32_t ar = bytes_to_num(receivedCmd+4,4);
1247 //Dbprintf("Auth attempt {nonce}{nr}{ar}: %08x %08x %08x", nonce, nr, ar);
1248
1249 if(flags & FLAG_NR_AR_ATTACK )
1250 {
1251 if(ar_nr_collected < 2){
1252 // Avoid duplicates... probably not necessary, nr should vary.
1253 //if(ar_nr_responses[3] != nr){
1254 ar_nr_responses[ar_nr_collected*5] = 0;
1255 ar_nr_responses[ar_nr_collected*5+1] = 0;
1256 ar_nr_responses[ar_nr_collected*5+2] = nonce;
1257 ar_nr_responses[ar_nr_collected*5+3] = nr;
1258 ar_nr_responses[ar_nr_collected*5+4] = ar;
1259 ar_nr_collected++;
1260 //}
1261 }
1262
1263 if(ar_nr_collected > 1 ) {
1264
1265 if (MF_DBGLEVEL >= 2) {
1266 Dbprintf("Collected two pairs of AR/NR which can be used to extract keys from reader:");
1267 Dbprintf("../tools/mfkey/mfkey32 %07x%08x %08x %08x %08x %08x %08x",
1268 ar_nr_responses[0], // UID1
1269 ar_nr_responses[1], // UID2
1270 ar_nr_responses[2], // NT
1271 ar_nr_responses[3], // AR1
1272 ar_nr_responses[4], // NR1
1273 ar_nr_responses[8], // AR2
1274 ar_nr_responses[9] // NR2
1275 );
1276 Dbprintf("../tools/mfkey/mfkey32v2 %06x%08x %08x %08x %08x %08x %08x %08x",
1277 ar_nr_responses[0], // UID1
1278 ar_nr_responses[1], // UID2
1279 ar_nr_responses[2], // NT1
1280 ar_nr_responses[3], // AR1
1281 ar_nr_responses[4], // NR1
1282 ar_nr_responses[7], // NT2
1283 ar_nr_responses[8], // AR2
1284 ar_nr_responses[9] // NR2
1285 );
1286 }
1287 uint8_t len = ar_nr_collected*5*4;
1288 cmd_send(CMD_ACK,CMD_SIMULATE_MIFARE_CARD,len,0,&ar_nr_responses,len);
1289 ar_nr_collected = 0;
1290 memset(ar_nr_responses, 0x00, len);
1291 }
1292 }
1293 } else if (receivedCmd[0] == 0x1a ) // ULC authentication
1294 {
1295
1296 }
1297 else if (receivedCmd[0] == 0x1b) // NTAG / EV-1 authentication
1298 {
1299 if ( tagType == 7 ) {
1300 p_response = &responses[8]; // PACK response
1301 uint32_t pwd = bytes_to_num(receivedCmd+1,4);
1302 Dbprintf("Auth attempt: %08x", pwd);
1303 }
1304 }
1305 else {
1306 // Check for ISO 14443A-4 compliant commands, look at left nibble
1307 switch (receivedCmd[0]) {
1308 case 0x02:
1309 case 0x03: { // IBlock (command no CID)
1310 dynamic_response_info.response[0] = receivedCmd[0];
1311 dynamic_response_info.response[1] = 0x90;
1312 dynamic_response_info.response[2] = 0x00;
1313 dynamic_response_info.response_n = 3;
1314 } break;
1315 case 0x0B:
1316 case 0x0A: { // IBlock (command CID)
1317 dynamic_response_info.response[0] = receivedCmd[0];
1318 dynamic_response_info.response[1] = 0x00;
1319 dynamic_response_info.response[2] = 0x90;
1320 dynamic_response_info.response[3] = 0x00;
1321 dynamic_response_info.response_n = 4;
1322 } break;
1323
1324 case 0x1A:
1325 case 0x1B: { // Chaining command
1326 dynamic_response_info.response[0] = 0xaa | ((receivedCmd[0]) & 1);
1327 dynamic_response_info.response_n = 2;
1328 } break;
1329
1330 case 0xaa:
1331 case 0xbb: {
1332 dynamic_response_info.response[0] = receivedCmd[0] ^ 0x11;
1333 dynamic_response_info.response_n = 2;
1334 } break;
1335
1336 case 0xBA: { // ping / pong
1337 dynamic_response_info.response[0] = 0xAB;
1338 dynamic_response_info.response[1] = 0x00;
1339 dynamic_response_info.response_n = 2;
1340 } break;
1341
1342 case 0xCA:
1343 case 0xC2: { // Readers sends deselect command
1344 dynamic_response_info.response[0] = 0xCA;
1345 dynamic_response_info.response[1] = 0x00;
1346 dynamic_response_info.response_n = 2;
1347 } break;
1348
1349 default: {
1350 // Never seen this command before
1351 if (tracing) {
1352 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1353 }
1354 Dbprintf("Received unknown command (len=%d):",len);
1355 Dbhexdump(len,receivedCmd,false);
1356 // Do not respond
1357 dynamic_response_info.response_n = 0;
1358 } break;
1359 }
1360
1361 if (dynamic_response_info.response_n > 0) {
1362 // Copy the CID from the reader query
1363 dynamic_response_info.response[1] = receivedCmd[1];
1364
1365 // Add CRC bytes, always used in ISO 14443A-4 compliant cards
1366 AppendCrc14443a(dynamic_response_info.response,dynamic_response_info.response_n);
1367 dynamic_response_info.response_n += 2;
1368
1369 if (prepare_tag_modulation(&dynamic_response_info,DYNAMIC_MODULATION_BUFFER_SIZE) == false) {
1370 Dbprintf("Error preparing tag response");
1371 if (tracing) {
1372 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1373 }
1374 break;
1375 }
1376 p_response = &dynamic_response_info;
1377 }
1378 }
1379
1380 // Count number of wakeups received after a halt
1381 if(order == 6 && lastorder == 5) { happened++; }
1382
1383 // Count number of other messages after a halt
1384 if(order != 6 && lastorder == 5) { happened2++; }
1385
1386 if(cmdsRecvd > 999) {
1387 DbpString("1000 commands later...");
1388 break;
1389 }
1390 cmdsRecvd++;
1391
1392 if (p_response != NULL) {
1393 EmSendCmd14443aRaw(p_response->modulation, p_response->modulation_n, receivedCmd[0] == 0x52);
1394 // do the tracing for the previous reader request and this tag answer:
1395 uint8_t par[MAX_PARITY_SIZE];
1396 GetParity(p_response->response, p_response->response_n, par);
1397
1398 EmLogTrace(Uart.output,
1399 Uart.len,
1400 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1401 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1402 Uart.parity,
1403 p_response->response,
1404 p_response->response_n,
1405 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1406 (LastTimeProxToAirStart + p_response->ProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1407 par);
1408 }
1409
1410 if (!tracing) {
1411 Dbprintf("Trace Full. Simulation stopped.");
1412 break;
1413 }
1414 }
1415
1416 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1417 BigBuf_free_keep_EM();
1418 LED_A_OFF();
1419
1420 if (MF_DBGLEVEL >= 4){
1421 Dbprintf("-[ Wake ups after halt [%d]", happened);
1422 Dbprintf("-[ Messages after halt [%d]", happened2);
1423 Dbprintf("-[ Num of received cmd [%d]", cmdsRecvd);
1424 }
1425 }
1426
1427
1428 // prepare a delayed transfer. This simply shifts ToSend[] by a number
1429 // of bits specified in the delay parameter.
1430 void PrepareDelayedTransfer(uint16_t delay)
1431 {
1432 uint8_t bitmask = 0;
1433 uint8_t bits_to_shift = 0;
1434 uint8_t bits_shifted = 0;
1435
1436 delay &= 0x07;
1437 if (delay) {
1438 for (uint16_t i = 0; i < delay; i++) {
1439 bitmask |= (0x01 << i);
1440 }
1441 ToSend[ToSendMax++] = 0x00;
1442 for (uint16_t i = 0; i < ToSendMax; i++) {
1443 bits_to_shift = ToSend[i] & bitmask;
1444 ToSend[i] = ToSend[i] >> delay;
1445 ToSend[i] = ToSend[i] | (bits_shifted << (8 - delay));
1446 bits_shifted = bits_to_shift;
1447 }
1448 }
1449 }
1450
1451
1452 //-------------------------------------------------------------------------------------
1453 // Transmit the command (to the tag) that was placed in ToSend[].
1454 // Parameter timing:
1455 // if NULL: transfer at next possible time, taking into account
1456 // request guard time and frame delay time
1457 // if == 0: transfer immediately and return time of transfer
1458 // if != 0: delay transfer until time specified
1459 //-------------------------------------------------------------------------------------
1460 static void TransmitFor14443a(const uint8_t *cmd, uint16_t len, uint32_t *timing)
1461 {
1462
1463 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
1464
1465 uint32_t ThisTransferTime = 0;
1466
1467 if (timing) {
1468 if(*timing == 0) { // Measure time
1469 *timing = (GetCountSspClk() + 8) & 0xfffffff8;
1470 } else {
1471 PrepareDelayedTransfer(*timing & 0x00000007); // Delay transfer (fine tuning - up to 7 MF clock ticks)
1472 }
1473 if(MF_DBGLEVEL >= 4 && GetCountSspClk() >= (*timing & 0xfffffff8)) Dbprintf("TransmitFor14443a: Missed timing");
1474 while(GetCountSspClk() < (*timing & 0xfffffff8)); // Delay transfer (multiple of 8 MF clock ticks)
1475 LastTimeProxToAirStart = *timing;
1476 } else {
1477 ThisTransferTime = ((MAX(NextTransferTime, GetCountSspClk()) & 0xfffffff8) + 8);
1478 while(GetCountSspClk() < ThisTransferTime);
1479 LastTimeProxToAirStart = ThisTransferTime;
1480 }
1481
1482 // clear TXRDY
1483 AT91C_BASE_SSC->SSC_THR = SEC_Y;
1484
1485 uint16_t c = 0;
1486 for(;;) {
1487 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1488 AT91C_BASE_SSC->SSC_THR = cmd[c];
1489 c++;
1490 if(c >= len) {
1491 break;
1492 }
1493 }
1494 }
1495
1496 NextTransferTime = MAX(NextTransferTime, LastTimeProxToAirStart + REQUEST_GUARD_TIME);
1497 }
1498
1499
1500 //-----------------------------------------------------------------------------
1501 // Prepare reader command (in bits, support short frames) to send to FPGA
1502 //-----------------------------------------------------------------------------
1503 void CodeIso14443aBitsAsReaderPar(const uint8_t *cmd, uint16_t bits, const uint8_t *parity)
1504 {
1505 int i, j;
1506 int last;
1507 uint8_t b;
1508
1509 ToSendReset();
1510
1511 // Start of Communication (Seq. Z)
1512 ToSend[++ToSendMax] = SEC_Z;
1513 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1514 last = 0;
1515
1516 size_t bytecount = nbytes(bits);
1517 // Generate send structure for the data bits
1518 for (i = 0; i < bytecount; i++) {
1519 // Get the current byte to send
1520 b = cmd[i];
1521 size_t bitsleft = MIN((bits-(i*8)),8);
1522
1523 for (j = 0; j < bitsleft; j++) {
1524 if (b & 1) {
1525 // Sequence X
1526 ToSend[++ToSendMax] = SEC_X;
1527 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1528 last = 1;
1529 } else {
1530 if (last == 0) {
1531 // Sequence Z
1532 ToSend[++ToSendMax] = SEC_Z;
1533 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1534 } else {
1535 // Sequence Y
1536 ToSend[++ToSendMax] = SEC_Y;
1537 last = 0;
1538 }
1539 }
1540 b >>= 1;
1541 }
1542
1543 // Only transmit parity bit if we transmitted a complete byte
1544 if (j == 8 && parity != NULL) {
1545 // Get the parity bit
1546 if (parity[i>>3] & (0x80 >> (i&0x0007))) {
1547 // Sequence X
1548 ToSend[++ToSendMax] = SEC_X;
1549 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1550 last = 1;
1551 } else {
1552 if (last == 0) {
1553 // Sequence Z
1554 ToSend[++ToSendMax] = SEC_Z;
1555 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1556 } else {
1557 // Sequence Y
1558 ToSend[++ToSendMax] = SEC_Y;
1559 last = 0;
1560 }
1561 }
1562 }
1563 }
1564
1565 // End of Communication: Logic 0 followed by Sequence Y
1566 if (last == 0) {
1567 // Sequence Z
1568 ToSend[++ToSendMax] = SEC_Z;
1569 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1570 } else {
1571 // Sequence Y
1572 ToSend[++ToSendMax] = SEC_Y;
1573 last = 0;
1574 }
1575 ToSend[++ToSendMax] = SEC_Y;
1576
1577 // Convert to length of command:
1578 ToSendMax++;
1579 }
1580
1581 //-----------------------------------------------------------------------------
1582 // Prepare reader command to send to FPGA
1583 //-----------------------------------------------------------------------------
1584 void CodeIso14443aAsReaderPar(const uint8_t *cmd, uint16_t len, const uint8_t *parity)
1585 {
1586 CodeIso14443aBitsAsReaderPar(cmd, len*8, parity);
1587 }
1588
1589
1590 //-----------------------------------------------------------------------------
1591 // Wait for commands from reader
1592 // Stop when button is pressed (return 1) or field was gone (return 2)
1593 // Or return 0 when command is captured
1594 //-----------------------------------------------------------------------------
1595 static int EmGetCmd(uint8_t *received, uint16_t *len, uint8_t *parity)
1596 {
1597 *len = 0;
1598
1599 uint32_t timer = 0, vtime = 0;
1600 int analogCnt = 0;
1601 int analogAVG = 0;
1602
1603 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
1604 // only, since we are receiving, not transmitting).
1605 // Signal field is off with the appropriate LED
1606 LED_D_OFF();
1607 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1608
1609 // Set ADC to read field strength
1610 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_SWRST;
1611 AT91C_BASE_ADC->ADC_MR =
1612 ADC_MODE_PRESCALE(63) |
1613 ADC_MODE_STARTUP_TIME(1) |
1614 ADC_MODE_SAMPLE_HOLD_TIME(15);
1615 AT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ADC_CHAN_HF);
1616 // start ADC
1617 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1618
1619 // Now run a 'software UART' on the stream of incoming samples.
1620 UartInit(received, parity);
1621
1622 // Clear RXRDY:
1623 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1624
1625 for(;;) {
1626 WDT_HIT();
1627
1628 if (BUTTON_PRESS()) return 1;
1629
1630 // test if the field exists
1631 if (AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ADC_CHAN_HF)) {
1632 analogCnt++;
1633 analogAVG += AT91C_BASE_ADC->ADC_CDR[ADC_CHAN_HF];
1634 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1635 if (analogCnt >= 32) {
1636 if ((MAX_ADC_HF_VOLTAGE * (analogAVG / analogCnt) >> 10) < MF_MINFIELDV) {
1637 vtime = GetTickCount();
1638 if (!timer) timer = vtime;
1639 // 50ms no field --> card to idle state
1640 if (vtime - timer > 50) return 2;
1641 } else
1642 if (timer) timer = 0;
1643 analogCnt = 0;
1644 analogAVG = 0;
1645 }
1646 }
1647
1648 // receive and test the miller decoding
1649 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1650 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1651 if(MillerDecoding(b, 0)) {
1652 *len = Uart.len;
1653 return 0;
1654 }
1655 }
1656
1657 }
1658 }
1659
1660
1661 static int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded)
1662 {
1663 uint8_t b;
1664 uint16_t i = 0;
1665 uint32_t ThisTransferTime;
1666
1667 // Modulate Manchester
1668 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD);
1669
1670 // include correction bit if necessary
1671 if (Uart.parityBits & 0x01) {
1672 correctionNeeded = TRUE;
1673 }
1674 if(correctionNeeded) {
1675 // 1236, so correction bit needed
1676 i = 0;
1677 } else {
1678 i = 1;
1679 }
1680
1681 // clear receiving shift register and holding register
1682 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1683 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1684 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1685 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1686
1687 // wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
1688 for (uint16_t j = 0; j < 5; j++) { // allow timeout - better late than never
1689 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1690 if (AT91C_BASE_SSC->SSC_RHR) break;
1691 }
1692
1693 while ((ThisTransferTime = GetCountSspClk()) & 0x00000007);
1694
1695 // Clear TXRDY:
1696 AT91C_BASE_SSC->SSC_THR = SEC_F;
1697
1698 // send cycle
1699 for(; i < respLen; ) {
1700 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1701 AT91C_BASE_SSC->SSC_THR = resp[i++];
1702 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1703 }
1704
1705 if(BUTTON_PRESS()) break;
1706 }
1707
1708 // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN again:
1709 uint8_t fpga_queued_bits = FpgaSendQueueDelay >> 3;
1710 for (i = 0; i <= fpga_queued_bits/8 + 1; ) {
1711 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1712 AT91C_BASE_SSC->SSC_THR = SEC_F;
1713 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1714 i++;
1715 }
1716 }
1717
1718 LastTimeProxToAirStart = ThisTransferTime + (correctionNeeded?8:0);
1719
1720 return 0;
1721 }
1722
1723 int EmSend4bitEx(uint8_t resp, bool correctionNeeded){
1724 Code4bitAnswerAsTag(resp);
1725 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
1726 // do the tracing for the previous reader request and this tag answer:
1727 uint8_t par[1];
1728 GetParity(&resp, 1, par);
1729 EmLogTrace(Uart.output,
1730 Uart.len,
1731 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1732 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1733 Uart.parity,
1734 &resp,
1735 1,
1736 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1737 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1738 par);
1739 return res;
1740 }
1741
1742 int EmSend4bit(uint8_t resp){
1743 return EmSend4bitEx(resp, false);
1744 }
1745
1746 int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par){
1747 CodeIso14443aAsTagPar(resp, respLen, par);
1748 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
1749 // do the tracing for the previous reader request and this tag answer:
1750 EmLogTrace(Uart.output,
1751 Uart.len,
1752 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1753 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1754 Uart.parity,
1755 resp,
1756 respLen,
1757 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1758 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1759 par);
1760 return res;
1761 }
1762
1763 int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded){
1764 uint8_t par[MAX_PARITY_SIZE];
1765 GetParity(resp, respLen, par);
1766 return EmSendCmdExPar(resp, respLen, correctionNeeded, par);
1767 }
1768
1769 int EmSendCmd(uint8_t *resp, uint16_t respLen){
1770 uint8_t par[MAX_PARITY_SIZE];
1771 GetParity(resp, respLen, par);
1772 return EmSendCmdExPar(resp, respLen, false, par);
1773 }
1774
1775 int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par){
1776 return EmSendCmdExPar(resp, respLen, false, par);
1777 }
1778
1779 bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint8_t *reader_Parity,
1780 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint8_t *tag_Parity)
1781 {
1782 if (tracing) {
1783 // we cannot exactly measure the end and start of a received command from reader. However we know that the delay from
1784 // end of the received command to start of the tag's (simulated by us) answer is n*128+20 or n*128+84 resp.
1785 // with n >= 9. The start of the tags answer can be measured and therefore the end of the received command be calculated:
1786 uint16_t reader_modlen = reader_EndTime - reader_StartTime;
1787 uint16_t approx_fdt = tag_StartTime - reader_EndTime;
1788 uint16_t exact_fdt = (approx_fdt - 20 + 32)/64 * 64 + 20;
1789 reader_EndTime = tag_StartTime - exact_fdt;
1790 reader_StartTime = reader_EndTime - reader_modlen;
1791 if (!LogTrace(reader_data, reader_len, reader_StartTime, reader_EndTime, reader_Parity, TRUE)) {
1792 return FALSE;
1793 } else return(!LogTrace(tag_data, tag_len, tag_StartTime, tag_EndTime, tag_Parity, FALSE));
1794 } else {
1795 return TRUE;
1796 }
1797 }
1798
1799 //-----------------------------------------------------------------------------
1800 // Wait a certain time for tag response
1801 // If a response is captured return TRUE
1802 // If it takes too long return FALSE
1803 //-----------------------------------------------------------------------------
1804 static int GetIso14443aAnswerFromTag(uint8_t *receivedResponse, uint8_t *receivedResponsePar, uint16_t offset)
1805 {
1806 uint32_t c = 0x00;
1807
1808 // Set FPGA mode to "reader listen mode", no modulation (listen
1809 // only, since we are receiving, not transmitting).
1810 // Signal field is on with the appropriate LED
1811 LED_D_ON();
1812 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN);
1813
1814 // Now get the answer from the card
1815 DemodInit(receivedResponse, receivedResponsePar);
1816
1817 // clear RXRDY:
1818 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1819
1820 for(;;) {
1821 WDT_HIT();
1822
1823 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1824 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1825 if(ManchesterDecoding(b, offset, 0)) {
1826 NextTransferTime = MAX(NextTransferTime, Demod.endTime - (DELAY_AIR2ARM_AS_READER + DELAY_ARM2AIR_AS_READER)/16 + FRAME_DELAY_TIME_PICC_TO_PCD);
1827 return TRUE;
1828 } else if (c++ > iso14a_timeout && Demod.state == DEMOD_UNSYNCD) {
1829 return FALSE;
1830 }
1831 }
1832 }
1833 }
1834
1835 void ReaderTransmitBitsPar(uint8_t* frame, uint16_t bits, uint8_t *par, uint32_t *timing)
1836 {
1837 CodeIso14443aBitsAsReaderPar(frame, bits, par);
1838
1839 // Send command to tag
1840 TransmitFor14443a(ToSend, ToSendMax, timing);
1841 if(trigger)
1842 LED_A_ON();
1843
1844 // Log reader command in trace buffer
1845 if (tracing) {
1846 LogTrace(frame, nbytes(bits), LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_READER, (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_READER, par, TRUE);
1847 }
1848 }
1849
1850 void ReaderTransmitPar(uint8_t* frame, uint16_t len, uint8_t *par, uint32_t *timing)
1851 {
1852 ReaderTransmitBitsPar(frame, len*8, par, timing);
1853 }
1854
1855 void ReaderTransmitBits(uint8_t* frame, uint16_t len, uint32_t *timing)
1856 {
1857 // Generate parity and redirect
1858 uint8_t par[MAX_PARITY_SIZE];
1859 GetParity(frame, len/8, par);
1860 ReaderTransmitBitsPar(frame, len, par, timing);
1861 }
1862
1863 void ReaderTransmit(uint8_t* frame, uint16_t len, uint32_t *timing)
1864 {
1865 // Generate parity and redirect
1866 uint8_t par[MAX_PARITY_SIZE];
1867 GetParity(frame, len, par);
1868 ReaderTransmitBitsPar(frame, len*8, par, timing);
1869 }
1870
1871 int ReaderReceiveOffset(uint8_t* receivedAnswer, uint16_t offset, uint8_t *parity)
1872 {
1873 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, offset)) return FALSE;
1874 if (tracing) {
1875 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
1876 }
1877 return Demod.len;
1878 }
1879
1880 int ReaderReceive(uint8_t *receivedAnswer, uint8_t *parity)
1881 {
1882 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, 0)) return FALSE;
1883 if (tracing) {
1884 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
1885 }
1886 return Demod.len;
1887 }
1888
1889 /* performs iso14443a anticollision procedure
1890 * fills the uid pointer unless NULL
1891 * fills resp_data unless NULL */
1892 int iso14443a_select_card(byte_t *uid_ptr, iso14a_card_select_t *p_hi14a_card, uint32_t *cuid_ptr) {
1893 uint8_t wupa[] = { 0x52 }; // 0x26 - REQA 0x52 - WAKE-UP
1894 uint8_t sel_all[] = { 0x93,0x20 };
1895 uint8_t sel_uid[] = { 0x93,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
1896 uint8_t rats[] = { 0xE0,0x80,0x00,0x00 }; // FSD=256, FSDI=8, CID=0
1897 uint8_t resp[MAX_FRAME_SIZE]; // theoretically. A usual RATS will be much smaller
1898 uint8_t resp_par[MAX_PARITY_SIZE];
1899 byte_t uid_resp[4];
1900 size_t uid_resp_len;
1901
1902 uint8_t sak = 0x04; // cascade uid
1903 int cascade_level = 0;
1904 int len;
1905
1906 // Broadcast for a card, WUPA (0x52) will force response from all cards in the field
1907 ReaderTransmitBitsPar(wupa,7,0, NULL);
1908
1909 // Receive the ATQA
1910 if(!ReaderReceive(resp, resp_par)) return 0;
1911
1912 if(p_hi14a_card) {
1913 memcpy(p_hi14a_card->atqa, resp, 2);
1914 p_hi14a_card->uidlen = 0;
1915 memset(p_hi14a_card->uid,0,10);
1916 }
1917
1918 // clear uid
1919 if (uid_ptr) {
1920 memset(uid_ptr,0,10);
1921 }
1922
1923 // check for proprietary anticollision:
1924 if ((resp[0] & 0x1F) == 0) {
1925 return 3;
1926 }
1927
1928 // OK we will select at least at cascade 1, lets see if first byte of UID was 0x88 in
1929 // which case we need to make a cascade 2 request and select - this is a long UID
1930 // While the UID is not complete, the 3nd bit (from the right) is set in the SAK.
1931 for(; sak & 0x04; cascade_level++) {
1932 // SELECT_* (L1: 0x93, L2: 0x95, L3: 0x97)
1933 sel_uid[0] = sel_all[0] = 0x93 + cascade_level * 2;
1934
1935 // SELECT_ALL
1936 ReaderTransmit(sel_all, sizeof(sel_all), NULL);
1937 if (!ReaderReceive(resp, resp_par)) return 0;
1938
1939 if (Demod.collisionPos) { // we had a collision and need to construct the UID bit by bit
1940 memset(uid_resp, 0, 4);
1941 uint16_t uid_resp_bits = 0;
1942 uint16_t collision_answer_offset = 0;
1943 // anti-collision-loop:
1944 while (Demod.collisionPos) {
1945 Dbprintf("Multiple tags detected. Collision after Bit %d", Demod.collisionPos);
1946 for (uint16_t i = collision_answer_offset; i < Demod.collisionPos; i++, uid_resp_bits++) { // add valid UID bits before collision point
1947 uint16_t UIDbit = (resp[i/8] >> (i % 8)) & 0x01;
1948 uid_resp[uid_resp_bits / 8] |= UIDbit << (uid_resp_bits % 8);
1949 }
1950 uid_resp[uid_resp_bits/8] |= 1 << (uid_resp_bits % 8); // next time select the card(s) with a 1 in the collision position
1951 uid_resp_bits++;
1952 // construct anticollosion command:
1953 sel_uid[1] = ((2 + uid_resp_bits/8) << 4) | (uid_resp_bits & 0x07); // length of data in bytes and bits
1954 for (uint16_t i = 0; i <= uid_resp_bits/8; i++) {
1955 sel_uid[2+i] = uid_resp[i];
1956 }
1957 collision_answer_offset = uid_resp_bits%8;
1958 ReaderTransmitBits(sel_uid, 16 + uid_resp_bits, NULL);
1959 if (!ReaderReceiveOffset(resp, collision_answer_offset, resp_par)) return 0;
1960 }
1961 // finally, add the last bits and BCC of the UID
1962 for (uint16_t i = collision_answer_offset; i < (Demod.len-1)*8; i++, uid_resp_bits++) {
1963 uint16_t UIDbit = (resp[i/8] >> (i%8)) & 0x01;
1964 uid_resp[uid_resp_bits/8] |= UIDbit << (uid_resp_bits % 8);
1965 }
1966
1967 } else { // no collision, use the response to SELECT_ALL as current uid
1968 memcpy(uid_resp, resp, 4);
1969 }
1970 uid_resp_len = 4;
1971
1972 // calculate crypto UID. Always use last 4 Bytes.
1973 if(cuid_ptr) {
1974 *cuid_ptr = bytes_to_num(uid_resp, 4);
1975 }
1976
1977 // Construct SELECT UID command
1978 sel_uid[1] = 0x70; // transmitting a full UID (1 Byte cmd, 1 Byte NVB, 4 Byte UID, 1 Byte BCC, 2 Bytes CRC)
1979 memcpy(sel_uid+2, uid_resp, 4); // the UID
1980 sel_uid[6] = sel_uid[2] ^ sel_uid[3] ^ sel_uid[4] ^ sel_uid[5]; // calculate and add BCC
1981 AppendCrc14443a(sel_uid, 7); // calculate and add CRC
1982 ReaderTransmit(sel_uid, sizeof(sel_uid), NULL);
1983
1984 // Receive the SAK
1985 if (!ReaderReceive(resp, resp_par)) return 0;
1986 sak = resp[0];
1987
1988 // Test if more parts of the uid are coming
1989 if ((sak & 0x04) /* && uid_resp[0] == 0x88 */) {
1990 // Remove first byte, 0x88 is not an UID byte, it CT, see page 3 of:
1991 // http://www.nxp.com/documents/application_note/AN10927.pdf
1992 uid_resp[0] = uid_resp[1];
1993 uid_resp[1] = uid_resp[2];
1994 uid_resp[2] = uid_resp[3];
1995
1996 uid_resp_len = 3;
1997 }
1998
1999 if(uid_ptr) {
2000 memcpy(uid_ptr + (cascade_level*3), uid_resp, uid_resp_len);
2001 }
2002
2003 if(p_hi14a_card) {
2004 memcpy(p_hi14a_card->uid + (cascade_level*3), uid_resp, uid_resp_len);
2005 p_hi14a_card->uidlen += uid_resp_len;
2006 }
2007 }
2008
2009 if(p_hi14a_card) {
2010 p_hi14a_card->sak = sak;
2011 p_hi14a_card->ats_len = 0;
2012 }
2013
2014 // non iso14443a compliant tag
2015 if( (sak & 0x20) == 0) return 2;
2016
2017 // Request for answer to select
2018 AppendCrc14443a(rats, 2);
2019 ReaderTransmit(rats, sizeof(rats), NULL);
2020
2021 if (!(len = ReaderReceive(resp, resp_par))) return 0;
2022
2023
2024 if(p_hi14a_card) {
2025 memcpy(p_hi14a_card->ats, resp, sizeof(p_hi14a_card->ats));
2026 p_hi14a_card->ats_len = len;
2027 }
2028
2029 // reset the PCB block number
2030 iso14_pcb_blocknum = 0;
2031
2032 // set default timeout based on ATS
2033 iso14a_set_ATS_timeout(resp);
2034
2035 return 1;
2036 }
2037
2038 void iso14443a_setup(uint8_t fpga_minor_mode) {
2039 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
2040 // Set up the synchronous serial port
2041 FpgaSetupSsc();
2042 // connect Demodulated Signal to ADC:
2043 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
2044
2045 // Signal field is on with the appropriate LED
2046 if (fpga_minor_mode == FPGA_HF_ISO14443A_READER_MOD
2047 || fpga_minor_mode == FPGA_HF_ISO14443A_READER_LISTEN) {
2048 LED_D_ON();
2049 } else {
2050 LED_D_OFF();
2051 }
2052 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | fpga_minor_mode);
2053
2054 // Start the timer
2055 StartCountSspClk();
2056
2057 DemodReset();
2058 UartReset();
2059 NextTransferTime = 2*DELAY_ARM2AIR_AS_READER;
2060 iso14a_set_timeout(10*106); // 10ms default
2061 }
2062
2063 int iso14_apdu(uint8_t *cmd, uint16_t cmd_len, void *data) {
2064 uint8_t parity[MAX_PARITY_SIZE];
2065 uint8_t real_cmd[cmd_len+4];
2066 real_cmd[0] = 0x0a; //I-Block
2067 // put block number into the PCB
2068 real_cmd[0] |= iso14_pcb_blocknum;
2069 real_cmd[1] = 0x00; //CID: 0 //FIXME: allow multiple selected cards
2070 memcpy(real_cmd+2, cmd, cmd_len);
2071 AppendCrc14443a(real_cmd,cmd_len+2);
2072
2073 ReaderTransmit(real_cmd, cmd_len+4, NULL);
2074 size_t len = ReaderReceive(data, parity);
2075 uint8_t *data_bytes = (uint8_t *) data;
2076 if (!len)
2077 return 0; //DATA LINK ERROR
2078 // if we received an I- or R(ACK)-Block with a block number equal to the
2079 // current block number, toggle the current block number
2080 else if (len >= 4 // PCB+CID+CRC = 4 bytes
2081 && ((data_bytes[0] & 0xC0) == 0 // I-Block
2082 || (data_bytes[0] & 0xD0) == 0x80) // R-Block with ACK bit set to 0
2083 && (data_bytes[0] & 0x01) == iso14_pcb_blocknum) // equal block numbers
2084 {
2085 iso14_pcb_blocknum ^= 1;
2086 }
2087
2088 return len;
2089 }
2090
2091 //-----------------------------------------------------------------------------
2092 // Read an ISO 14443a tag. Send out commands and store answers.
2093 //
2094 //-----------------------------------------------------------------------------
2095 void ReaderIso14443a(UsbCommand *c)
2096 {
2097 iso14a_command_t param = c->arg[0];
2098 uint8_t *cmd = c->d.asBytes;
2099 size_t len = c->arg[1] & 0xffff;
2100 size_t lenbits = c->arg[1] >> 16;
2101 uint32_t timeout = c->arg[2];
2102 uint32_t arg0 = 0;
2103 byte_t buf[USB_CMD_DATA_SIZE];
2104 uint8_t par[MAX_PARITY_SIZE];
2105
2106 if(param & ISO14A_CONNECT) {
2107 clear_trace();
2108 }
2109
2110 set_tracing(TRUE);
2111
2112 if(param & ISO14A_REQUEST_TRIGGER) {
2113 iso14a_set_trigger(TRUE);
2114 }
2115
2116 if(param & ISO14A_CONNECT) {
2117 iso14443a_setup(FPGA_HF_ISO14443A_READER_LISTEN);
2118 if(!(param & ISO14A_NO_SELECT)) {
2119 iso14a_card_select_t *card = (iso14a_card_select_t*)buf;
2120 arg0 = iso14443a_select_card(NULL,card,NULL);
2121 cmd_send(CMD_ACK,arg0,card->uidlen,0,buf,sizeof(iso14a_card_select_t));
2122 }
2123 }
2124
2125 if(param & ISO14A_SET_TIMEOUT) {
2126 iso14a_set_timeout(timeout);
2127 }
2128
2129 if(param & ISO14A_APDU) {
2130 arg0 = iso14_apdu(cmd, len, buf);
2131 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
2132 }
2133
2134 if(param & ISO14A_RAW) {
2135 if(param & ISO14A_APPEND_CRC) {
2136 if(param & ISO14A_TOPAZMODE) {
2137 AppendCrc14443b(cmd,len);
2138 } else {
2139 AppendCrc14443a(cmd,len);
2140 }
2141 len += 2;
2142 if (lenbits) lenbits += 16;
2143 }
2144 if(lenbits>0) { // want to send a specific number of bits (e.g. short commands)
2145 if(param & ISO14A_TOPAZMODE) {
2146 int bits_to_send = lenbits;
2147 uint16_t i = 0;
2148 ReaderTransmitBitsPar(&cmd[i++], MIN(bits_to_send, 7), NULL, NULL); // first byte is always short (7bits) and no parity
2149 bits_to_send -= 7;
2150 while (bits_to_send > 0) {
2151 ReaderTransmitBitsPar(&cmd[i++], MIN(bits_to_send, 8), NULL, NULL); // following bytes are 8 bit and no parity
2152 bits_to_send -= 8;
2153 }
2154 } else {
2155 GetParity(cmd, lenbits/8, par);
2156 ReaderTransmitBitsPar(cmd, lenbits, par, NULL); // bytes are 8 bit with odd parity
2157 }
2158 } else { // want to send complete bytes only
2159 if(param & ISO14A_TOPAZMODE) {
2160 uint16_t i = 0;
2161 ReaderTransmitBitsPar(&cmd[i++], 7, NULL, NULL); // first byte: 7 bits, no paritiy
2162 while (i < len) {
2163 ReaderTransmitBitsPar(&cmd[i++], 8, NULL, NULL); // following bytes: 8 bits, no paritiy
2164 }
2165 } else {
2166 ReaderTransmit(cmd,len, NULL); // 8 bits, odd parity
2167 }
2168 }
2169 arg0 = ReaderReceive(buf, par);
2170 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
2171 }
2172
2173 if(param & ISO14A_REQUEST_TRIGGER) {
2174 iso14a_set_trigger(FALSE);
2175 }
2176
2177 if(param & ISO14A_NO_DISCONNECT) {
2178 return;
2179 }
2180
2181 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2182 LEDsoff();
2183 }
2184
2185
2186 // Determine the distance between two nonces.
2187 // Assume that the difference is small, but we don't know which is first.
2188 // Therefore try in alternating directions.
2189 int32_t dist_nt(uint32_t nt1, uint32_t nt2) {
2190
2191 uint16_t i;
2192 uint32_t nttmp1, nttmp2;
2193
2194 if (nt1 == nt2) return 0;
2195
2196 nttmp1 = nt1;
2197 nttmp2 = nt2;
2198
2199 for (i = 1; i < 0xFFFF; i++) {
2200 nttmp1 = prng_successor(nttmp1, 1);
2201 if (nttmp1 == nt2) return i;
2202 nttmp2 = prng_successor(nttmp2, 1);
2203 if (nttmp2 == nt1) return -i;
2204 }
2205
2206 return(-99999); // either nt1 or nt2 are invalid nonces
2207 }
2208
2209 int32_t dist_nt_ex32(uint32_t nt1, uint32_t nt2, bool *result) {
2210
2211 uint16_t i;
2212 uint32_t nttmp1, nttmp2;
2213
2214 if (nt1 == nt2) return 0;
2215
2216 nttmp1 = nt1;
2217 nttmp2 = nt2;
2218
2219 *result = true;
2220 for (i = 1; i < 0xFFFFFFFF; i++) {
2221 nttmp1 = prng_successor(nttmp1, 1);
2222 if (nttmp1 == nt2) return i;
2223
2224 nttmp2 = prng_successor(nttmp2, 1);
2225 if (nttmp2 == nt1) return -i;
2226 }
2227
2228 *result = false;
2229 return(-99999); // either nt1 or nt2 are invalid nonces
2230 }
2231
2232 //-----------------------------------------------------------------------------
2233 // Recover several bits of the cypher stream. This implements (first stages of)
2234 // the algorithm described in "The Dark Side of Security by Obscurity and
2235 // Cloning MiFare Classic Rail and Building Passes, Anywhere, Anytime"
2236 // (article by Nicolas T. Courtois, 2009)
2237 //-----------------------------------------------------------------------------
2238 void ReaderMifare(bool first_try)
2239 {
2240 // Mifare AUTH
2241 uint8_t mf_auth[] = { 0x60,0x00,0xf5,0x7b };
2242 uint8_t mf_nr_ar[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 };
2243 static uint8_t mf_nr_ar3;
2244
2245 uint8_t receivedAnswer[MAX_MIFARE_FRAME_SIZE];
2246 uint8_t receivedAnswerPar[MAX_MIFARE_PARITY_SIZE];
2247
2248 if (first_try) {
2249 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD);
2250 }
2251
2252 // free eventually allocated BigBuf memory. We want all for tracing.
2253 BigBuf_free();
2254
2255 clear_trace();
2256 set_tracing(TRUE);
2257
2258 byte_t nt_diff = 0;
2259 uint8_t par[1] = {0}; // maximum 8 Bytes to be sent here, 1 byte parity is therefore enough
2260 static byte_t par_low = 0;
2261 bool led_on = TRUE;
2262 uint8_t uid[10] ={0};
2263 uint32_t cuid;
2264
2265 uint32_t nt = 0;
2266 uint32_t previous_nt = 0;
2267 static uint32_t nt_attacked = 0;
2268 byte_t par_list[8] = {0x00};
2269 byte_t ks_list[8] = {0x00};
2270
2271 #define PRNG_SEQUENCE_LENGTH (1 << 16);
2272 static uint32_t sync_time = 0;
2273 static uint32_t sync_cycles = 0;
2274 int catch_up_cycles = 0;
2275 int last_catch_up = 0;
2276 uint16_t consecutive_resyncs = 0;
2277 int isOK = 0;
2278
2279 if (first_try) {
2280 mf_nr_ar3 = 0;
2281 sync_time = GetCountSspClk() & 0xfffffff8;
2282 sync_cycles = PRNG_SEQUENCE_LENGTH; //65536; //0x10000 // theory: Mifare Classic's random generator repeats every 2^16 cycles (and so do the nonces).
2283 nt_attacked = 0;
2284 nt = 0;
2285 par[0] = 0;
2286 }
2287 else {
2288 // we were unsuccessful on a previous call. Try another READER nonce (first 3 parity bits remain the same)
2289 mf_nr_ar3++;
2290 mf_nr_ar[3] = mf_nr_ar3;
2291 par[0] = par_low;
2292 }
2293
2294 LED_A_ON();
2295 LED_B_OFF();
2296 LED_C_OFF();
2297
2298
2299 #define MAX_UNEXPECTED_RANDOM 5 // maximum number of unexpected (i.e. real) random numbers when trying to sync. Then give up.
2300 #define MAX_SYNC_TRIES 16
2301 uint16_t unexpected_random = 0;
2302 uint16_t sync_tries = 0;
2303 int16_t debug_info_nr = -1;
2304 uint32_t debug_info[MAX_SYNC_TRIES];
2305
2306 for(uint16_t i = 0; TRUE; i++) {
2307
2308 LED_C_ON();
2309 WDT_HIT();
2310
2311 // Test if the action was cancelled
2312 if(BUTTON_PRESS()) {
2313 isOK = -1;
2314 break;
2315 }
2316
2317 if(!iso14443a_select_card(uid, NULL, &cuid)) {
2318 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Can't select card");
2319 continue;
2320 }
2321
2322 if (debug_info_nr == -1) {
2323 sync_time = (sync_time & 0xfffffff8) + sync_cycles + catch_up_cycles;
2324 catch_up_cycles = 0;
2325
2326 // if we missed the sync time already, advance to the next nonce repeat
2327 while(GetCountSspClk() > sync_time) {
2328 sync_time = (sync_time & 0xfffffff8) + sync_cycles;
2329 }
2330
2331 // Transmit MIFARE_CLASSIC_AUTH at synctime. Should result in returning the same tag nonce (== nt_attacked)
2332 ReaderTransmit(mf_auth, sizeof(mf_auth), &sync_time);
2333 } else {
2334 ReaderTransmit(mf_auth, sizeof(mf_auth), NULL);
2335 }
2336
2337 // Receive the (4 Byte) "random" nonce
2338 if (!ReaderReceive(receivedAnswer, receivedAnswerPar)) {
2339 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Couldn't receive tag nonce");
2340 continue;
2341 }
2342
2343 previous_nt = nt;
2344 nt = bytes_to_num(receivedAnswer, 4);
2345
2346 // Transmit reader nonce with fake par
2347 ReaderTransmitPar(mf_nr_ar, sizeof(mf_nr_ar), par, NULL);
2348
2349 if (first_try && previous_nt && !nt_attacked) { // we didn't calibrate our clock yet
2350 int nt_distance = dist_nt(previous_nt, nt);
2351 if (nt_distance == 0) {
2352 nt_attacked = nt;
2353 } else {
2354 if (nt_distance == -99999) { // invalid nonce received
2355 unexpected_random++;
2356 if (!nt_attacked && unexpected_random > MAX_UNEXPECTED_RANDOM) {
2357 isOK = -3; // Card has an unpredictable PRNG. Give up
2358 break;
2359 } else {
2360 continue; // continue trying...
2361 }
2362 }
2363 if (++sync_tries > MAX_SYNC_TRIES) {
2364 if (sync_tries > 2 * MAX_SYNC_TRIES) {
2365 isOK = -4; // Card's PRNG runs at an unexpected frequency or resets unexpectedly
2366 break;
2367 } else { // continue for a while, just to collect some debug info
2368 debug_info[++debug_info_nr] = nt_distance;
2369 continue;
2370 }
2371 }
2372 sync_cycles = (sync_cycles - nt_distance);
2373 if (sync_cycles <= 0) {
2374 sync_cycles += PRNG_SEQUENCE_LENGTH;
2375 }
2376 if (MF_DBGLEVEL >= 3) {
2377 Dbprintf("calibrating in cycle %d. nt_distance=%d, Sync_cycles: %d\n", i, nt_distance, sync_cycles);
2378 }
2379 continue;
2380 }
2381 }
2382
2383 if ((nt != nt_attacked) && nt_attacked) { // we somehow lost sync. Try to catch up again...
2384 catch_up_cycles = -dist_nt(nt_attacked, nt);
2385 if (catch_up_cycles == 99999) { // invalid nonce received. Don't resync on that one.
2386 catch_up_cycles = 0;
2387 continue;
2388 }
2389 if (catch_up_cycles == last_catch_up) {
2390 consecutive_resyncs++;
2391 }
2392 else {
2393 last_catch_up = catch_up_cycles;
2394 consecutive_resyncs = 0;
2395 }
2396 if (consecutive_resyncs < 3) {
2397 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d. nt_distance=%d. Consecutive Resyncs = %d. Trying one time catch up...\n", i, -catch_up_cycles, consecutive_resyncs);
2398 }
2399 else {
2400 sync_cycles = sync_cycles + catch_up_cycles;
2401 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d for the fourth time consecutively (nt_distance = %d). Adjusting sync_cycles to %d.\n", i, -catch_up_cycles, sync_cycles);
2402 }
2403 continue;
2404 }
2405
2406 consecutive_resyncs = 0;
2407
2408 // Receive answer. This will be a 4 Bit NACK when the 8 parity bits are OK after decoding
2409 if (ReaderReceive(receivedAnswer, receivedAnswerPar))
2410 {
2411 catch_up_cycles = 8; // the PRNG is delayed by 8 cycles due to the NAC (4Bits = 0x05 encrypted) transfer
2412
2413 if (nt_diff == 0)
2414 {
2415 par_low = par[0] & 0xE0; // there is no need to check all parities for other nt_diff. Parity Bits for mf_nr_ar[0..2] won't change
2416 }
2417
2418 led_on = !led_on;
2419 if(led_on) LED_B_ON(); else LED_B_OFF();
2420
2421 par_list[nt_diff] = SwapBits(par[0], 8);
2422 ks_list[nt_diff] = receivedAnswer[0] ^ 0x05;
2423
2424 // Test if the information is complete
2425 if (nt_diff == 0x07) {
2426 isOK = 1;
2427 break;
2428 }
2429
2430 nt_diff = (nt_diff + 1) & 0x07;
2431 mf_nr_ar[3] = (mf_nr_ar[3] & 0x1F) | (nt_diff << 5);
2432 par[0] = par_low;
2433 } else {
2434 if (nt_diff == 0 && first_try)
2435 {
2436 par[0]++;
2437 if (par[0] == 0x00) { // tried all 256 possible parities without success. Card doesn't send NACK.
2438 isOK = -2;
2439 break;
2440 }
2441 } else {
2442 par[0] = ((par[0] & 0x1F) + 1) | par_low;
2443 }
2444 }
2445 }
2446
2447
2448 mf_nr_ar[3] &= 0x1F;
2449
2450 if (isOK == -4) {
2451 if (MF_DBGLEVEL >= 3) {
2452 for(uint16_t i = 0; i < MAX_SYNC_TRIES; i++) {
2453 Dbprintf("collected debug info[%d] = %d\n", i, debug_info[i]);
2454 }
2455 }
2456 }
2457
2458 byte_t buf[28];
2459 memcpy(buf + 0, uid, 4);
2460 num_to_bytes(nt, 4, buf + 4);
2461 memcpy(buf + 8, par_list, 8);
2462 memcpy(buf + 16, ks_list, 8);
2463 memcpy(buf + 24, mf_nr_ar, 4);
2464
2465 cmd_send(CMD_ACK,isOK,0,0,buf,28);
2466
2467 // Thats it...
2468 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2469 LEDsoff();
2470
2471 set_tracing(FALSE);
2472 }
2473
2474 /**
2475 *MIFARE 1K simulate.
2476 *
2477 *@param flags :
2478 * FLAG_INTERACTIVE - In interactive mode, we are expected to finish the operation with an ACK
2479 * 4B_FLAG_UID_IN_DATA - means that there is a 4-byte UID in the data-section, we're expected to use that
2480 * 7B_FLAG_UID_IN_DATA - means that there is a 7-byte UID in the data-section, we're expected to use that
2481 * FLAG_NR_AR_ATTACK - means we should collect NR_AR responses for bruteforcing later
2482 *@param exitAfterNReads, exit simulation after n blocks have been read, 0 is inifite
2483 */
2484 void Mifare1ksim(uint8_t flags, uint8_t exitAfterNReads, uint8_t arg2, uint8_t *datain)
2485 {
2486 int cardSTATE = MFEMUL_NOFIELD;
2487 int _7BUID = 0;
2488 int vHf = 0; // in mV
2489 int res;
2490 uint32_t selTimer = 0;
2491 uint32_t authTimer = 0;
2492 uint16_t len = 0;
2493 uint8_t cardWRBL = 0;
2494 uint8_t cardAUTHSC = 0;
2495 uint8_t cardAUTHKEY = 0xff; // no authentication
2496 // uint32_t cardRr = 0;
2497 uint32_t cuid = 0;
2498 //uint32_t rn_enc = 0;
2499 uint32_t ans = 0;
2500 uint32_t cardINTREG = 0;
2501 uint8_t cardINTBLOCK = 0;
2502 struct Crypto1State mpcs = {0, 0};
2503 struct Crypto1State *pcs;
2504 pcs = &mpcs;
2505 uint32_t numReads = 0;//Counts numer of times reader read a block
2506 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE];
2507 uint8_t receivedCmd_par[MAX_MIFARE_PARITY_SIZE];
2508 uint8_t response[MAX_MIFARE_FRAME_SIZE];
2509 uint8_t response_par[MAX_MIFARE_PARITY_SIZE];
2510
2511 uint8_t rATQA[] = {0x04, 0x00}; // Mifare classic 1k 4BUID
2512 uint8_t rUIDBCC1[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2513 uint8_t rUIDBCC2[] = {0xde, 0xad, 0xbe, 0xaf, 0x62}; // !!!
2514 //uint8_t rSAK[] = {0x08, 0xb6, 0xdd}; // Mifare Classic
2515 uint8_t rSAK[] = {0x09, 0x3f, 0xcc }; // Mifare Mini
2516 uint8_t rSAK1[] = {0x04, 0xda, 0x17};
2517
2518 uint8_t rAUTH_NT[] = {0x01, 0x01, 0x01, 0x01};
2519 uint8_t rAUTH_AT[] = {0x00, 0x00, 0x00, 0x00};
2520
2521 //Here, we collect UID,NT,AR,NR,UID2,NT2,AR2,NR2
2522 // This can be used in a reader-only attack.
2523 // (it can also be retrieved via 'hf 14a list', but hey...
2524 uint32_t ar_nr_responses[] = {0,0,0,0,0,0,0,0,0,0};
2525 uint8_t ar_nr_collected = 0;
2526
2527 // Authenticate response - nonce
2528 uint32_t nonce = bytes_to_num(rAUTH_NT, 4);
2529
2530 //-- Determine the UID
2531 // Can be set from emulator memory, incoming data
2532 // and can be 7 or 4 bytes long
2533 if (flags & FLAG_4B_UID_IN_DATA)
2534 {
2535 // 4B uid comes from data-portion of packet
2536 memcpy(rUIDBCC1,datain,4);
2537 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2538
2539 } else if (flags & FLAG_7B_UID_IN_DATA) {
2540 // 7B uid comes from data-portion of packet
2541 memcpy(&rUIDBCC1[1],datain,3);
2542 memcpy(rUIDBCC2, datain+3, 4);
2543 _7BUID = true;
2544 } else {
2545 // get UID from emul memory
2546 emlGetMemBt(receivedCmd, 7, 1);
2547 _7BUID = !(receivedCmd[0] == 0x00);
2548 if (!_7BUID) { // ---------- 4BUID
2549 emlGetMemBt(rUIDBCC1, 0, 4);
2550 } else { // ---------- 7BUID
2551 emlGetMemBt(&rUIDBCC1[1], 0, 3);
2552 emlGetMemBt(rUIDBCC2, 3, 4);
2553 }
2554 }
2555
2556 // save uid.
2557 ar_nr_responses[0*5] = bytes_to_num(rUIDBCC1+1, 3);
2558 if ( _7BUID )
2559 ar_nr_responses[0*5+1] = bytes_to_num(rUIDBCC2, 4);
2560
2561 /*
2562 * Regardless of what method was used to set the UID, set fifth byte and modify
2563 * the ATQA for 4 or 7-byte UID
2564 */
2565 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2566 if (_7BUID) {
2567 rATQA[0] = 0x44;
2568 rUIDBCC1[0] = 0x88;
2569 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2570 rUIDBCC2[4] = rUIDBCC2[0] ^ rUIDBCC2[1] ^ rUIDBCC2[2] ^ rUIDBCC2[3];
2571 }
2572
2573 if (MF_DBGLEVEL >= 1) {
2574 if (!_7BUID) {
2575 Dbprintf("4B UID: %02x%02x%02x%02x",
2576 rUIDBCC1[0], rUIDBCC1[1], rUIDBCC1[2], rUIDBCC1[3]);
2577 } else {
2578 Dbprintf("7B UID: (%02x)%02x%02x%02x%02x%02x%02x%02x",
2579 rUIDBCC1[0], rUIDBCC1[1], rUIDBCC1[2], rUIDBCC1[3],
2580 rUIDBCC2[0], rUIDBCC2[1] ,rUIDBCC2[2], rUIDBCC2[3]);
2581 }
2582 }
2583
2584 // We need to listen to the high-frequency, peak-detected path.
2585 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
2586
2587 // free eventually allocated BigBuf memory but keep Emulator Memory
2588 BigBuf_free_keep_EM();
2589
2590 // clear trace
2591 clear_trace();
2592 set_tracing(TRUE);
2593
2594
2595 bool finished = FALSE;
2596 while (!BUTTON_PRESS() && !finished) {
2597 WDT_HIT();
2598
2599 // find reader field
2600 if (cardSTATE == MFEMUL_NOFIELD) {
2601 vHf = (MAX_ADC_HF_VOLTAGE * AvgAdc(ADC_CHAN_HF)) >> 10;
2602 if (vHf > MF_MINFIELDV) {
2603 cardSTATE_TO_IDLE();
2604 LED_A_ON();
2605 }
2606 }
2607 if(cardSTATE == MFEMUL_NOFIELD) continue;
2608
2609 //Now, get data
2610 res = EmGetCmd(receivedCmd, &len, receivedCmd_par);
2611 if (res == 2) { //Field is off!
2612 cardSTATE = MFEMUL_NOFIELD;
2613 LEDsoff();
2614 continue;
2615 } else if (res == 1) {
2616 break; //return value 1 means button press
2617 }
2618
2619 // REQ or WUP request in ANY state and WUP in HALTED state
2620 if (len == 1 && ((receivedCmd[0] == 0x26 && cardSTATE != MFEMUL_HALTED) || receivedCmd[0] == 0x52)) {
2621 selTimer = GetTickCount();
2622 EmSendCmdEx(rATQA, sizeof(rATQA), (receivedCmd[0] == 0x52));
2623 cardSTATE = MFEMUL_SELECT1;
2624
2625 // init crypto block
2626 LED_B_OFF();
2627 LED_C_OFF();
2628 crypto1_destroy(pcs);
2629 cardAUTHKEY = 0xff;
2630 continue;
2631 }
2632
2633 switch (cardSTATE) {
2634 case MFEMUL_NOFIELD:
2635 case MFEMUL_HALTED:
2636 case MFEMUL_IDLE:{
2637 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2638 break;
2639 }
2640 case MFEMUL_SELECT1:{
2641 // select all
2642 if (len == 2 && (receivedCmd[0] == 0x93 && receivedCmd[1] == 0x20)) {
2643 if (MF_DBGLEVEL >= 4) Dbprintf("SELECT ALL received");
2644 EmSendCmd(rUIDBCC1, sizeof(rUIDBCC1));
2645 break;
2646 }
2647
2648 if (MF_DBGLEVEL >= 4 && len == 9 && receivedCmd[0] == 0x93 && receivedCmd[1] == 0x70 )
2649 {
2650 Dbprintf("SELECT %02x%02x%02x%02x received",receivedCmd[2],receivedCmd[3],receivedCmd[4],receivedCmd[5]);
2651 }
2652 // select card
2653 if (len == 9 &&
2654 (receivedCmd[0] == 0x93 && receivedCmd[1] == 0x70 && memcmp(&receivedCmd[2], rUIDBCC1, 4) == 0)) {
2655 EmSendCmd(_7BUID?rSAK1:rSAK, _7BUID?sizeof(rSAK1):sizeof(rSAK));
2656 cuid = bytes_to_num(rUIDBCC1, 4);
2657 if (!_7BUID) {
2658 cardSTATE = MFEMUL_WORK;
2659 LED_B_ON();
2660 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol1 time: %d", GetTickCount() - selTimer);
2661 break;
2662 } else {
2663 cardSTATE = MFEMUL_SELECT2;
2664 }
2665 }
2666 break;
2667 }
2668 case MFEMUL_AUTH1:{
2669 if( len != 8)
2670 {
2671 cardSTATE_TO_IDLE();
2672 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2673 break;
2674 }
2675
2676 uint32_t ar = bytes_to_num(receivedCmd, 4);
2677 uint32_t nr = bytes_to_num(&receivedCmd[4], 4);
2678
2679 //Collect AR/NR
2680 //if(ar_nr_collected < 2 && cardAUTHSC == 2){
2681 if(ar_nr_collected < 2){
2682 if(ar_nr_responses[2] != ar)
2683 {// Avoid duplicates... probably not necessary, ar should vary.
2684 //ar_nr_responses[ar_nr_collected*5] = 0;
2685 //ar_nr_responses[ar_nr_collected*5+1] = 0;
2686 ar_nr_responses[ar_nr_collected*5+2] = nonce;
2687 ar_nr_responses[ar_nr_collected*5+3] = nr;
2688 ar_nr_responses[ar_nr_collected*5+4] = ar;
2689 ar_nr_collected++;
2690 }
2691 // Interactive mode flag, means we need to send ACK
2692 if(flags & FLAG_INTERACTIVE && ar_nr_collected == 2)
2693 {
2694 finished = true;
2695 }
2696 }
2697
2698 // --- crypto
2699 //crypto1_word(pcs, ar , 1);
2700 //cardRr = nr ^ crypto1_word(pcs, 0, 0);
2701
2702 //test if auth OK
2703 //if (cardRr != prng_successor(nonce, 64)){
2704
2705 //if (MF_DBGLEVEL >= 4) Dbprintf("AUTH FAILED for sector %d with key %c. cardRr=%08x, succ=%08x",
2706 // cardAUTHSC, cardAUTHKEY == 0 ? 'A' : 'B',
2707 // cardRr, prng_successor(nonce, 64));
2708 // Shouldn't we respond anything here?
2709 // Right now, we don't nack or anything, which causes the
2710 // reader to do a WUPA after a while. /Martin
2711 // -- which is the correct response. /piwi
2712 //cardSTATE_TO_IDLE();
2713 //LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2714 //break;
2715 //}
2716
2717 ans = prng_successor(nonce, 96) ^ crypto1_word(pcs, 0, 0);
2718
2719 num_to_bytes(ans, 4, rAUTH_AT);
2720 // --- crypto
2721 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2722 LED_C_ON();
2723 cardSTATE = MFEMUL_WORK;
2724 if (MF_DBGLEVEL >= 4) Dbprintf("AUTH COMPLETED for sector %d with key %c. time=%d",
2725 cardAUTHSC, cardAUTHKEY == 0 ? 'A' : 'B',
2726 GetTickCount() - authTimer);
2727 break;
2728 }
2729 case MFEMUL_SELECT2:{
2730 if (!len) {
2731 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2732 break;
2733 }
2734 if (len == 2 && (receivedCmd[0] == 0x95 && receivedCmd[1] == 0x20)) {
2735 EmSendCmd(rUIDBCC2, sizeof(rUIDBCC2));
2736 break;
2737 }
2738
2739 // select 2 card
2740 if (len == 9 &&
2741 (receivedCmd[0] == 0x95 && receivedCmd[1] == 0x70 && memcmp(&receivedCmd[2], rUIDBCC2, 4) == 0)) {
2742 EmSendCmd(rSAK, sizeof(rSAK));
2743 cuid = bytes_to_num(rUIDBCC2, 4);
2744 cardSTATE = MFEMUL_WORK;
2745 LED_B_ON();
2746 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol2 time: %d", GetTickCount() - selTimer);
2747 break;
2748 }
2749
2750 // i guess there is a command). go into the work state.
2751 if (len != 4) {
2752 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2753 break;
2754 }
2755 cardSTATE = MFEMUL_WORK;
2756 //goto lbWORK;
2757 //intentional fall-through to the next case-stmt
2758 }
2759
2760 case MFEMUL_WORK:{
2761 if (len == 0) {
2762 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2763 break;
2764 }
2765
2766 bool encrypted_data = (cardAUTHKEY != 0xFF) ;
2767
2768 if(encrypted_data) {
2769 // decrypt seqence
2770 mf_crypto1_decrypt(pcs, receivedCmd, len);
2771 }
2772
2773 if (len == 4 && (receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61)) {
2774 authTimer = GetTickCount();
2775 cardAUTHSC = receivedCmd[1] / 4; // received block num
2776 cardAUTHKEY = receivedCmd[0] - 0x60;
2777 crypto1_destroy(pcs);//Added by martin
2778 crypto1_create(pcs, emlGetKey(cardAUTHSC, cardAUTHKEY));
2779
2780 if (!encrypted_data) { // first authentication
2781 if (MF_DBGLEVEL >= 4) Dbprintf("Reader authenticating for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
2782
2783 crypto1_word(pcs, cuid ^ nonce, 0);//Update crypto state
2784 num_to_bytes(nonce, 4, rAUTH_AT); // Send nonce
2785 } else { // nested authentication
2786 if (MF_DBGLEVEL >= 4) Dbprintf("Reader doing nested authentication for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
2787 ans = nonce ^ crypto1_word(pcs, cuid ^ nonce, 0);
2788 num_to_bytes(ans, 4, rAUTH_AT);
2789 }
2790
2791 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2792 //Dbprintf("Sending rAUTH %02x%02x%02x%02x", rAUTH_AT[0],rAUTH_AT[1],rAUTH_AT[2],rAUTH_AT[3]);
2793 cardSTATE = MFEMUL_AUTH1;
2794 break;
2795 }
2796
2797 // rule 13 of 7.5.3. in ISO 14443-4. chaining shall be continued
2798 // BUT... ACK --> NACK
2799 if (len == 1 && receivedCmd[0] == CARD_ACK) {
2800 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2801 break;
2802 }
2803
2804 // rule 12 of 7.5.3. in ISO 14443-4. R(NAK) --> R(ACK)
2805 if (len == 1 && receivedCmd[0] == CARD_NACK_NA) {
2806 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2807 break;
2808 }
2809
2810 if(len != 4) {
2811 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2812 break;
2813 }
2814
2815 if(receivedCmd[0] == 0x30 // read block
2816 || receivedCmd[0] == 0xA0 // write block
2817 || receivedCmd[0] == 0xC0 // inc
2818 || receivedCmd[0] == 0xC1 // dec
2819 || receivedCmd[0] == 0xC2 // restore
2820 || receivedCmd[0] == 0xB0) { // transfer
2821 if (receivedCmd[1] >= 16 * 4) {
2822 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2823 if (MF_DBGLEVEL >= 4) Dbprintf("Reader tried to operate (0x%02) on out of range block: %d (0x%02x), nacking",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2824 break;
2825 }
2826
2827 if (receivedCmd[1] / 4 != cardAUTHSC) {
2828 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2829 if (MF_DBGLEVEL >= 4) Dbprintf("Reader tried to operate (0x%02) on block (0x%02x) not authenticated for (0x%02x), nacking",receivedCmd[0],receivedCmd[1],cardAUTHSC);
2830 break;
2831 }
2832 }
2833 // read block
2834 if (receivedCmd[0] == 0x30) {
2835 if (MF_DBGLEVEL >= 4) {
2836 Dbprintf("Reader reading block %d (0x%02x)",receivedCmd[1],receivedCmd[1]);
2837 }
2838 emlGetMem(response, receivedCmd[1], 1);
2839 AppendCrc14443a(response, 16);
2840 mf_crypto1_encrypt(pcs, response, 18, response_par);
2841 EmSendCmdPar(response, 18, response_par);
2842 numReads++;
2843 if(exitAfterNReads > 0 && numReads >= exitAfterNReads) {
2844 Dbprintf("%d reads done, exiting", numReads);
2845 finished = true;
2846 }
2847 break;
2848 }
2849 // write block
2850 if (receivedCmd[0] == 0xA0) {
2851 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0xA0 write block %d (%02x)",receivedCmd[1],receivedCmd[1]);
2852 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2853 cardSTATE = MFEMUL_WRITEBL2;
2854 cardWRBL = receivedCmd[1];
2855 break;
2856 }
2857 // increment, decrement, restore
2858 if (receivedCmd[0] == 0xC0 || receivedCmd[0] == 0xC1 || receivedCmd[0] == 0xC2) {
2859 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x inc(0xC1)/dec(0xC0)/restore(0xC2) block %d (%02x)",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2860 if (emlCheckValBl(receivedCmd[1])) {
2861 if (MF_DBGLEVEL >= 4) Dbprintf("Reader tried to operate on block, but emlCheckValBl failed, nacking");
2862 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2863 break;
2864 }
2865 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2866 if (receivedCmd[0] == 0xC1)
2867 cardSTATE = MFEMUL_INTREG_INC;
2868 if (receivedCmd[0] == 0xC0)
2869 cardSTATE = MFEMUL_INTREG_DEC;
2870 if (receivedCmd[0] == 0xC2)
2871 cardSTATE = MFEMUL_INTREG_REST;
2872 cardWRBL = receivedCmd[1];
2873 break;
2874 }
2875 // transfer
2876 if (receivedCmd[0] == 0xB0) {
2877 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x transfer block %d (%02x)",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2878 if (emlSetValBl(cardINTREG, cardINTBLOCK, receivedCmd[1]))
2879 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2880 else
2881 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2882 break;
2883 }
2884 // halt
2885 if (receivedCmd[0] == 0x50 && receivedCmd[1] == 0x00) {
2886 LED_B_OFF();
2887 LED_C_OFF();
2888 cardSTATE = MFEMUL_HALTED;
2889 if (MF_DBGLEVEL >= 4) Dbprintf("--> HALTED. Selected time: %d ms", GetTickCount() - selTimer);
2890 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2891 break;
2892 }
2893 // RATS
2894 if (receivedCmd[0] == 0xe0) {//RATS
2895 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2896 break;
2897 }
2898 // command not allowed
2899 if (MF_DBGLEVEL >= 4) Dbprintf("Received command not allowed, nacking");
2900 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2901 break;
2902 }
2903 case MFEMUL_WRITEBL2:{
2904 if (len == 18){
2905 mf_crypto1_decrypt(pcs, receivedCmd, len);
2906 emlSetMem(receivedCmd, cardWRBL, 1);
2907 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2908 cardSTATE = MFEMUL_WORK;
2909 } else {
2910 cardSTATE_TO_IDLE();
2911 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2912 }
2913 break;
2914 }
2915
2916 case MFEMUL_INTREG_INC:{
2917 mf_crypto1_decrypt(pcs, receivedCmd, len);
2918 memcpy(&ans, receivedCmd, 4);
2919 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2920 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2921 cardSTATE_TO_IDLE();
2922 break;
2923 }
2924 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2925 cardINTREG = cardINTREG + ans;
2926 cardSTATE = MFEMUL_WORK;
2927 break;
2928 }
2929 case MFEMUL_INTREG_DEC:{
2930 mf_crypto1_decrypt(pcs, receivedCmd, len);
2931 memcpy(&ans, receivedCmd, 4);
2932 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2933 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2934 cardSTATE_TO_IDLE();
2935 break;
2936 }
2937 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2938 cardINTREG = cardINTREG - ans;
2939 cardSTATE = MFEMUL_WORK;
2940 break;
2941 }
2942 case MFEMUL_INTREG_REST:{
2943 mf_crypto1_decrypt(pcs, receivedCmd, len);
2944 memcpy(&ans, receivedCmd, 4);
2945 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2946 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2947 cardSTATE_TO_IDLE();
2948 break;
2949 }
2950 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2951 cardSTATE = MFEMUL_WORK;
2952 break;
2953 }
2954 }
2955 }
2956
2957 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2958 LEDsoff();
2959
2960 if(flags & FLAG_INTERACTIVE)// Interactive mode flag, means we need to send ACK
2961 {
2962 //May just aswell send the collected ar_nr in the response aswell
2963 uint8_t len = ar_nr_collected*5*4;
2964 cmd_send(CMD_ACK, CMD_SIMULATE_MIFARE_CARD, len, 0, &ar_nr_responses, len);
2965 }
2966
2967 if(flags & FLAG_NR_AR_ATTACK && MF_DBGLEVEL >= 1 )
2968 {
2969 if(ar_nr_collected > 1 ) {
2970 Dbprintf("Collected two pairs of AR/NR which can be used to extract keys from reader:");
2971 Dbprintf("../tools/mfkey/mfkey32 %06x%08x %08x %08x %08x %08x %08x",
2972 ar_nr_responses[0], // UID1
2973 ar_nr_responses[1], // UID2
2974 ar_nr_responses[2], // NT
2975 ar_nr_responses[3], // AR1
2976 ar_nr_responses[4], // NR1
2977 ar_nr_responses[8], // AR2
2978 ar_nr_responses[9] // NR2
2979 );
2980 Dbprintf("../tools/mfkey/mfkey32v2 %06x%08x %08x %08x %08x %08x %08x %08x",
2981 ar_nr_responses[0], // UID1
2982 ar_nr_responses[1], // UID2
2983 ar_nr_responses[2], // NT1
2984 ar_nr_responses[3], // AR1
2985 ar_nr_responses[4], // NR1
2986 ar_nr_responses[7], // NT2
2987 ar_nr_responses[8], // AR2
2988 ar_nr_responses[9] // NR2
2989 );
2990 } else {
2991 Dbprintf("Failed to obtain two AR/NR pairs!");
2992 if(ar_nr_collected > 0 ) {
2993 Dbprintf("Only got these: UID=%07x%08x, nonce=%08x, AR1=%08x, NR1=%08x",
2994 ar_nr_responses[0], // UID1
2995 ar_nr_responses[1], // UID2
2996 ar_nr_responses[2], // NT
2997 ar_nr_responses[3], // AR1
2998 ar_nr_responses[4] // NR1
2999 );
3000 }
3001 }
3002 }
3003 if (MF_DBGLEVEL >= 1) Dbprintf("Emulator stopped. Tracing: %d trace length: %d ", tracing, BigBuf_get_traceLen());
3004 }
3005
3006
3007 //-----------------------------------------------------------------------------
3008 // MIFARE sniffer.
3009 //
3010 //-----------------------------------------------------------------------------
3011 void RAMFUNC SniffMifare(uint8_t param) {
3012 // param:
3013 // bit 0 - trigger from first card answer
3014 // bit 1 - trigger from first reader 7-bit request
3015
3016 // C(red) A(yellow) B(green)
3017 LEDsoff();
3018 // init trace buffer
3019 clear_trace();
3020 set_tracing(TRUE);
3021
3022 // The command (reader -> tag) that we're receiving.
3023 // The length of a received command will in most cases be no more than 18 bytes.
3024 // So 32 should be enough!
3025 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE];
3026 uint8_t receivedCmdPar[MAX_MIFARE_PARITY_SIZE];
3027 // The response (tag -> reader) that we're receiving.
3028 uint8_t receivedResponse[MAX_MIFARE_FRAME_SIZE];
3029 uint8_t receivedResponsePar[MAX_MIFARE_PARITY_SIZE];
3030
3031 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
3032
3033 // free eventually allocated BigBuf memory
3034 BigBuf_free();
3035 // allocate the DMA buffer, used to stream samples from the FPGA
3036 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
3037 uint8_t *data = dmaBuf;
3038 uint8_t previous_data = 0;
3039 int maxDataLen = 0;
3040 int dataLen = 0;
3041 bool ReaderIsActive = FALSE;
3042 bool TagIsActive = FALSE;
3043
3044 // Set up the demodulator for tag -> reader responses.
3045 DemodInit(receivedResponse, receivedResponsePar);
3046
3047 // Set up the demodulator for the reader -> tag commands
3048 UartInit(receivedCmd, receivedCmdPar);
3049
3050 // Setup for the DMA.
3051 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
3052
3053 LED_D_OFF();
3054
3055 // init sniffer
3056 MfSniffInit();
3057
3058 // And now we loop, receiving samples.
3059 for(uint32_t sniffCounter = 0; TRUE; ) {
3060
3061 if(BUTTON_PRESS()) {
3062 DbpString("cancelled by button");
3063 break;
3064 }
3065
3066 LED_A_ON();
3067 WDT_HIT();
3068
3069 if ((sniffCounter & 0x0000FFFF) == 0) { // from time to time
3070 // check if a transaction is completed (timeout after 2000ms).
3071 // if yes, stop the DMA transfer and send what we have so far to the client
3072 if (MfSniffSend(2000)) {
3073 // Reset everything - we missed some sniffed data anyway while the DMA was stopped
3074 sniffCounter = 0;
3075 data = dmaBuf;
3076 maxDataLen = 0;
3077 ReaderIsActive = FALSE;
3078 TagIsActive = FALSE;
3079 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
3080 }
3081 }
3082
3083 int register readBufDataP = data - dmaBuf; // number of bytes we have processed so far
3084 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR; // number of bytes already transferred
3085 if (readBufDataP <= dmaBufDataP){ // we are processing the same block of data which is currently being transferred
3086 dataLen = dmaBufDataP - readBufDataP; // number of bytes still to be processed
3087 } else {
3088 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP; // number of bytes still to be processed
3089 }
3090 // test for length of buffer
3091 if(dataLen > maxDataLen) { // we are more behind than ever...
3092 maxDataLen = dataLen;
3093 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
3094 Dbprintf("blew circular buffer! dataLen=0x%x", dataLen);
3095 break;
3096 }
3097 }
3098 if(dataLen < 1) continue;
3099
3100 // primary buffer was stopped ( <-- we lost data!
3101 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
3102 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
3103 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
3104 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
3105 }
3106 // secondary buffer sets as primary, secondary buffer was stopped
3107 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
3108 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
3109 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
3110 }
3111
3112 LED_A_OFF();
3113
3114 if (sniffCounter & 0x01) {
3115
3116 if(!TagIsActive) { // no need to try decoding tag data if the reader is sending
3117 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
3118 if(MillerDecoding(readerdata, (sniffCounter-1)*4)) {
3119 LED_C_INV();
3120 if (MfSniffLogic(receivedCmd, Uart.len, Uart.parity, Uart.bitCount, TRUE)) break;
3121
3122 /* And ready to receive another command. */
3123 UartReset();
3124
3125 /* And also reset the demod code */
3126 DemodReset();
3127 }
3128 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
3129 }
3130
3131 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending
3132 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
3133 if(ManchesterDecoding(tagdata, 0, (sniffCounter-1)*4)) {
3134 LED_C_INV();
3135
3136 if (MfSniffLogic(receivedResponse, Demod.len, Demod.parity, Demod.bitCount, FALSE)) break;
3137
3138 // And ready to receive another response.
3139 DemodReset();
3140
3141 // And reset the Miller decoder including its (now outdated) input buffer
3142 UartInit(receivedCmd, receivedCmdPar);
3143 // why not UartReset?
3144 }
3145 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
3146 }
3147 }
3148
3149 previous_data = *data;
3150 sniffCounter++;
3151 data++;
3152 if(data == dmaBuf + DMA_BUFFER_SIZE) {
3153 data = dmaBuf;
3154 }
3155
3156 } // main cycle
3157
3158 FpgaDisableSscDma();
3159 MfSniffEnd();
3160 LEDsoff();
3161 Dbprintf("maxDataLen=%x, Uart.state=%x, Uart.len=%x", maxDataLen, Uart.state, Uart.len);
3162 }
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