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1 //-----------------------------------------------------------------------------
2 // (c) 2009 Henryk Plötz <henryk@ploetzli.ch>
3 // 2016 Iceman
4 //
5 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
6 // at your option, any later version. See the LICENSE.txt file for the text of
7 // the license.
8 //-----------------------------------------------------------------------------
9 // LEGIC RF simulation code
10 //-----------------------------------------------------------------------------
11 #include "legicrf.h"
12
13 static struct legic_frame {
14 uint8_t bits;
15 uint32_t data;
16 } current_frame;
17
18 static enum {
19 STATE_DISCON,
20 STATE_IV,
21 STATE_CON,
22 } legic_state;
23
24 static crc_t legic_crc;
25 static int legic_read_count;
26 static uint32_t legic_prng_bc;
27 static uint32_t legic_prng_iv;
28
29 static int legic_phase_drift;
30 static int legic_frame_drift;
31 static int legic_reqresp_drift;
32
33 AT91PS_TC timer;
34 AT91PS_TC prng_timer;
35
36 /*
37 static void setup_timer(void) {
38 // Set up Timer 1 to use for measuring time between pulses. Since we're bit-banging
39 // this it won't be terribly accurate but should be good enough.
40 //
41 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
42 timer = AT91C_BASE_TC1;
43 timer->TC_CCR = AT91C_TC_CLKDIS;
44 timer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK;
45 timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
46
47 //
48 // Set up Timer 2 to use for measuring time between frames in
49 // tag simulation mode. Runs 4x faster as Timer 1
50 //
51 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC2);
52 prng_timer = AT91C_BASE_TC2;
53 prng_timer->TC_CCR = AT91C_TC_CLKDIS;
54 prng_timer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV2_CLOCK;
55 prng_timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
56 }
57
58 AT91C_BASE_PMC->PMC_PCER |= (0x1 << 12) | (0x1 << 13) | (0x1 << 14);
59 AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
60
61 // fast clock
62 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable
63 AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz)/32 -- tick=1.5mks
64 AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR |
65 AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;
66 AT91C_BASE_TC0->TC_RA = 1;
67 AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000
68
69 */
70
71 // At TIMER_CLOCK3 (MCK/32)
72 // testing calculating in (us) microseconds.
73 #define RWD_TIME_1 120 // READER_TIME_PAUSE 20us off, 80us on = 100us 80 * 1.5 == 120ticks
74 #define RWD_TIME_0 60 // READER_TIME_PAUSE 20us off, 40us on = 60us 40 * 1.5 == 60ticks
75 #define RWD_TIME_PAUSE 30 // 20us == 20 * 1.5 == 30ticks */
76 #define TAG_BIT_PERIOD 142 // 100us == 100 * 1.5 == 150ticks
77 #define TAG_FRAME_WAIT 495 // 330us from READER frame end to TAG frame start. 330 * 1.5 == 495
78
79 #define RWD_TIME_FUZZ 20 // rather generous 13us, since the peak detector + hysteresis fuzz quite a bit
80
81 #define SIM_DIVISOR 586 /* prng_time/SIM_DIVISOR count prng needs to be forwared */
82 #define SIM_SHIFT 900 /* prng_time+SIM_SHIFT shift of delayed start */
83
84 #define OFFSET_LOG 1024
85
86 #define FUZZ_EQUAL(value, target, fuzz) ((value) > ((target)-(fuzz)) && (value) < ((target)+(fuzz)))
87
88 #ifndef SHORT_COIL
89 # define SHORT_COIL LOW(GPIO_SSC_DOUT);
90 #endif
91 #ifndef OPEN_COIL
92 # define OPEN_COIL HIGH(GPIO_SSC_DOUT);
93 #endif
94 #ifndef LINE_IN
95 # define LINE_IN AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
96 #endif
97 // Pause pulse, off in 20us / 30ticks,
98 // ONE / ZERO bit pulse,
99 // one == 80us / 120ticks
100 // zero == 40us / 60ticks
101 #ifndef COIL_PULSE
102 # define COIL_PULSE(x) \
103 do { \
104 SHORT_COIL; \
105 WaitTicks( (RWD_TIME_PAUSE) ); \
106 OPEN_COIL; \
107 WaitTicks((x)); \
108 } while (0);
109 #endif
110
111 // ToDo: define a meaningful maximum size for auth_table. The bigger this is, the lower will be the available memory for traces.
112 // Historically it used to be FREE_BUFFER_SIZE, which was 2744.
113 #define LEGIC_CARD_MEMSIZE 1024
114 static uint8_t* cardmem;
115
116 static void frame_append_bit(struct legic_frame * const f, uint8_t bit) {
117 // Overflow, won't happen
118 if (f->bits >= 31) return;
119
120 f->data |= (bit << f->bits);
121 f->bits++;
122 }
123
124 static void frame_clean(struct legic_frame * const f) {
125 f->data = 0;
126 f->bits = 0;
127 }
128
129 // Prng works when waiting in 99.1us cycles.
130 // and while sending/receiving in bit frames (100, 60)
131 /*static void CalibratePrng( uint32_t time){
132 // Calculate Cycles based on timer 100us
133 uint32_t i = (time - sendFrameStop) / 100 ;
134
135 // substract cycles of finished frames
136 int k = i - legic_prng_count()+1;
137
138 // substract current frame length, rewind to beginning
139 if ( k > 0 )
140 legic_prng_forward(k);
141 }
142 */
143
144 /* Generate Keystream */
145 uint32_t get_key_stream(int skip, int count) {
146
147 int i;
148
149 // Use int to enlarge timer tc to 32bit
150 legic_prng_bc += prng_timer->TC_CV;
151
152 // reset the prng timer.
153
154 /* If skip == -1, forward prng time based */
155 if(skip == -1) {
156 i = (legic_prng_bc + SIM_SHIFT)/SIM_DIVISOR; /* Calculate Cycles based on timer */
157 i -= legic_prng_count(); /* substract cycles of finished frames */
158 i -= count; /* substract current frame length, rewind to beginning */
159 legic_prng_forward(i);
160 } else {
161 legic_prng_forward(skip);
162 }
163
164 i = (count == 6) ? -1 : legic_read_count;
165
166 /* Generate KeyStream */
167 return legic_prng_get_bits(count);
168 }
169
170 /* Send a frame in tag mode, the FPGA must have been set up by
171 * LegicRfSimulate
172 */
173 void frame_send_tag(uint16_t response, uint8_t bits) {
174
175 uint16_t mask = 1;
176
177 /* Bitbang the response */
178 SHORT_COIL;
179 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
180 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
181
182 /* TAG_FRAME_WAIT -> shift by 2 */
183 legic_prng_forward(2);
184 response ^= legic_prng_get_bits(bits);
185
186 /* Wait for the frame start */
187 WaitTicks( TAG_FRAME_WAIT );
188
189 for (; mask < BITMASK(bits); mask <<= 1) {
190 if (response & mask)
191 OPEN_COIL
192 else
193 SHORT_COIL
194 WaitTicks(TAG_BIT_PERIOD);
195 }
196 SHORT_COIL;
197 }
198
199 /* Send a frame in reader mode, the FPGA must have been set up by
200 * LegicRfReader
201 */
202 void frame_sendAsReader(uint32_t data, uint8_t bits){
203
204 uint32_t starttime = GET_TICKS, send = 0, mask = 1;
205
206 // xor lsfr onto data.
207 send = data ^ legic_prng_get_bits(bits);
208
209 for (; mask < BITMASK(bits); mask <<= 1) {
210 if (send & mask)
211 COIL_PULSE(RWD_TIME_1)
212 else
213 COIL_PULSE(RWD_TIME_0)
214 }
215
216 // Final pause to mark the end of the frame
217 COIL_PULSE(0);
218
219 // log
220 uint8_t cmdbytes[] = {bits, BYTEx(data,0), BYTEx(data,1), BYTEx(data,2) , BYTEx(send,0), BYTEx(send,1)};
221 LogTrace(cmdbytes, sizeof(cmdbytes), starttime, GET_TICKS, NULL, TRUE);
222 }
223
224 /* Receive a frame from the card in reader emulation mode, the FPGA and
225 * timer must have been set up by LegicRfReader and frame_sendAsReader.
226 *
227 * The LEGIC RF protocol from card to reader does not include explicit
228 * frame start/stop information or length information. The reader must
229 * know beforehand how many bits it wants to receive. (Notably: a card
230 * sending a stream of 0-bits is indistinguishable from no card present.)
231 *
232 * Receive methodology: There is a fancy correlator in hi_read_rx_xcorr, but
233 * I'm not smart enough to use it. Instead I have patched hi_read_tx to output
234 * the ADC signal with hysteresis on SSP_DIN. Bit-bang that signal and look
235 * for edges. Count the edges in each bit interval. If they are approximately
236 * 0 this was a 0-bit, if they are approximately equal to the number of edges
237 * expected for a 212kHz subcarrier, this was a 1-bit. For timing we use the
238 * timer that's still running from frame_sendAsReader in order to get a synchronization
239 * with the frame that we just sent.
240 *
241 * FIXME: Because we're relying on the hysteresis to just do the right thing
242 * the range is severely reduced (and you'll probably also need a good antenna).
243 * So this should be fixed some time in the future for a proper receiver.
244 */
245 static void frame_receiveAsReader(struct legic_frame * const f, uint8_t bits) {
246
247 if ( bits > 32 ) return;
248
249 uint8_t i = bits, edges = 0;
250 uint32_t the_bit = 1, next_bit_at = 0, data = 0;
251 uint32_t old_level = 0;
252 volatile uint32_t level = 0;
253
254 frame_clean(f);
255
256 // calibrate the prng.
257 legic_prng_forward(2);
258 data = legic_prng_get_bits(bits);
259
260 //FIXED time between sending frame and now listening frame. 330us
261 uint32_t starttime = GET_TICKS;
262 // its about 9+9 ticks delay from end-send to here.
263 WaitTicks( 477 );
264
265 next_bit_at = GET_TICKS + TAG_BIT_PERIOD;
266
267 while ( i-- ){
268 edges = 0;
269 while ( GET_TICKS < next_bit_at) {
270
271 level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
272
273 if (level != old_level)
274 ++edges;
275
276 old_level = level;
277 }
278
279 next_bit_at += TAG_BIT_PERIOD;
280
281 // We expect 42 edges (ONE)
282 if ( edges > 20 )
283 data ^= the_bit;
284
285 the_bit <<= 1;
286 }
287
288 // output
289 f->data = data;
290 f->bits = bits;
291
292 // log
293 uint8_t cmdbytes[] = {bits, BYTEx(data, 0), BYTEx(data, 1)};
294 LogTrace(cmdbytes, sizeof(cmdbytes), starttime, GET_TICKS, NULL, FALSE);
295 }
296
297 // Setup pm3 as a Legic Reader
298 static uint32_t setup_phase_reader(uint8_t iv) {
299
300 // Switch on carrier and let the tag charge for 1ms
301 HIGH(GPIO_SSC_DOUT);
302 WaitUS(5000);
303
304 ResetTicks();
305
306 // no keystream yet
307 legic_prng_init(0);
308
309 // send IV handshake
310 frame_sendAsReader(iv, 7);
311
312 // Now both tag and reader has same IV. Prng can start.
313 legic_prng_init(iv);
314
315 frame_receiveAsReader(&current_frame, 6);
316
317 // 292us (438t) - fixed delay before sending ack.
318 // minus log and stuff 100tick?
319 WaitTicks(338);
320 legic_prng_forward(3);
321
322 // Send obsfuscated acknowledgment frame.
323 // 0x19 = 0x18 MIM22, 0x01 LSB READCMD
324 // 0x39 = 0x38 MIM256, MIM1024 0x01 LSB READCMD
325 switch ( current_frame.data ) {
326 case 0x0D: frame_sendAsReader(0x19, 6); break;
327 case 0x1D:
328 case 0x3D: frame_sendAsReader(0x39, 6); break;
329 default: break;
330 }
331
332 legic_prng_forward(2);
333 return current_frame.data;
334 }
335
336 static void LegicCommonInit(void) {
337
338 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
339 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX);
340 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
341
342 /* Bitbang the transmitter */
343 SHORT_COIL;
344 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
345 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
346 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
347
348 // reserve a cardmem, meaning we can use the tracelog function in bigbuff easier.
349 cardmem = BigBuf_get_EM_addr();
350 memset(cardmem, 0x00, LEGIC_CARD_MEMSIZE);
351
352 clear_trace();
353 set_tracing(TRUE);
354 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
355
356 StartTicks();
357 }
358
359 // Switch off carrier, make sure tag is reset
360 static void switch_off_tag_rwd(void) {
361 SHORT_COIL;
362 WaitUS(20);
363 WDT_HIT();
364 }
365
366 // calculate crc4 for a legic READ command
367 static uint32_t legic4Crc(uint8_t cmd, uint16_t byte_index, uint8_t value, uint8_t cmd_sz) {
368 crc_clear(&legic_crc);
369 uint32_t temp = (value << cmd_sz) | (byte_index << 1) | cmd;
370 crc_update(&legic_crc, temp, cmd_sz + 8 );
371 return crc_finish(&legic_crc);
372 }
373
374 int legic_read_byte( uint16_t index, uint8_t cmd_sz) {
375
376 uint8_t byte, crc, calcCrc = 0;
377 uint32_t cmd = (index << 1) | LEGIC_READ;
378
379 // 90ticks = 60us (should be 100us but crc calc takes time.)
380 //WaitTicks(330); // 330ticks prng(4) - works
381 WaitTicks(240); // 240ticks prng(3) - works
382
383 frame_sendAsReader(cmd, cmd_sz);
384 frame_receiveAsReader(&current_frame, 12);
385
386 // CRC check.
387 byte = BYTEx(current_frame.data, 0);
388 crc = BYTEx(current_frame.data, 1);
389 calcCrc = legic4Crc(LEGIC_READ, index, byte, cmd_sz);
390
391 if( calcCrc != crc ) {
392 Dbprintf("!!! crc mismatch: %x != %x !!!", calcCrc, crc);
393 return -1;
394 }
395
396 legic_prng_forward(3);
397 return byte;
398 }
399
400 /*
401 * - assemble a write_cmd_frame with crc and send it
402 * - wait until the tag sends back an ACK ('1' bit unencrypted)
403 * - forward the prng based on the timing
404 */
405 bool legic_write_byte(uint16_t index, uint8_t byte, uint8_t addr_sz) {
406
407 bool isOK = false;
408 uint8_t i = 80, edges = 0;
409 uint8_t cmd_sz = addr_sz+1+8+4; //crc+data+cmd;
410 uint32_t steps = 0, next_bit_at, start, crc, old_level = 0;
411
412 /*
413 crc_clear(&legic_crc);
414 crc_update(&legic_crc, 0, 1); // CMD_WRITE
415 crc_update(&legic_crc, index, addr_sz);
416 crc_update(&legic_crc, byte, 8);
417 uint32_t crc = crc_finish(&legic_crc);
418 */
419 crc = legic4Crc(LEGIC_WRITE, index, byte, addr_sz+1);
420
421 // send write command
422 uint32_t cmd = LEGIC_WRITE;
423 cmd |= index << 1; // index
424 cmd |= byte << (addr_sz+1); // Data
425 cmd |= (crc & 0xF ) << (addr_sz+1+8); // CRC
426
427 /* Bitbang the response */
428 SHORT_COIL;
429 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
430
431 WaitTicks(330);
432
433 frame_sendAsReader(cmd, cmd_sz);
434
435 LINE_IN;
436
437 start = GET_TICKS;
438
439 // ACK, - one single "1" bit after 3.6ms
440 // 3.6ms = 3600us * 1.5 = 5400ticks.
441 WaitTicks(5000);
442 //WaitTicks(330);
443
444 next_bit_at = GET_TICKS + TAG_BIT_PERIOD;
445
446 while ( i-- ) {
447 WDT_HIT();
448 edges = 0;
449 while ( GET_TICKS < next_bit_at) {
450
451 volatile uint32_t level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
452
453 if (level != old_level)
454 ++edges;
455
456 old_level = level;
457 }
458
459 next_bit_at += TAG_BIT_PERIOD;
460
461 // We expect 42 edges (ONE)
462 if(edges > 20 ) {
463 steps = ( (GET_TICKS - start) / TAG_BIT_PERIOD);
464 legic_prng_forward(steps);
465 isOK = true;
466 goto OUT;
467 }
468 }
469
470 OUT: ;
471 // log
472 uint8_t cmdbytes[] = {1, isOK, BYTEx(steps, 0), BYTEx(steps, 1) };
473 LogTrace(cmdbytes, sizeof(cmdbytes), start, GET_TICKS, NULL, FALSE);
474 return isOK;
475 }
476
477 int LegicRfReader(uint16_t offset, uint16_t len, uint8_t iv) {
478
479 uint16_t i = 0;
480 uint8_t isOK = 1;
481 legic_card_select_t card;
482
483 LegicCommonInit();
484
485 if ( legic_select_card_iv(&card, iv) ) {
486 isOK = 0;
487 goto OUT;
488 }
489
490 if (len + offset >= card.cardsize)
491 len = card.cardsize - offset;
492
493 LED_B_ON();
494 while (i < len) {
495 int r = legic_read_byte(offset + i, card.cmdsize);
496
497 if (r == -1 || BUTTON_PRESS()) {
498 if ( MF_DBGLEVEL >= 2) DbpString("operation aborted");
499 isOK = 0;
500 goto OUT;
501 }
502 cardmem[i++] = r;
503 WDT_HIT();
504 }
505
506 OUT:
507 WDT_HIT();
508 switch_off_tag_rwd();
509 LEDsoff();
510 cmd_send(CMD_ACK, isOK, len, 0, cardmem, len);
511 return 0;
512 }
513
514 void LegicRfWriter(uint16_t offset, uint16_t len, uint8_t iv, uint8_t *data) {
515
516 #define LOWERLIMIT 4
517 uint8_t isOK = 1;
518 legic_card_select_t card;
519
520 // uid NOT is writeable.
521 if ( offset <= LOWERLIMIT ) {
522 isOK = 0;
523 goto OUT;
524 }
525
526 LegicCommonInit();
527
528 if ( legic_select_card_iv(&card, iv) ) {
529 isOK = 0;
530 goto OUT;
531 }
532
533 if ( len + offset + LOWERLIMIT >= card.cardsize) {
534 isOK = 0;
535 goto OUT;
536 }
537
538 LED_B_ON();
539 while( len > 0 ) {
540 --len;
541 if ( !legic_write_byte( len + offset, data[len], card.addrsize) ) {
542 Dbprintf("operation failed | %d | %d | %d", len + offset, len, data[len] );
543 isOK = 0;
544 goto OUT;
545 }
546 WDT_HIT();
547 }
548 OUT:
549 cmd_send(CMD_ACK, isOK, 0,0,0,0);
550 switch_off_tag_rwd();
551 LEDsoff();
552 }
553
554 int legic_select_card_iv(legic_card_select_t *p_card, uint8_t iv){
555
556 if ( p_card == NULL ) return 1;
557
558 p_card->tagtype = setup_phase_reader(iv);
559
560 switch(p_card->tagtype) {
561 case 0x0d:
562 p_card->cmdsize = 6;
563 p_card->addrsize = 5;
564 p_card->cardsize = 22;
565 break;
566 case 0x1d:
567 p_card->cmdsize = 9;
568 p_card->addrsize = 8;
569 p_card->cardsize = 256;
570 break;
571 case 0x3d:
572 p_card->cmdsize = 11;
573 p_card->addrsize = 10;
574 p_card->cardsize = 1024;
575 break;
576 default:
577 p_card->cmdsize = 0;
578 p_card->addrsize = 0;
579 p_card->cardsize = 0;
580 return 2;
581 }
582 return 0;
583 }
584 int legic_select_card(legic_card_select_t *p_card){
585 return legic_select_card_iv(p_card, 0x01);
586 }
587
588 //-----------------------------------------------------------------------------
589 // Work with emulator memory
590 //
591 // Note: we call FpgaDownloadAndGo(FPGA_BITSTREAM_HF) here although FPGA is not
592 // involved in dealing with emulator memory. But if it is called later, it might
593 // destroy the Emulator Memory.
594 //-----------------------------------------------------------------------------
595 // arg0 = offset
596 // arg1 = num of bytes
597 void LegicEMemSet(uint32_t arg0, uint32_t arg1, uint8_t *data) {
598 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
599 legic_emlset_mem(data, arg0, arg1);
600 }
601 // arg0 = offset
602 // arg1 = num of bytes
603 void LegicEMemGet(uint32_t arg0, uint32_t arg1) {
604 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
605 uint8_t buf[USB_CMD_DATA_SIZE] = {0x00};
606 legic_emlget_mem(buf, arg0, arg1);
607 LED_B_ON();
608 cmd_send(CMD_ACK, arg0, arg1, 0, buf, USB_CMD_DATA_SIZE);
609 LED_B_OFF();
610 }
611 void legic_emlset_mem(uint8_t *data, int offset, int numofbytes) {
612 cardmem = BigBuf_get_EM_addr();
613 memcpy(cardmem + offset, data, numofbytes);
614 }
615 void legic_emlget_mem(uint8_t *data, int offset, int numofbytes) {
616 cardmem = BigBuf_get_EM_addr();
617 memcpy(data, cardmem + offset, numofbytes);
618 }
619
620 void LegicRfInfo(void){
621
622 int r;
623
624 uint8_t buf[sizeof(legic_card_select_t)] = {0x00};
625 legic_card_select_t *card = (legic_card_select_t*) buf;
626
627 LegicCommonInit();
628
629 if ( legic_select_card(card) ) {
630 cmd_send(CMD_ACK,0,0,0,0,0);
631 goto OUT;
632 }
633
634 // read UID bytes
635 for ( uint8_t i = 0; i < sizeof(card->uid); ++i) {
636 r = legic_read_byte(i, card->cmdsize);
637 if ( r == -1 ) {
638 cmd_send(CMD_ACK,0,0,0,0,0);
639 goto OUT;
640 }
641 card->uid[i] = r & 0xFF;
642 }
643
644 // MCC byte.
645 r = legic_read_byte(4, card->cmdsize);
646 uint32_t calc_mcc = CRC8Legic(card->uid, 4);;
647 if ( r != calc_mcc) {
648 cmd_send(CMD_ACK,0,0,0,0,0);
649 goto OUT;
650 }
651
652 // OK
653 cmd_send(CMD_ACK, 1, 0, 0, buf, sizeof(legic_card_select_t));
654
655 OUT:
656 switch_off_tag_rwd();
657 LEDsoff();
658 }
659
660 /* Handle (whether to respond) a frame in tag mode
661 * Only called when simulating a tag.
662 */
663 static void frame_handle_tag(struct legic_frame const * const f)
664 {
665 // log
666 //uint8_t cmdbytes[] = {bits, BYTEx(data, 0), BYTEx(data, 1)};
667 //LogTrace(cmdbytes, sizeof(cmdbytes), starttime, GET_TICKS, NULL, FALSE);
668
669 cardmem = BigBuf_get_EM_addr();
670
671 /* First Part of Handshake (IV) */
672 if(f->bits == 7) {
673
674 LED_C_ON();
675
676 // Reset prng timer
677 ResetTimer(prng_timer);
678
679 // IV from reader.
680 legic_prng_init(f->data);
681
682 // We should have three tagtypes with three different answers.
683 frame_send_tag(0x3d, 6); /* 0x3d^0x26 = 0x1B */
684
685 legic_state = STATE_IV;
686 legic_read_count = 0;
687 legic_prng_bc = 0;
688 legic_prng_iv = f->data;
689
690
691 ResetTimer(timer);
692 WaitUS(280);
693 return;
694 }
695
696 /* 0x19==??? */
697 if(legic_state == STATE_IV) {
698 uint32_t local_key = get_key_stream(3, 6);
699 int xored = 0x39 ^ local_key;
700 if((f->bits == 6) && (f->data == xored)) {
701 legic_state = STATE_CON;
702
703 ResetTimer(timer);
704 WaitUS(200);
705 return;
706
707 } else {
708 legic_state = STATE_DISCON;
709 LED_C_OFF();
710 Dbprintf("iv: %02x frame: %02x key: %02x xored: %02x", legic_prng_iv, f->data, local_key, xored);
711 return;
712 }
713 }
714
715 /* Read */
716 if(f->bits == 11) {
717 if(legic_state == STATE_CON) {
718 uint32_t key = get_key_stream(2, 11); //legic_phase_drift, 11);
719 uint16_t addr = f->data ^ key;
720 addr >>= 1;
721 uint8_t data = cardmem[addr];
722 int hash = legic4Crc(LEGIC_READ, addr, data, 11) << 8;
723
724 legic_read_count++;
725 legic_prng_forward(legic_reqresp_drift);
726
727 frame_send_tag(hash | data, 12);
728 ResetTimer(timer);
729 legic_prng_forward(2);
730 WaitTicks(330);
731 return;
732 }
733 }
734
735 /* Write */
736 if(f->bits == 23) {
737 uint32_t key = get_key_stream(-1, 23); //legic_frame_drift, 23);
738 uint16_t addr = f->data ^ key;
739 addr >>= 1;
740 addr &= 0x3ff;
741 uint32_t data = f->data ^ key;
742 data >>= 11;
743 data &= 0xff;
744
745 cardmem[addr] = data;
746 /* write command */
747 legic_state = STATE_DISCON;
748 LED_C_OFF();
749 Dbprintf("write - addr: %x, data: %x", addr, data);
750 // should send a ACK within 3.5ms too
751 return;
752 }
753
754 if(legic_state != STATE_DISCON) {
755 Dbprintf("Unexpected: sz:%u, Data:%03.3x, State:%u, Count:%u", f->bits, f->data, legic_state, legic_read_count);
756 Dbprintf("IV: %03.3x", legic_prng_iv);
757 }
758
759 legic_state = STATE_DISCON;
760 legic_read_count = 0;
761 SpinDelay(10);
762 LED_C_OFF();
763 return;
764 }
765
766 /* Read bit by bit untill full frame is received
767 * Call to process frame end answer
768 */
769 static void emit(int bit) {
770
771 switch (bit) {
772 case 1:
773 frame_append_bit(&current_frame, 1);
774 break;
775 case 0:
776 frame_append_bit(&current_frame, 0);
777 break;
778 default:
779 if(current_frame.bits <= 4) {
780 frame_clean(&current_frame);
781 } else {
782 frame_handle_tag(&current_frame);
783 frame_clean(&current_frame);
784 }
785 WDT_HIT();
786 break;
787 }
788 }
789
790 void LegicRfSimulate(int phase, int frame, int reqresp)
791 {
792 /* ADC path high-frequency peak detector, FPGA in high-frequency simulator mode,
793 * modulation mode set to 212kHz subcarrier. We are getting the incoming raw
794 * envelope waveform on DIN and should send our response on DOUT.
795 *
796 * The LEGIC RF protocol is pulse-pause-encoding from reader to card, so we'll
797 * measure the time between two rising edges on DIN, and no encoding on the
798 * subcarrier from card to reader, so we'll just shift out our verbatim data
799 * on DOUT, 1 bit is 100us. The time from reader to card frame is still unclear,
800 * seems to be 300us-ish.
801 */
802
803 int old_level = 0, active = 0;
804 legic_state = STATE_DISCON;
805
806 legic_phase_drift = phase;
807 legic_frame_drift = frame;
808 legic_reqresp_drift = reqresp;
809
810 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
811 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
812 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_212K);
813
814 /* Bitbang the receiver */
815 LINE_IN;
816
817 // need a way to determine which tagtype we are simulating
818
819 // hook up emulator memory
820 cardmem = BigBuf_get_EM_addr();
821
822 clear_trace();
823 set_tracing(TRUE);
824
825 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
826
827 StartTicks();
828
829 LED_B_ON();
830 DbpString("Starting Legic emulator, press button to end");
831
832 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
833 volatile uint32_t level = !!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
834
835 uint32_t time = GET_TICKS;
836
837 if (level != old_level) {
838
839 if (level) {
840
841 ResetTicks();
842
843 if (FUZZ_EQUAL(time, RWD_TIME_1, RWD_TIME_FUZZ)) {
844 /* 1 bit */
845 emit(1);
846 active = 1;
847 LED_A_ON();
848 } else if (FUZZ_EQUAL(time, RWD_TIME_0, RWD_TIME_FUZZ)) {
849 /* 0 bit */
850 emit(0);
851 active = 1;
852 LED_A_ON();
853 } else if (active) {
854 /* invalid */
855 emit(-1);
856 active = 0;
857 LED_A_OFF();
858 }
859 }
860 }
861
862 /* Frame end */
863 if(time >= (RWD_TIME_1+RWD_TIME_FUZZ) && active) {
864 emit(-1);
865 active = 0;
866 LED_A_OFF();
867 }
868
869 /*
870 * Disable the counter, Then wait for the clock to acknowledge the
871 * shutdown in its status register. Reading the SR has the
872 * side-effect of clearing any pending state in there.
873 */
874 if(time >= (20*RWD_TIME_1) && (timer->TC_SR & AT91C_TC_CLKSTA))
875 StopTicks();
876
877 old_level = level;
878 WDT_HIT();
879 }
880
881 WDT_HIT();
882 switch_off_tag_rwd();
883 LEDsoff();
884 cmd_send(CMD_ACK, 1, 0, 0, 0, 0);
885 }
886
887 //-----------------------------------------------------------------------------
888 // Code up a string of octets at layer 2 (including CRC, we don't generate
889 // that here) so that they can be transmitted to the reader. Doesn't transmit
890 // them yet, just leaves them ready to send in ToSend[].
891 //-----------------------------------------------------------------------------
892 // static void CodeLegicAsTag(const uint8_t *cmd, int len)
893 // {
894 // int i;
895
896 // ToSendReset();
897
898 // // Transmit a burst of ones, as the initial thing that lets the
899 // // reader get phase sync. This (TR1) must be > 80/fs, per spec,
900 // // but tag that I've tried (a Paypass) exceeds that by a fair bit,
901 // // so I will too.
902 // for(i = 0; i < 20; i++) {
903 // ToSendStuffBit(1);
904 // ToSendStuffBit(1);
905 // ToSendStuffBit(1);
906 // ToSendStuffBit(1);
907 // }
908
909 // // Send SOF.
910 // for(i = 0; i < 10; i++) {
911 // ToSendStuffBit(0);
912 // ToSendStuffBit(0);
913 // ToSendStuffBit(0);
914 // ToSendStuffBit(0);
915 // }
916 // for(i = 0; i < 2; i++) {
917 // ToSendStuffBit(1);
918 // ToSendStuffBit(1);
919 // ToSendStuffBit(1);
920 // ToSendStuffBit(1);
921 // }
922
923 // for(i = 0; i < len; i++) {
924 // int j;
925 // uint8_t b = cmd[i];
926
927 // // Start bit
928 // ToSendStuffBit(0);
929 // ToSendStuffBit(0);
930 // ToSendStuffBit(0);
931 // ToSendStuffBit(0);
932
933 // // Data bits
934 // for(j = 0; j < 8; j++) {
935 // if(b & 1) {
936 // ToSendStuffBit(1);
937 // ToSendStuffBit(1);
938 // ToSendStuffBit(1);
939 // ToSendStuffBit(1);
940 // } else {
941 // ToSendStuffBit(0);
942 // ToSendStuffBit(0);
943 // ToSendStuffBit(0);
944 // ToSendStuffBit(0);
945 // }
946 // b >>= 1;
947 // }
948
949 // // Stop bit
950 // ToSendStuffBit(1);
951 // ToSendStuffBit(1);
952 // ToSendStuffBit(1);
953 // ToSendStuffBit(1);
954 // }
955
956 // // Send EOF.
957 // for(i = 0; i < 10; i++) {
958 // ToSendStuffBit(0);
959 // ToSendStuffBit(0);
960 // ToSendStuffBit(0);
961 // ToSendStuffBit(0);
962 // }
963 // for(i = 0; i < 2; i++) {
964 // ToSendStuffBit(1);
965 // ToSendStuffBit(1);
966 // ToSendStuffBit(1);
967 // ToSendStuffBit(1);
968 // }
969
970 // // Convert from last byte pos to length
971 // ToSendMax++;
972 // }
973
974 //-----------------------------------------------------------------------------
975 // The software UART that receives commands from the reader, and its state
976 // variables.
977 //-----------------------------------------------------------------------------
978 /*
979 static struct {
980 enum {
981 STATE_UNSYNCD,
982 STATE_GOT_FALLING_EDGE_OF_SOF,
983 STATE_AWAITING_START_BIT,
984 STATE_RECEIVING_DATA
985 } state;
986 uint16_t shiftReg;
987 int bitCnt;
988 int byteCnt;
989 int byteCntMax;
990 int posCnt;
991 uint8_t *output;
992 } Uart;
993 */
994 /* Receive & handle a bit coming from the reader.
995 *
996 * This function is called 4 times per bit (every 2 subcarrier cycles).
997 * Subcarrier frequency fs is 212kHz, 1/fs = 4,72us, i.e. function is called every 9,44us
998 *
999 * LED handling:
1000 * LED A -> ON once we have received the SOF and are expecting the rest.
1001 * LED A -> OFF once we have received EOF or are in error state or unsynced
1002 *
1003 * Returns: true if we received a EOF
1004 * false if we are still waiting for some more
1005 */
1006 // static RAMFUNC int HandleLegicUartBit(uint8_t bit)
1007 // {
1008 // switch(Uart.state) {
1009 // case STATE_UNSYNCD:
1010 // if(!bit) {
1011 // // we went low, so this could be the beginning of an SOF
1012 // Uart.state = STATE_GOT_FALLING_EDGE_OF_SOF;
1013 // Uart.posCnt = 0;
1014 // Uart.bitCnt = 0;
1015 // }
1016 // break;
1017
1018 // case STATE_GOT_FALLING_EDGE_OF_SOF:
1019 // Uart.posCnt++;
1020 // if(Uart.posCnt == 2) { // sample every 4 1/fs in the middle of a bit
1021 // if(bit) {
1022 // if(Uart.bitCnt > 9) {
1023 // // we've seen enough consecutive
1024 // // zeros that it's a valid SOF
1025 // Uart.posCnt = 0;
1026 // Uart.byteCnt = 0;
1027 // Uart.state = STATE_AWAITING_START_BIT;
1028 // LED_A_ON(); // Indicate we got a valid SOF
1029 // } else {
1030 // // didn't stay down long enough
1031 // // before going high, error
1032 // Uart.state = STATE_UNSYNCD;
1033 // }
1034 // } else {
1035 // // do nothing, keep waiting
1036 // }
1037 // Uart.bitCnt++;
1038 // }
1039 // if(Uart.posCnt >= 4) Uart.posCnt = 0;
1040 // if(Uart.bitCnt > 12) {
1041 // // Give up if we see too many zeros without
1042 // // a one, too.
1043 // LED_A_OFF();
1044 // Uart.state = STATE_UNSYNCD;
1045 // }
1046 // break;
1047
1048 // case STATE_AWAITING_START_BIT:
1049 // Uart.posCnt++;
1050 // if(bit) {
1051 // if(Uart.posCnt > 50/2) { // max 57us between characters = 49 1/fs, max 3 etus after low phase of SOF = 24 1/fs
1052 // // stayed high for too long between
1053 // // characters, error
1054 // Uart.state = STATE_UNSYNCD;
1055 // }
1056 // } else {
1057 // // falling edge, this starts the data byte
1058 // Uart.posCnt = 0;
1059 // Uart.bitCnt = 0;
1060 // Uart.shiftReg = 0;
1061 // Uart.state = STATE_RECEIVING_DATA;
1062 // }
1063 // break;
1064
1065 // case STATE_RECEIVING_DATA:
1066 // Uart.posCnt++;
1067 // if(Uart.posCnt == 2) {
1068 // // time to sample a bit
1069 // Uart.shiftReg >>= 1;
1070 // if(bit) {
1071 // Uart.shiftReg |= 0x200;
1072 // }
1073 // Uart.bitCnt++;
1074 // }
1075 // if(Uart.posCnt >= 4) {
1076 // Uart.posCnt = 0;
1077 // }
1078 // if(Uart.bitCnt == 10) {
1079 // if((Uart.shiftReg & 0x200) && !(Uart.shiftReg & 0x001))
1080 // {
1081 // // this is a data byte, with correct
1082 // // start and stop bits
1083 // Uart.output[Uart.byteCnt] = (Uart.shiftReg >> 1) & 0xff;
1084 // Uart.byteCnt++;
1085
1086 // if(Uart.byteCnt >= Uart.byteCntMax) {
1087 // // Buffer overflowed, give up
1088 // LED_A_OFF();
1089 // Uart.state = STATE_UNSYNCD;
1090 // } else {
1091 // // so get the next byte now
1092 // Uart.posCnt = 0;
1093 // Uart.state = STATE_AWAITING_START_BIT;
1094 // }
1095 // } else if (Uart.shiftReg == 0x000) {
1096 // // this is an EOF byte
1097 // LED_A_OFF(); // Finished receiving
1098 // Uart.state = STATE_UNSYNCD;
1099 // if (Uart.byteCnt != 0) {
1100 // return TRUE;
1101 // }
1102 // } else {
1103 // // this is an error
1104 // LED_A_OFF();
1105 // Uart.state = STATE_UNSYNCD;
1106 // }
1107 // }
1108 // break;
1109
1110 // default:
1111 // LED_A_OFF();
1112 // Uart.state = STATE_UNSYNCD;
1113 // break;
1114 // }
1115
1116 // return FALSE;
1117 // }
1118 /*
1119
1120 static void UartReset() {
1121 Uart.byteCntMax = 3;
1122 Uart.state = STATE_UNSYNCD;
1123 Uart.byteCnt = 0;
1124 Uart.bitCnt = 0;
1125 Uart.posCnt = 0;
1126 memset(Uart.output, 0x00, 3);
1127 }
1128 */
1129 // static void UartInit(uint8_t *data) {
1130 // Uart.output = data;
1131 // UartReset();
1132 // }
1133
1134 //=============================================================================
1135 // An LEGIC reader. We take layer two commands, code them
1136 // appropriately, and then send them to the tag. We then listen for the
1137 // tag's response, which we leave in the buffer to be demodulated on the
1138 // PC side.
1139 //=============================================================================
1140 /*
1141 static struct {
1142 enum {
1143 DEMOD_UNSYNCD,
1144 DEMOD_PHASE_REF_TRAINING,
1145 DEMOD_AWAITING_FALLING_EDGE_OF_SOF,
1146 DEMOD_GOT_FALLING_EDGE_OF_SOF,
1147 DEMOD_AWAITING_START_BIT,
1148 DEMOD_RECEIVING_DATA
1149 } state;
1150 int bitCount;
1151 int posCount;
1152 int thisBit;
1153 uint16_t shiftReg;
1154 uint8_t *output;
1155 int len;
1156 int sumI;
1157 int sumQ;
1158 } Demod;
1159 */
1160 /*
1161 * Handles reception of a bit from the tag
1162 *
1163 * This function is called 2 times per bit (every 4 subcarrier cycles).
1164 * Subcarrier frequency fs is 212kHz, 1/fs = 4,72us, i.e. function is called every 9,44us
1165 *
1166 * LED handling:
1167 * LED C -> ON once we have received the SOF and are expecting the rest.
1168 * LED C -> OFF once we have received EOF or are unsynced
1169 *
1170 * Returns: true if we received a EOF
1171 * false if we are still waiting for some more
1172 *
1173 */
1174
1175 /*
1176 static RAMFUNC int HandleLegicSamplesDemod(int ci, int cq)
1177 {
1178 int v = 0;
1179 int ai = ABS(ci);
1180 int aq = ABS(cq);
1181 int halfci = (ai >> 1);
1182 int halfcq = (aq >> 1);
1183
1184 switch(Demod.state) {
1185 case DEMOD_UNSYNCD:
1186
1187 CHECK_FOR_SUBCARRIER()
1188
1189 if(v > SUBCARRIER_DETECT_THRESHOLD) { // subcarrier detected
1190 Demod.state = DEMOD_PHASE_REF_TRAINING;
1191 Demod.sumI = ci;
1192 Demod.sumQ = cq;
1193 Demod.posCount = 1;
1194 }
1195 break;
1196
1197 case DEMOD_PHASE_REF_TRAINING:
1198 if(Demod.posCount < 8) {
1199
1200 CHECK_FOR_SUBCARRIER()
1201
1202 if (v > SUBCARRIER_DETECT_THRESHOLD) {
1203 // set the reference phase (will code a logic '1') by averaging over 32 1/fs.
1204 // note: synchronization time > 80 1/fs
1205 Demod.sumI += ci;
1206 Demod.sumQ += cq;
1207 ++Demod.posCount;
1208 } else {
1209 // subcarrier lost
1210 Demod.state = DEMOD_UNSYNCD;
1211 }
1212 } else {
1213 Demod.state = DEMOD_AWAITING_FALLING_EDGE_OF_SOF;
1214 }
1215 break;
1216
1217 case DEMOD_AWAITING_FALLING_EDGE_OF_SOF:
1218
1219 MAKE_SOFT_DECISION()
1220
1221 //Dbprintf("ICE: %d %d %d %d %d", v, Demod.sumI, Demod.sumQ, ci, cq );
1222 // logic '0' detected
1223 if (v <= 0) {
1224
1225 Demod.state = DEMOD_GOT_FALLING_EDGE_OF_SOF;
1226
1227 // start of SOF sequence
1228 Demod.posCount = 0;
1229 } else {
1230 // maximum length of TR1 = 200 1/fs
1231 if(Demod.posCount > 25*2) Demod.state = DEMOD_UNSYNCD;
1232 }
1233 ++Demod.posCount;
1234 break;
1235
1236 case DEMOD_GOT_FALLING_EDGE_OF_SOF:
1237 ++Demod.posCount;
1238
1239 MAKE_SOFT_DECISION()
1240
1241 if(v > 0) {
1242 // low phase of SOF too short (< 9 etu). Note: spec is >= 10, but FPGA tends to "smear" edges
1243 if(Demod.posCount < 10*2) {
1244 Demod.state = DEMOD_UNSYNCD;
1245 } else {
1246 LED_C_ON(); // Got SOF
1247 Demod.state = DEMOD_AWAITING_START_BIT;
1248 Demod.posCount = 0;
1249 Demod.len = 0;
1250 }
1251 } else {
1252 // low phase of SOF too long (> 12 etu)
1253 if(Demod.posCount > 13*2) {
1254 Demod.state = DEMOD_UNSYNCD;
1255 LED_C_OFF();
1256 }
1257 }
1258 break;
1259
1260 case DEMOD_AWAITING_START_BIT:
1261 ++Demod.posCount;
1262
1263 MAKE_SOFT_DECISION()
1264
1265 if(v > 0) {
1266 // max 19us between characters = 16 1/fs, max 3 etu after low phase of SOF = 24 1/fs
1267 if(Demod.posCount > 3*2) {
1268 Demod.state = DEMOD_UNSYNCD;
1269 LED_C_OFF();
1270 }
1271 } else {
1272 // start bit detected
1273 Demod.bitCount = 0;
1274 Demod.posCount = 1; // this was the first half
1275 Demod.thisBit = v;
1276 Demod.shiftReg = 0;
1277 Demod.state = DEMOD_RECEIVING_DATA;
1278 }
1279 break;
1280
1281 case DEMOD_RECEIVING_DATA:
1282
1283 MAKE_SOFT_DECISION()
1284
1285 if(Demod.posCount == 0) {
1286 // first half of bit
1287 Demod.thisBit = v;
1288 Demod.posCount = 1;
1289 } else {
1290 // second half of bit
1291 Demod.thisBit += v;
1292 Demod.shiftReg >>= 1;
1293 // logic '1'
1294 if(Demod.thisBit > 0)
1295 Demod.shiftReg |= 0x200;
1296
1297 ++Demod.bitCount;
1298
1299 if(Demod.bitCount == 10) {
1300
1301 uint16_t s = Demod.shiftReg;
1302
1303 if((s & 0x200) && !(s & 0x001)) {
1304 // stop bit == '1', start bit == '0'
1305 uint8_t b = (s >> 1);
1306 Demod.output[Demod.len] = b;
1307 ++Demod.len;
1308 Demod.state = DEMOD_AWAITING_START_BIT;
1309 } else {
1310 Demod.state = DEMOD_UNSYNCD;
1311 LED_C_OFF();
1312
1313 if(s == 0x000) {
1314 // This is EOF (start, stop and all data bits == '0'
1315 return TRUE;
1316 }
1317 }
1318 }
1319 Demod.posCount = 0;
1320 }
1321 break;
1322
1323 default:
1324 Demod.state = DEMOD_UNSYNCD;
1325 LED_C_OFF();
1326 break;
1327 }
1328 return FALSE;
1329 }
1330 */
1331 /*
1332 // Clear out the state of the "UART" that receives from the tag.
1333 static void DemodReset() {
1334 Demod.len = 0;
1335 Demod.state = DEMOD_UNSYNCD;
1336 Demod.posCount = 0;
1337 Demod.sumI = 0;
1338 Demod.sumQ = 0;
1339 Demod.bitCount = 0;
1340 Demod.thisBit = 0;
1341 Demod.shiftReg = 0;
1342 memset(Demod.output, 0x00, 3);
1343 }
1344
1345 static void DemodInit(uint8_t *data) {
1346 Demod.output = data;
1347 DemodReset();
1348 }
1349 */
1350
1351 /*
1352 * Demodulate the samples we received from the tag, also log to tracebuffer
1353 * quiet: set to 'TRUE' to disable debug output
1354 */
1355
1356 /*
1357 #define LEGIC_DMA_BUFFER_SIZE 256
1358
1359 static void GetSamplesForLegicDemod(int n, bool quiet)
1360 {
1361 int max = 0;
1362 bool gotFrame = FALSE;
1363 int lastRxCounter = LEGIC_DMA_BUFFER_SIZE;
1364 int ci, cq, samples = 0;
1365
1366 BigBuf_free();
1367
1368 // And put the FPGA in the appropriate mode
1369 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_QUARTER_FREQ);
1370
1371 // The response (tag -> reader) that we're receiving.
1372 // Set up the demodulator for tag -> reader responses.
1373 DemodInit(BigBuf_malloc(MAX_FRAME_SIZE));
1374
1375 // The DMA buffer, used to stream samples from the FPGA
1376 int8_t *dmaBuf = (int8_t*) BigBuf_malloc(LEGIC_DMA_BUFFER_SIZE);
1377 int8_t *upTo = dmaBuf;
1378
1379 // Setup and start DMA.
1380 if ( !FpgaSetupSscDma((uint8_t*) dmaBuf, LEGIC_DMA_BUFFER_SIZE) ){
1381 if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting");
1382 return;
1383 }
1384
1385 // Signal field is ON with the appropriate LED:
1386 LED_D_ON();
1387 for(;;) {
1388 int behindBy = lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR;
1389 if(behindBy > max) max = behindBy;
1390
1391 while(((lastRxCounter-AT91C_BASE_PDC_SSC->PDC_RCR) & (LEGIC_DMA_BUFFER_SIZE-1)) > 2) {
1392 ci = upTo[0];
1393 cq = upTo[1];
1394 upTo += 2;
1395 if(upTo >= dmaBuf + LEGIC_DMA_BUFFER_SIZE) {
1396 upTo = dmaBuf;
1397 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo;
1398 AT91C_BASE_PDC_SSC->PDC_RNCR = LEGIC_DMA_BUFFER_SIZE;
1399 }
1400 lastRxCounter -= 2;
1401 if(lastRxCounter <= 0)
1402 lastRxCounter = LEGIC_DMA_BUFFER_SIZE;
1403
1404 samples += 2;
1405
1406 gotFrame = HandleLegicSamplesDemod(ci , cq );
1407 if ( gotFrame )
1408 break;
1409 }
1410
1411 if(samples > n || gotFrame)
1412 break;
1413 }
1414
1415 FpgaDisableSscDma();
1416
1417 if (!quiet && Demod.len == 0) {
1418 Dbprintf("max behindby = %d, samples = %d, gotFrame = %d, Demod.len = %d, Demod.sumI = %d, Demod.sumQ = %d",
1419 max,
1420 samples,
1421 gotFrame,
1422 Demod.len,
1423 Demod.sumI,
1424 Demod.sumQ
1425 );
1426 }
1427
1428 //Tracing
1429 if (Demod.len > 0) {
1430 uint8_t parity[MAX_PARITY_SIZE] = {0x00};
1431 LogTrace(Demod.output, Demod.len, 0, 0, parity, FALSE);
1432 }
1433 }
1434
1435 */
1436
1437 //-----------------------------------------------------------------------------
1438 // Transmit the command (to the tag) that was placed in ToSend[].
1439 //-----------------------------------------------------------------------------
1440 /*
1441 static void TransmitForLegic(void)
1442 {
1443 int c;
1444
1445 FpgaSetupSsc();
1446
1447 while(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY))
1448 AT91C_BASE_SSC->SSC_THR = 0xff;
1449
1450 // Signal field is ON with the appropriate Red LED
1451 LED_D_ON();
1452
1453 // Signal we are transmitting with the Green LED
1454 LED_B_ON();
1455 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
1456
1457 for(c = 0; c < 10;) {
1458 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1459 AT91C_BASE_SSC->SSC_THR = 0xff;
1460 c++;
1461 }
1462 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1463 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
1464 (void)r;
1465 }
1466 WDT_HIT();
1467 }
1468
1469 c = 0;
1470 for(;;) {
1471 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1472 AT91C_BASE_SSC->SSC_THR = ToSend[c];
1473 legic_prng_forward(1); // forward the lfsr
1474 c++;
1475 if(c >= ToSendMax) {
1476 break;
1477 }
1478 }
1479 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1480 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
1481 (void)r;
1482 }
1483 WDT_HIT();
1484 }
1485 LED_B_OFF();
1486 }
1487 */
1488
1489 //-----------------------------------------------------------------------------
1490 // Code a layer 2 command (string of octets, including CRC) into ToSend[],
1491 // so that it is ready to transmit to the tag using TransmitForLegic().
1492 //-----------------------------------------------------------------------------
1493 /*
1494 static void CodeLegicBitsAsReader(const uint8_t *cmd, uint8_t cmdlen, int bits)
1495 {
1496 int i, j;
1497 uint8_t b;
1498
1499 ToSendReset();
1500
1501 // Send SOF
1502 for(i = 0; i < 7; i++)
1503 ToSendStuffBit(1);
1504
1505
1506 for(i = 0; i < cmdlen; i++) {
1507 // Start bit
1508 ToSendStuffBit(0);
1509
1510 // Data bits
1511 b = cmd[i];
1512 for(j = 0; j < bits; j++) {
1513 if(b & 1) {
1514 ToSendStuffBit(1);
1515 } else {
1516 ToSendStuffBit(0);
1517 }
1518 b >>= 1;
1519 }
1520 }
1521
1522 // Convert from last character reference to length
1523 ++ToSendMax;
1524 }
1525 */
1526 /**
1527 Convenience function to encode, transmit and trace Legic comms
1528 **/
1529 /*
1530 static void CodeAndTransmitLegicAsReader(const uint8_t *cmd, uint8_t cmdlen, int bits)
1531 {
1532 CodeLegicBitsAsReader(cmd, cmdlen, bits);
1533 TransmitForLegic();
1534 if (tracing) {
1535 uint8_t parity[1] = {0x00};
1536 LogTrace(cmd, cmdlen, 0, 0, parity, TRUE);
1537 }
1538 }
1539
1540 */
1541 // Set up LEGIC communication
1542 /*
1543 void ice_legic_setup() {
1544
1545 // standard things.
1546 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1547 BigBuf_free(); BigBuf_Clear_ext(false);
1548 clear_trace();
1549 set_tracing(TRUE);
1550 DemodReset();
1551 UartReset();
1552
1553 // Set up the synchronous serial port
1554 FpgaSetupSsc();
1555
1556 // connect Demodulated Signal to ADC:
1557 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1558
1559 // Signal field is on with the appropriate LED
1560 LED_D_ON();
1561 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
1562 SpinDelay(20);
1563 // Start the timer
1564 //StartCountSspClk();
1565
1566 // initalize CRC
1567 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
1568
1569 // initalize prng
1570 legic_prng_init(0);
1571 }
1572 */
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