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1 //-----------------------------------------------------------------------------
2 // (c) 2009 Henryk Plötz <henryk@ploetzli.ch>
3 // 2016 Iceman
4 //
5 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
6 // at your option, any later version. See the LICENSE.txt file for the text of
7 // the license.
8 //-----------------------------------------------------------------------------
9 // LEGIC RF simulation code
10 //-----------------------------------------------------------------------------
11 #include "legicrf.h"
12
13 static struct legic_frame {
14 uint8_t bits;
15 uint32_t data;
16 } current_frame;
17
18 static enum {
19 STATE_DISCON,
20 STATE_IV,
21 STATE_CON,
22 } legic_state;
23
24 static crc_t legic_crc;
25 static int legic_read_count;
26 static uint32_t legic_prng_bc;
27 static uint32_t legic_prng_iv;
28
29 static int legic_phase_drift;
30 static int legic_frame_drift;
31 static int legic_reqresp_drift;
32
33 AT91PS_TC timer;
34 AT91PS_TC prng_timer;
35
36 /*
37 static void setup_timer(void) {
38 // Set up Timer 1 to use for measuring time between pulses. Since we're bit-banging
39 // this it won't be terribly accurate but should be good enough.
40 //
41 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
42 timer = AT91C_BASE_TC1;
43 timer->TC_CCR = AT91C_TC_CLKDIS;
44 timer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK;
45 timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
46
47 //
48 // Set up Timer 2 to use for measuring time between frames in
49 // tag simulation mode. Runs 4x faster as Timer 1
50 //
51 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC2);
52 prng_timer = AT91C_BASE_TC2;
53 prng_timer->TC_CCR = AT91C_TC_CLKDIS;
54 prng_timer->TC_CMR = AT91C_TC_CLKS_TIMER_DIV2_CLOCK;
55 prng_timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
56 }
57
58 AT91C_BASE_PMC->PMC_PCER |= (0x1 << 12) | (0x1 << 13) | (0x1 << 14);
59 AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
60
61 // fast clock
62 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable
63 AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz)/32 -- tick=1.5mks
64 AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR |
65 AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;
66 AT91C_BASE_TC0->TC_RA = 1;
67 AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000
68
69 */
70
71 // At TIMER_CLOCK3 (MCK/32)
72 // testing calculating in (us) microseconds.
73 #define RWD_TIME_1 120 // READER_TIME_PAUSE 20us off, 80us on = 100us 80 * 1.5 == 120ticks
74 #define RWD_TIME_0 60 // READER_TIME_PAUSE 20us off, 40us on = 60us 40 * 1.5 == 60ticks
75 #define RWD_TIME_PAUSE 30 // 20us == 20 * 1.5 == 30ticks */
76 #define TAG_BIT_PERIOD 142 // 100us == 100 * 1.5 == 150ticks
77 #define TAG_FRAME_WAIT 495 // 330us from READER frame end to TAG frame start. 330 * 1.5 == 495
78
79 #define RWD_TIME_FUZZ 20 // rather generous 13us, since the peak detector + hysteresis fuzz quite a bit
80
81 #define SIM_DIVISOR 586 /* prng_time/SIM_DIVISOR count prng needs to be forwared */
82 #define SIM_SHIFT 900 /* prng_time+SIM_SHIFT shift of delayed start */
83
84 #define OFFSET_LOG 1024
85
86 #define FUZZ_EQUAL(value, target, fuzz) ((value) > ((target)-(fuzz)) && (value) < ((target)+(fuzz)))
87
88 #ifndef SHORT_COIL
89 # define SHORT_COIL LOW(GPIO_SSC_DOUT);
90 #endif
91 #ifndef OPEN_COIL
92 # define OPEN_COIL HIGH(GPIO_SSC_DOUT);
93 #endif
94 #ifndef LINE_IN
95 # define LINE_IN AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
96 #endif
97 // Pause pulse, off in 20us / 30ticks,
98 // ONE / ZERO bit pulse,
99 // one == 80us / 120ticks
100 // zero == 40us / 60ticks
101 #ifndef COIL_PULSE
102 # define COIL_PULSE(x) \
103 do { \
104 SHORT_COIL; \
105 WaitTicks( (RWD_TIME_PAUSE) ); \
106 OPEN_COIL; \
107 WaitTicks((x)); \
108 } while (0);
109 #endif
110
111 // ToDo: define a meaningful maximum size for auth_table. The bigger this is, the lower will be the available memory for traces.
112 // Historically it used to be FREE_BUFFER_SIZE, which was 2744.
113 #define LEGIC_CARD_MEMSIZE 1024
114 static uint8_t* cardmem;
115
116 static void frame_append_bit(struct legic_frame * const f, uint8_t bit) {
117 // Overflow, won't happen
118 if (f->bits >= 31) return;
119
120 f->data |= (bit << f->bits);
121 f->bits++;
122 }
123
124 static void frame_clean(struct legic_frame * const f) {
125 f->data = 0;
126 f->bits = 0;
127 }
128
129 // Prng works when waiting in 99.1us cycles.
130 // and while sending/receiving in bit frames (100, 60)
131 /*static void CalibratePrng( uint32_t time){
132 // Calculate Cycles based on timer 100us
133 uint32_t i = (time - sendFrameStop) / 100 ;
134
135 // substract cycles of finished frames
136 int k = i - legic_prng_count()+1;
137
138 // substract current frame length, rewind to beginning
139 if ( k > 0 )
140 legic_prng_forward(k);
141 }
142 */
143
144 /* Generate Keystream */
145 uint32_t get_key_stream(int skip, int count) {
146
147 int i;
148
149 // Use int to enlarge timer tc to 32bit
150 legic_prng_bc += prng_timer->TC_CV;
151
152 // reset the prng timer.
153
154 /* If skip == -1, forward prng time based */
155 if(skip == -1) {
156 i = (legic_prng_bc + SIM_SHIFT)/SIM_DIVISOR; /* Calculate Cycles based on timer */
157 i -= legic_prng_count(); /* substract cycles of finished frames */
158 i -= count; /* substract current frame length, rewind to beginning */
159 legic_prng_forward(i);
160 } else {
161 legic_prng_forward(skip);
162 }
163
164 i = (count == 6) ? -1 : legic_read_count;
165
166 /* Generate KeyStream */
167 return legic_prng_get_bits(count);
168 }
169
170 /* Send a frame in tag mode, the FPGA must have been set up by
171 * LegicRfSimulate
172 */
173 void frame_send_tag(uint16_t response, uint8_t bits) {
174
175 uint16_t mask = 1;
176
177 /* Bitbang the response */
178 SHORT_COIL;
179 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
180 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
181
182 /* TAG_FRAME_WAIT -> shift by 2 */
183 legic_prng_forward(2);
184 response ^= legic_prng_get_bits(bits);
185
186 /* Wait for the frame start */
187 WaitTicks( TAG_FRAME_WAIT );
188
189 for (; mask < BITMASK(bits); mask <<= 1) {
190 if (response & mask)
191 OPEN_COIL
192 else
193 SHORT_COIL
194 WaitTicks(TAG_BIT_PERIOD);
195 }
196 SHORT_COIL;
197 }
198
199 /* Send a frame in reader mode, the FPGA must have been set up by
200 * LegicRfReader
201 */
202 void frame_sendAsReader(uint32_t data, uint8_t bits){
203
204 uint32_t starttime = GET_TICKS, send = 0, mask = 1;
205
206 // xor lsfr onto data.
207 send = data ^ legic_prng_get_bits(bits);
208
209 for (; mask < BITMASK(bits); mask <<= 1) {
210 if (send & mask)
211 COIL_PULSE(RWD_TIME_1)
212 else
213 COIL_PULSE(RWD_TIME_0)
214 }
215
216 // Final pause to mark the end of the frame
217 COIL_PULSE(0);
218
219 // log
220 uint8_t cmdbytes[] = {bits, BYTEx(data,0), BYTEx(data,1), BYTEx(data,2) , BYTEx(send,0), BYTEx(send,1)};
221 LogTrace(cmdbytes, sizeof(cmdbytes), starttime, GET_TICKS, NULL, TRUE);
222 }
223
224 /* Receive a frame from the card in reader emulation mode, the FPGA and
225 * timer must have been set up by LegicRfReader and frame_sendAsReader.
226 *
227 * The LEGIC RF protocol from card to reader does not include explicit
228 * frame start/stop information or length information. The reader must
229 * know beforehand how many bits it wants to receive. (Notably: a card
230 * sending a stream of 0-bits is indistinguishable from no card present.)
231 *
232 * Receive methodology: There is a fancy correlator in hi_read_rx_xcorr, but
233 * I'm not smart enough to use it. Instead I have patched hi_read_tx to output
234 * the ADC signal with hysteresis on SSP_DIN. Bit-bang that signal and look
235 * for edges. Count the edges in each bit interval. If they are approximately
236 * 0 this was a 0-bit, if they are approximately equal to the number of edges
237 * expected for a 212kHz subcarrier, this was a 1-bit. For timing we use the
238 * timer that's still running from frame_sendAsReader in order to get a synchronization
239 * with the frame that we just sent.
240 *
241 * FIXME: Because we're relying on the hysteresis to just do the right thing
242 * the range is severely reduced (and you'll probably also need a good antenna).
243 * So this should be fixed some time in the future for a proper receiver.
244 */
245 static void frame_receiveAsReader(struct legic_frame * const f, uint8_t bits) {
246
247 if ( bits > 32 ) return;
248
249 uint8_t i = bits, edges = 0;
250 uint32_t the_bit = 1, next_bit_at = 0, data = 0;
251 uint32_t old_level = 0;
252 volatile uint32_t level = 0;
253
254 frame_clean(f);
255
256 // calibrate the prng.
257 legic_prng_forward(2);
258 data = legic_prng_get_bits(bits);
259
260 //FIXED time between sending frame and now listening frame. 330us
261 uint32_t starttime = GET_TICKS;
262 // its about 9+9 ticks delay from end-send to here.
263 WaitTicks( 477 );
264
265 next_bit_at = GET_TICKS + TAG_BIT_PERIOD;
266
267 while ( i-- ){
268 edges = 0;
269 while ( GET_TICKS < next_bit_at) {
270
271 level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
272
273 if (level != old_level)
274 ++edges;
275
276 old_level = level;
277 }
278
279 next_bit_at += TAG_BIT_PERIOD;
280
281 // We expect 42 edges (ONE)
282 if ( edges > 20 )
283 data ^= the_bit;
284
285 the_bit <<= 1;
286 }
287
288 // output
289 f->data = data;
290 f->bits = bits;
291
292 // log
293 uint8_t cmdbytes[] = {bits, BYTEx(data, 0), BYTEx(data, 1)};
294 LogTrace(cmdbytes, sizeof(cmdbytes), starttime, GET_TICKS, NULL, FALSE);
295 }
296
297 // Setup pm3 as a Legic Reader
298 static uint32_t setup_phase_reader(uint8_t iv) {
299
300 // Switch on carrier and let the tag charge for 1ms
301 HIGH(GPIO_SSC_DOUT);
302 WaitUS(5000);
303
304 ResetTicks();
305
306 // no keystream yet
307 legic_prng_init(0);
308
309 // send IV handshake
310 frame_sendAsReader(iv, 7);
311
312 // Now both tag and reader has same IV. Prng can start.
313 legic_prng_init(iv);
314
315 frame_receiveAsReader(&current_frame, 6);
316
317 // 292us (438t) - fixed delay before sending ack.
318 // minus log and stuff 100tick?
319 WaitTicks(338);
320 legic_prng_forward(3);
321
322 // Send obsfuscated acknowledgment frame.
323 // 0x19 = 0x18 MIM22, 0x01 LSB READCMD
324 // 0x39 = 0x38 MIM256, MIM1024 0x01 LSB READCMD
325 switch ( current_frame.data ) {
326 case 0x0D: frame_sendAsReader(0x19, 6); break;
327 case 0x1D:
328 case 0x3D: frame_sendAsReader(0x39, 6); break;
329 default: break;
330 }
331
332 legic_prng_forward(2);
333 return current_frame.data;
334 }
335
336 static void LegicCommonInit(void) {
337
338 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
339 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX);
340 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
341
342 /* Bitbang the transmitter */
343 SHORT_COIL;
344 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
345 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
346 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
347
348 // reserve a cardmem, meaning we can use the tracelog function in bigbuff easier.
349 cardmem = BigBuf_get_EM_addr();
350 memset(cardmem, 0x00, LEGIC_CARD_MEMSIZE);
351
352 clear_trace();
353 set_tracing(TRUE);
354 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
355
356 StartTicks();
357 }
358
359 // Switch off carrier, make sure tag is reset
360 static void switch_off_tag_rwd(void) {
361 SHORT_COIL;
362 WaitUS(20);
363 WDT_HIT();
364 }
365
366 // calculate crc4 for a legic READ command
367 static uint32_t legic4Crc(uint8_t cmd, uint16_t byte_index, uint8_t value, uint8_t cmd_sz) {
368 crc_clear(&legic_crc);
369 uint32_t temp = (value << cmd_sz) | (byte_index << 1) | cmd;
370 crc_update(&legic_crc, temp, cmd_sz + 8 );
371 return crc_finish(&legic_crc);
372 }
373
374 int legic_read_byte( uint16_t index, uint8_t cmd_sz) {
375
376 uint8_t byte, crc, calcCrc = 0;
377 uint32_t cmd = (index << 1) | LEGIC_READ;
378
379 // 90ticks = 60us (should be 100us but crc calc takes time.)
380 //WaitTicks(330); // 330ticks prng(4) - works
381 WaitTicks(240); // 240ticks prng(3) - works
382
383 frame_sendAsReader(cmd, cmd_sz);
384 frame_receiveAsReader(&current_frame, 12);
385
386 // CRC check.
387 byte = BYTEx(current_frame.data, 0);
388 crc = BYTEx(current_frame.data, 1);
389 calcCrc = legic4Crc(LEGIC_READ, index, byte, cmd_sz);
390
391 if( calcCrc != crc ) {
392 Dbprintf("!!! crc mismatch: %x != %x !!!", calcCrc, crc);
393 return -1;
394 }
395
396 legic_prng_forward(3);
397 return byte;
398 }
399
400 /*
401 * - assemble a write_cmd_frame with crc and send it
402 * - wait until the tag sends back an ACK ('1' bit unencrypted)
403 * - forward the prng based on the timing
404 */
405 bool legic_write_byte(uint16_t index, uint8_t byte, uint8_t addr_sz) {
406
407 bool isOK = false;
408 int8_t i = 40;
409 uint8_t edges = 0;
410 uint8_t cmd_sz = addr_sz+1+8+4; //crc+data+cmd;
411 uint32_t steps = 0, next_bit_at, start, crc, old_level = 0;
412
413 /*
414 crc_clear(&legic_crc);
415 crc_update(&legic_crc, 0, 1); // CMD_WRITE
416 crc_update(&legic_crc, index, addr_sz);
417 crc_update(&legic_crc, byte, 8);
418 crc = crc_finish(&legic_crc);
419 */
420 crc = legic4Crc(LEGIC_WRITE, index, byte, addr_sz+1);
421
422 // send write command
423 uint32_t cmd = LEGIC_WRITE;
424 cmd |= index << 1; // index
425 cmd |= byte << (addr_sz+1); // Data
426 cmd |= (crc & 0xF ) << (addr_sz+1+8); // CRC
427
428 /* Bitbang the response */
429 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
430
431 legic_prng_forward(2);
432 WaitTicks(330);
433
434 frame_sendAsReader(cmd, cmd_sz);
435
436 LINE_IN;
437
438 start = GET_TICKS;
439
440 // ACK, - one single "1" bit after 3.6ms
441 // 3.6ms = 3600us * 1.5 = 5400ticks.
442 WaitTicks(5300);
443
444 next_bit_at = GET_TICKS + TAG_BIT_PERIOD;
445
446 while ( i-- ) {
447 WDT_HIT();
448 edges = 0;
449 while ( GET_TICKS < next_bit_at) {
450
451 volatile uint32_t level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
452
453 if (level != old_level)
454 ++edges;
455
456 old_level = level;
457 }
458
459 next_bit_at += TAG_BIT_PERIOD;
460
461 // We expect 42 edges (ONE)
462 if(edges > 20 ) {
463 steps = ( (GET_TICKS - start) / TAG_BIT_PERIOD);
464 legic_prng_forward(steps);
465 isOK = true;
466 goto OUT;
467 }
468 }
469
470 Dbprintf("ice: i == %d",i);
471
472 OUT: ;
473 // log
474 uint8_t cmdbytes[] = {1, isOK, BYTEx(steps, 0), BYTEx(steps, 1) };
475 LogTrace(cmdbytes, sizeof(cmdbytes), start, GET_TICKS, NULL, FALSE);
476 return isOK;
477 }
478
479 int LegicRfReader(uint16_t offset, uint16_t len, uint8_t iv) {
480
481 uint16_t i = 0;
482 uint8_t isOK = 1;
483 legic_card_select_t card;
484
485 LegicCommonInit();
486
487 if ( legic_select_card_iv(&card, iv) ) {
488 isOK = 0;
489 goto OUT;
490 }
491
492 if (len + offset >= card.cardsize)
493 len = card.cardsize - offset;
494
495 LED_B_ON();
496 while (i < len) {
497 int r = legic_read_byte(offset + i, card.cmdsize);
498
499 if (r == -1 || BUTTON_PRESS()) {
500 if ( MF_DBGLEVEL >= 2) DbpString("operation aborted");
501 isOK = 0;
502 goto OUT;
503 }
504 cardmem[i++] = r;
505 WDT_HIT();
506 }
507
508 OUT:
509 WDT_HIT();
510 switch_off_tag_rwd();
511 LEDsoff();
512 cmd_send(CMD_ACK, isOK, len, 0, cardmem, len);
513 return 0;
514 }
515
516 void LegicRfWriter(uint16_t offset, uint16_t len, uint8_t iv, uint8_t *data) {
517
518 #define LOWERLIMIT 4
519 uint8_t isOK = 1;
520 legic_card_select_t card;
521
522 // uid NOT is writeable.
523 if ( offset <= LOWERLIMIT ) {
524 isOK = 0;
525 goto OUT;
526 }
527
528 LegicCommonInit();
529
530 if ( legic_select_card_iv(&card, iv) ) {
531 isOK = 0;
532 goto OUT;
533 }
534
535 if ( len + offset + LOWERLIMIT >= card.cardsize) {
536 isOK = 0;
537 goto OUT;
538 }
539
540 LED_B_ON();
541 while( len > 0 ) {
542 --len;
543 if ( !legic_write_byte( len + offset, data[len], card.addrsize) ) {
544 Dbprintf("operation failed | %d | %d | %d", len + offset, len, data[len] );
545 isOK = 0;
546 goto OUT;
547 }
548 WDT_HIT();
549 }
550 OUT:
551 cmd_send(CMD_ACK, isOK, 0,0,0,0);
552 switch_off_tag_rwd();
553 LEDsoff();
554 }
555
556 int legic_select_card_iv(legic_card_select_t *p_card, uint8_t iv){
557
558 if ( p_card == NULL ) return 1;
559
560 p_card->tagtype = setup_phase_reader(iv);
561
562 switch(p_card->tagtype) {
563 case 0x0d:
564 p_card->cmdsize = 6;
565 p_card->addrsize = 5;
566 p_card->cardsize = 22;
567 break;
568 case 0x1d:
569 p_card->cmdsize = 9;
570 p_card->addrsize = 8;
571 p_card->cardsize = 256;
572 break;
573 case 0x3d:
574 p_card->cmdsize = 11;
575 p_card->addrsize = 10;
576 p_card->cardsize = 1024;
577 break;
578 default:
579 p_card->cmdsize = 0;
580 p_card->addrsize = 0;
581 p_card->cardsize = 0;
582 return 2;
583 }
584 return 0;
585 }
586 int legic_select_card(legic_card_select_t *p_card){
587 return legic_select_card_iv(p_card, 0x01);
588 }
589
590 //-----------------------------------------------------------------------------
591 // Work with emulator memory
592 //
593 // Note: we call FpgaDownloadAndGo(FPGA_BITSTREAM_HF) here although FPGA is not
594 // involved in dealing with emulator memory. But if it is called later, it might
595 // destroy the Emulator Memory.
596 //-----------------------------------------------------------------------------
597 // arg0 = offset
598 // arg1 = num of bytes
599 void LegicEMemSet(uint32_t arg0, uint32_t arg1, uint8_t *data) {
600 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
601 legic_emlset_mem(data, arg0, arg1);
602 }
603 // arg0 = offset
604 // arg1 = num of bytes
605 void LegicEMemGet(uint32_t arg0, uint32_t arg1) {
606 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
607 uint8_t buf[USB_CMD_DATA_SIZE] = {0x00};
608 legic_emlget_mem(buf, arg0, arg1);
609 LED_B_ON();
610 cmd_send(CMD_ACK, arg0, arg1, 0, buf, USB_CMD_DATA_SIZE);
611 LED_B_OFF();
612 }
613 void legic_emlset_mem(uint8_t *data, int offset, int numofbytes) {
614 cardmem = BigBuf_get_EM_addr();
615 memcpy(cardmem + offset, data, numofbytes);
616 }
617 void legic_emlget_mem(uint8_t *data, int offset, int numofbytes) {
618 cardmem = BigBuf_get_EM_addr();
619 memcpy(data, cardmem + offset, numofbytes);
620 }
621
622 void LegicRfInfo(void){
623
624 int r;
625
626 uint8_t buf[sizeof(legic_card_select_t)] = {0x00};
627 legic_card_select_t *card = (legic_card_select_t*) buf;
628
629 LegicCommonInit();
630
631 if ( legic_select_card(card) ) {
632 cmd_send(CMD_ACK,0,0,0,0,0);
633 goto OUT;
634 }
635
636 // read UID bytes
637 for ( uint8_t i = 0; i < sizeof(card->uid); ++i) {
638 r = legic_read_byte(i, card->cmdsize);
639 if ( r == -1 ) {
640 cmd_send(CMD_ACK,0,0,0,0,0);
641 goto OUT;
642 }
643 card->uid[i] = r & 0xFF;
644 }
645
646 // MCC byte.
647 r = legic_read_byte(4, card->cmdsize);
648 uint32_t calc_mcc = CRC8Legic(card->uid, 4);;
649 if ( r != calc_mcc) {
650 cmd_send(CMD_ACK,0,0,0,0,0);
651 goto OUT;
652 }
653
654 // OK
655 cmd_send(CMD_ACK, 1, 0, 0, buf, sizeof(legic_card_select_t));
656
657 OUT:
658 switch_off_tag_rwd();
659 LEDsoff();
660 }
661
662 /* Handle (whether to respond) a frame in tag mode
663 * Only called when simulating a tag.
664 */
665 static void frame_handle_tag(struct legic_frame const * const f)
666 {
667 // log
668 //uint8_t cmdbytes[] = {bits, BYTEx(data, 0), BYTEx(data, 1)};
669 //LogTrace(cmdbytes, sizeof(cmdbytes), starttime, GET_TICKS, NULL, FALSE);
670
671 cardmem = BigBuf_get_EM_addr();
672
673 /* First Part of Handshake (IV) */
674 if(f->bits == 7) {
675
676 LED_C_ON();
677
678 // Reset prng timer
679 ResetTimer(prng_timer);
680
681 // IV from reader.
682 legic_prng_init(f->data);
683
684 // We should have three tagtypes with three different answers.
685 frame_send_tag(0x3d, 6); /* 0x3d^0x26 = 0x1B */
686
687 legic_state = STATE_IV;
688 legic_read_count = 0;
689 legic_prng_bc = 0;
690 legic_prng_iv = f->data;
691
692
693 ResetTimer(timer);
694 WaitUS(280);
695 return;
696 }
697
698 /* 0x19==??? */
699 if(legic_state == STATE_IV) {
700 uint32_t local_key = get_key_stream(3, 6);
701 int xored = 0x39 ^ local_key;
702 if((f->bits == 6) && (f->data == xored)) {
703 legic_state = STATE_CON;
704
705 ResetTimer(timer);
706 WaitUS(200);
707 return;
708
709 } else {
710 legic_state = STATE_DISCON;
711 LED_C_OFF();
712 Dbprintf("iv: %02x frame: %02x key: %02x xored: %02x", legic_prng_iv, f->data, local_key, xored);
713 return;
714 }
715 }
716
717 /* Read */
718 if(f->bits == 11) {
719 if(legic_state == STATE_CON) {
720 uint32_t key = get_key_stream(2, 11); //legic_phase_drift, 11);
721 uint16_t addr = f->data ^ key;
722 addr >>= 1;
723 uint8_t data = cardmem[addr];
724 int hash = legic4Crc(LEGIC_READ, addr, data, 11) << 8;
725
726 legic_read_count++;
727 legic_prng_forward(legic_reqresp_drift);
728
729 frame_send_tag(hash | data, 12);
730 ResetTimer(timer);
731 legic_prng_forward(2);
732 WaitTicks(330);
733 return;
734 }
735 }
736
737 /* Write */
738 if(f->bits == 23) {
739 uint32_t key = get_key_stream(-1, 23); //legic_frame_drift, 23);
740 uint16_t addr = f->data ^ key;
741 addr >>= 1;
742 addr &= 0x3ff;
743 uint32_t data = f->data ^ key;
744 data >>= 11;
745 data &= 0xff;
746
747 cardmem[addr] = data;
748 /* write command */
749 legic_state = STATE_DISCON;
750 LED_C_OFF();
751 Dbprintf("write - addr: %x, data: %x", addr, data);
752 // should send a ACK within 3.5ms too
753 return;
754 }
755
756 if(legic_state != STATE_DISCON) {
757 Dbprintf("Unexpected: sz:%u, Data:%03.3x, State:%u, Count:%u", f->bits, f->data, legic_state, legic_read_count);
758 Dbprintf("IV: %03.3x", legic_prng_iv);
759 }
760
761 legic_state = STATE_DISCON;
762 legic_read_count = 0;
763 SpinDelay(10);
764 LED_C_OFF();
765 return;
766 }
767
768 /* Read bit by bit untill full frame is received
769 * Call to process frame end answer
770 */
771 static void emit(int bit) {
772
773 switch (bit) {
774 case 1:
775 frame_append_bit(&current_frame, 1);
776 break;
777 case 0:
778 frame_append_bit(&current_frame, 0);
779 break;
780 default:
781 if(current_frame.bits <= 4) {
782 frame_clean(&current_frame);
783 } else {
784 frame_handle_tag(&current_frame);
785 frame_clean(&current_frame);
786 }
787 WDT_HIT();
788 break;
789 }
790 }
791
792 void LegicRfSimulate(int phase, int frame, int reqresp)
793 {
794 /* ADC path high-frequency peak detector, FPGA in high-frequency simulator mode,
795 * modulation mode set to 212kHz subcarrier. We are getting the incoming raw
796 * envelope waveform on DIN and should send our response on DOUT.
797 *
798 * The LEGIC RF protocol is pulse-pause-encoding from reader to card, so we'll
799 * measure the time between two rising edges on DIN, and no encoding on the
800 * subcarrier from card to reader, so we'll just shift out our verbatim data
801 * on DOUT, 1 bit is 100us. The time from reader to card frame is still unclear,
802 * seems to be 300us-ish.
803 */
804
805 int old_level = 0, active = 0;
806 legic_state = STATE_DISCON;
807
808 legic_phase_drift = phase;
809 legic_frame_drift = frame;
810 legic_reqresp_drift = reqresp;
811
812 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
813 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
814 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_212K);
815
816 /* Bitbang the receiver */
817 LINE_IN;
818
819 // need a way to determine which tagtype we are simulating
820
821 // hook up emulator memory
822 cardmem = BigBuf_get_EM_addr();
823
824 clear_trace();
825 set_tracing(TRUE);
826
827 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
828
829 StartTicks();
830
831 LED_B_ON();
832 DbpString("Starting Legic emulator, press button to end");
833
834 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
835 volatile uint32_t level = !!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
836
837 uint32_t time = GET_TICKS;
838
839 if (level != old_level) {
840
841 if (level) {
842
843 ResetTicks();
844
845 if (FUZZ_EQUAL(time, RWD_TIME_1, RWD_TIME_FUZZ)) {
846 /* 1 bit */
847 emit(1);
848 active = 1;
849 LED_A_ON();
850 } else if (FUZZ_EQUAL(time, RWD_TIME_0, RWD_TIME_FUZZ)) {
851 /* 0 bit */
852 emit(0);
853 active = 1;
854 LED_A_ON();
855 } else if (active) {
856 /* invalid */
857 emit(-1);
858 active = 0;
859 LED_A_OFF();
860 }
861 }
862 }
863
864 /* Frame end */
865 if(time >= (RWD_TIME_1+RWD_TIME_FUZZ) && active) {
866 emit(-1);
867 active = 0;
868 LED_A_OFF();
869 }
870
871 /*
872 * Disable the counter, Then wait for the clock to acknowledge the
873 * shutdown in its status register. Reading the SR has the
874 * side-effect of clearing any pending state in there.
875 */
876 if(time >= (20*RWD_TIME_1) && (timer->TC_SR & AT91C_TC_CLKSTA))
877 StopTicks();
878
879 old_level = level;
880 WDT_HIT();
881 }
882
883 WDT_HIT();
884 switch_off_tag_rwd();
885 LEDsoff();
886 cmd_send(CMD_ACK, 1, 0, 0, 0, 0);
887 }
888
889 //-----------------------------------------------------------------------------
890 // Code up a string of octets at layer 2 (including CRC, we don't generate
891 // that here) so that they can be transmitted to the reader. Doesn't transmit
892 // them yet, just leaves them ready to send in ToSend[].
893 //-----------------------------------------------------------------------------
894 // static void CodeLegicAsTag(const uint8_t *cmd, int len)
895 // {
896 // int i;
897
898 // ToSendReset();
899
900 // // Transmit a burst of ones, as the initial thing that lets the
901 // // reader get phase sync. This (TR1) must be > 80/fs, per spec,
902 // // but tag that I've tried (a Paypass) exceeds that by a fair bit,
903 // // so I will too.
904 // for(i = 0; i < 20; i++) {
905 // ToSendStuffBit(1);
906 // ToSendStuffBit(1);
907 // ToSendStuffBit(1);
908 // ToSendStuffBit(1);
909 // }
910
911 // // Send SOF.
912 // for(i = 0; i < 10; i++) {
913 // ToSendStuffBit(0);
914 // ToSendStuffBit(0);
915 // ToSendStuffBit(0);
916 // ToSendStuffBit(0);
917 // }
918 // for(i = 0; i < 2; i++) {
919 // ToSendStuffBit(1);
920 // ToSendStuffBit(1);
921 // ToSendStuffBit(1);
922 // ToSendStuffBit(1);
923 // }
924
925 // for(i = 0; i < len; i++) {
926 // int j;
927 // uint8_t b = cmd[i];
928
929 // // Start bit
930 // ToSendStuffBit(0);
931 // ToSendStuffBit(0);
932 // ToSendStuffBit(0);
933 // ToSendStuffBit(0);
934
935 // // Data bits
936 // for(j = 0; j < 8; j++) {
937 // if(b & 1) {
938 // ToSendStuffBit(1);
939 // ToSendStuffBit(1);
940 // ToSendStuffBit(1);
941 // ToSendStuffBit(1);
942 // } else {
943 // ToSendStuffBit(0);
944 // ToSendStuffBit(0);
945 // ToSendStuffBit(0);
946 // ToSendStuffBit(0);
947 // }
948 // b >>= 1;
949 // }
950
951 // // Stop bit
952 // ToSendStuffBit(1);
953 // ToSendStuffBit(1);
954 // ToSendStuffBit(1);
955 // ToSendStuffBit(1);
956 // }
957
958 // // Send EOF.
959 // for(i = 0; i < 10; i++) {
960 // ToSendStuffBit(0);
961 // ToSendStuffBit(0);
962 // ToSendStuffBit(0);
963 // ToSendStuffBit(0);
964 // }
965 // for(i = 0; i < 2; i++) {
966 // ToSendStuffBit(1);
967 // ToSendStuffBit(1);
968 // ToSendStuffBit(1);
969 // ToSendStuffBit(1);
970 // }
971
972 // // Convert from last byte pos to length
973 // ToSendMax++;
974 // }
975
976 //-----------------------------------------------------------------------------
977 // The software UART that receives commands from the reader, and its state
978 // variables.
979 //-----------------------------------------------------------------------------
980 /*
981 static struct {
982 enum {
983 STATE_UNSYNCD,
984 STATE_GOT_FALLING_EDGE_OF_SOF,
985 STATE_AWAITING_START_BIT,
986 STATE_RECEIVING_DATA
987 } state;
988 uint16_t shiftReg;
989 int bitCnt;
990 int byteCnt;
991 int byteCntMax;
992 int posCnt;
993 uint8_t *output;
994 } Uart;
995 */
996 /* Receive & handle a bit coming from the reader.
997 *
998 * This function is called 4 times per bit (every 2 subcarrier cycles).
999 * Subcarrier frequency fs is 212kHz, 1/fs = 4,72us, i.e. function is called every 9,44us
1000 *
1001 * LED handling:
1002 * LED A -> ON once we have received the SOF and are expecting the rest.
1003 * LED A -> OFF once we have received EOF or are in error state or unsynced
1004 *
1005 * Returns: true if we received a EOF
1006 * false if we are still waiting for some more
1007 */
1008 // static RAMFUNC int HandleLegicUartBit(uint8_t bit)
1009 // {
1010 // switch(Uart.state) {
1011 // case STATE_UNSYNCD:
1012 // if(!bit) {
1013 // // we went low, so this could be the beginning of an SOF
1014 // Uart.state = STATE_GOT_FALLING_EDGE_OF_SOF;
1015 // Uart.posCnt = 0;
1016 // Uart.bitCnt = 0;
1017 // }
1018 // break;
1019
1020 // case STATE_GOT_FALLING_EDGE_OF_SOF:
1021 // Uart.posCnt++;
1022 // if(Uart.posCnt == 2) { // sample every 4 1/fs in the middle of a bit
1023 // if(bit) {
1024 // if(Uart.bitCnt > 9) {
1025 // // we've seen enough consecutive
1026 // // zeros that it's a valid SOF
1027 // Uart.posCnt = 0;
1028 // Uart.byteCnt = 0;
1029 // Uart.state = STATE_AWAITING_START_BIT;
1030 // LED_A_ON(); // Indicate we got a valid SOF
1031 // } else {
1032 // // didn't stay down long enough
1033 // // before going high, error
1034 // Uart.state = STATE_UNSYNCD;
1035 // }
1036 // } else {
1037 // // do nothing, keep waiting
1038 // }
1039 // Uart.bitCnt++;
1040 // }
1041 // if(Uart.posCnt >= 4) Uart.posCnt = 0;
1042 // if(Uart.bitCnt > 12) {
1043 // // Give up if we see too many zeros without
1044 // // a one, too.
1045 // LED_A_OFF();
1046 // Uart.state = STATE_UNSYNCD;
1047 // }
1048 // break;
1049
1050 // case STATE_AWAITING_START_BIT:
1051 // Uart.posCnt++;
1052 // if(bit) {
1053 // if(Uart.posCnt > 50/2) { // max 57us between characters = 49 1/fs, max 3 etus after low phase of SOF = 24 1/fs
1054 // // stayed high for too long between
1055 // // characters, error
1056 // Uart.state = STATE_UNSYNCD;
1057 // }
1058 // } else {
1059 // // falling edge, this starts the data byte
1060 // Uart.posCnt = 0;
1061 // Uart.bitCnt = 0;
1062 // Uart.shiftReg = 0;
1063 // Uart.state = STATE_RECEIVING_DATA;
1064 // }
1065 // break;
1066
1067 // case STATE_RECEIVING_DATA:
1068 // Uart.posCnt++;
1069 // if(Uart.posCnt == 2) {
1070 // // time to sample a bit
1071 // Uart.shiftReg >>= 1;
1072 // if(bit) {
1073 // Uart.shiftReg |= 0x200;
1074 // }
1075 // Uart.bitCnt++;
1076 // }
1077 // if(Uart.posCnt >= 4) {
1078 // Uart.posCnt = 0;
1079 // }
1080 // if(Uart.bitCnt == 10) {
1081 // if((Uart.shiftReg & 0x200) && !(Uart.shiftReg & 0x001))
1082 // {
1083 // // this is a data byte, with correct
1084 // // start and stop bits
1085 // Uart.output[Uart.byteCnt] = (Uart.shiftReg >> 1) & 0xff;
1086 // Uart.byteCnt++;
1087
1088 // if(Uart.byteCnt >= Uart.byteCntMax) {
1089 // // Buffer overflowed, give up
1090 // LED_A_OFF();
1091 // Uart.state = STATE_UNSYNCD;
1092 // } else {
1093 // // so get the next byte now
1094 // Uart.posCnt = 0;
1095 // Uart.state = STATE_AWAITING_START_BIT;
1096 // }
1097 // } else if (Uart.shiftReg == 0x000) {
1098 // // this is an EOF byte
1099 // LED_A_OFF(); // Finished receiving
1100 // Uart.state = STATE_UNSYNCD;
1101 // if (Uart.byteCnt != 0) {
1102 // return TRUE;
1103 // }
1104 // } else {
1105 // // this is an error
1106 // LED_A_OFF();
1107 // Uart.state = STATE_UNSYNCD;
1108 // }
1109 // }
1110 // break;
1111
1112 // default:
1113 // LED_A_OFF();
1114 // Uart.state = STATE_UNSYNCD;
1115 // break;
1116 // }
1117
1118 // return FALSE;
1119 // }
1120 /*
1121
1122 static void UartReset() {
1123 Uart.byteCntMax = 3;
1124 Uart.state = STATE_UNSYNCD;
1125 Uart.byteCnt = 0;
1126 Uart.bitCnt = 0;
1127 Uart.posCnt = 0;
1128 memset(Uart.output, 0x00, 3);
1129 }
1130 */
1131 // static void UartInit(uint8_t *data) {
1132 // Uart.output = data;
1133 // UartReset();
1134 // }
1135
1136 //=============================================================================
1137 // An LEGIC reader. We take layer two commands, code them
1138 // appropriately, and then send them to the tag. We then listen for the
1139 // tag's response, which we leave in the buffer to be demodulated on the
1140 // PC side.
1141 //=============================================================================
1142 /*
1143 static struct {
1144 enum {
1145 DEMOD_UNSYNCD,
1146 DEMOD_PHASE_REF_TRAINING,
1147 DEMOD_AWAITING_FALLING_EDGE_OF_SOF,
1148 DEMOD_GOT_FALLING_EDGE_OF_SOF,
1149 DEMOD_AWAITING_START_BIT,
1150 DEMOD_RECEIVING_DATA
1151 } state;
1152 int bitCount;
1153 int posCount;
1154 int thisBit;
1155 uint16_t shiftReg;
1156 uint8_t *output;
1157 int len;
1158 int sumI;
1159 int sumQ;
1160 } Demod;
1161 */
1162 /*
1163 * Handles reception of a bit from the tag
1164 *
1165 * This function is called 2 times per bit (every 4 subcarrier cycles).
1166 * Subcarrier frequency fs is 212kHz, 1/fs = 4,72us, i.e. function is called every 9,44us
1167 *
1168 * LED handling:
1169 * LED C -> ON once we have received the SOF and are expecting the rest.
1170 * LED C -> OFF once we have received EOF or are unsynced
1171 *
1172 * Returns: true if we received a EOF
1173 * false if we are still waiting for some more
1174 *
1175 */
1176
1177 /*
1178 static RAMFUNC int HandleLegicSamplesDemod(int ci, int cq)
1179 {
1180 int v = 0;
1181 int ai = ABS(ci);
1182 int aq = ABS(cq);
1183 int halfci = (ai >> 1);
1184 int halfcq = (aq >> 1);
1185
1186 switch(Demod.state) {
1187 case DEMOD_UNSYNCD:
1188
1189 CHECK_FOR_SUBCARRIER()
1190
1191 if(v > SUBCARRIER_DETECT_THRESHOLD) { // subcarrier detected
1192 Demod.state = DEMOD_PHASE_REF_TRAINING;
1193 Demod.sumI = ci;
1194 Demod.sumQ = cq;
1195 Demod.posCount = 1;
1196 }
1197 break;
1198
1199 case DEMOD_PHASE_REF_TRAINING:
1200 if(Demod.posCount < 8) {
1201
1202 CHECK_FOR_SUBCARRIER()
1203
1204 if (v > SUBCARRIER_DETECT_THRESHOLD) {
1205 // set the reference phase (will code a logic '1') by averaging over 32 1/fs.
1206 // note: synchronization time > 80 1/fs
1207 Demod.sumI += ci;
1208 Demod.sumQ += cq;
1209 ++Demod.posCount;
1210 } else {
1211 // subcarrier lost
1212 Demod.state = DEMOD_UNSYNCD;
1213 }
1214 } else {
1215 Demod.state = DEMOD_AWAITING_FALLING_EDGE_OF_SOF;
1216 }
1217 break;
1218
1219 case DEMOD_AWAITING_FALLING_EDGE_OF_SOF:
1220
1221 MAKE_SOFT_DECISION()
1222
1223 //Dbprintf("ICE: %d %d %d %d %d", v, Demod.sumI, Demod.sumQ, ci, cq );
1224 // logic '0' detected
1225 if (v <= 0) {
1226
1227 Demod.state = DEMOD_GOT_FALLING_EDGE_OF_SOF;
1228
1229 // start of SOF sequence
1230 Demod.posCount = 0;
1231 } else {
1232 // maximum length of TR1 = 200 1/fs
1233 if(Demod.posCount > 25*2) Demod.state = DEMOD_UNSYNCD;
1234 }
1235 ++Demod.posCount;
1236 break;
1237
1238 case DEMOD_GOT_FALLING_EDGE_OF_SOF:
1239 ++Demod.posCount;
1240
1241 MAKE_SOFT_DECISION()
1242
1243 if(v > 0) {
1244 // low phase of SOF too short (< 9 etu). Note: spec is >= 10, but FPGA tends to "smear" edges
1245 if(Demod.posCount < 10*2) {
1246 Demod.state = DEMOD_UNSYNCD;
1247 } else {
1248 LED_C_ON(); // Got SOF
1249 Demod.state = DEMOD_AWAITING_START_BIT;
1250 Demod.posCount = 0;
1251 Demod.len = 0;
1252 }
1253 } else {
1254 // low phase of SOF too long (> 12 etu)
1255 if(Demod.posCount > 13*2) {
1256 Demod.state = DEMOD_UNSYNCD;
1257 LED_C_OFF();
1258 }
1259 }
1260 break;
1261
1262 case DEMOD_AWAITING_START_BIT:
1263 ++Demod.posCount;
1264
1265 MAKE_SOFT_DECISION()
1266
1267 if(v > 0) {
1268 // max 19us between characters = 16 1/fs, max 3 etu after low phase of SOF = 24 1/fs
1269 if(Demod.posCount > 3*2) {
1270 Demod.state = DEMOD_UNSYNCD;
1271 LED_C_OFF();
1272 }
1273 } else {
1274 // start bit detected
1275 Demod.bitCount = 0;
1276 Demod.posCount = 1; // this was the first half
1277 Demod.thisBit = v;
1278 Demod.shiftReg = 0;
1279 Demod.state = DEMOD_RECEIVING_DATA;
1280 }
1281 break;
1282
1283 case DEMOD_RECEIVING_DATA:
1284
1285 MAKE_SOFT_DECISION()
1286
1287 if(Demod.posCount == 0) {
1288 // first half of bit
1289 Demod.thisBit = v;
1290 Demod.posCount = 1;
1291 } else {
1292 // second half of bit
1293 Demod.thisBit += v;
1294 Demod.shiftReg >>= 1;
1295 // logic '1'
1296 if(Demod.thisBit > 0)
1297 Demod.shiftReg |= 0x200;
1298
1299 ++Demod.bitCount;
1300
1301 if(Demod.bitCount == 10) {
1302
1303 uint16_t s = Demod.shiftReg;
1304
1305 if((s & 0x200) && !(s & 0x001)) {
1306 // stop bit == '1', start bit == '0'
1307 uint8_t b = (s >> 1);
1308 Demod.output[Demod.len] = b;
1309 ++Demod.len;
1310 Demod.state = DEMOD_AWAITING_START_BIT;
1311 } else {
1312 Demod.state = DEMOD_UNSYNCD;
1313 LED_C_OFF();
1314
1315 if(s == 0x000) {
1316 // This is EOF (start, stop and all data bits == '0'
1317 return TRUE;
1318 }
1319 }
1320 }
1321 Demod.posCount = 0;
1322 }
1323 break;
1324
1325 default:
1326 Demod.state = DEMOD_UNSYNCD;
1327 LED_C_OFF();
1328 break;
1329 }
1330 return FALSE;
1331 }
1332 */
1333 /*
1334 // Clear out the state of the "UART" that receives from the tag.
1335 static void DemodReset() {
1336 Demod.len = 0;
1337 Demod.state = DEMOD_UNSYNCD;
1338 Demod.posCount = 0;
1339 Demod.sumI = 0;
1340 Demod.sumQ = 0;
1341 Demod.bitCount = 0;
1342 Demod.thisBit = 0;
1343 Demod.shiftReg = 0;
1344 memset(Demod.output, 0x00, 3);
1345 }
1346
1347 static void DemodInit(uint8_t *data) {
1348 Demod.output = data;
1349 DemodReset();
1350 }
1351 */
1352
1353 /*
1354 * Demodulate the samples we received from the tag, also log to tracebuffer
1355 * quiet: set to 'TRUE' to disable debug output
1356 */
1357
1358 /*
1359 #define LEGIC_DMA_BUFFER_SIZE 256
1360
1361 static void GetSamplesForLegicDemod(int n, bool quiet)
1362 {
1363 int max = 0;
1364 bool gotFrame = FALSE;
1365 int lastRxCounter = LEGIC_DMA_BUFFER_SIZE;
1366 int ci, cq, samples = 0;
1367
1368 BigBuf_free();
1369
1370 // And put the FPGA in the appropriate mode
1371 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_QUARTER_FREQ);
1372
1373 // The response (tag -> reader) that we're receiving.
1374 // Set up the demodulator for tag -> reader responses.
1375 DemodInit(BigBuf_malloc(MAX_FRAME_SIZE));
1376
1377 // The DMA buffer, used to stream samples from the FPGA
1378 int8_t *dmaBuf = (int8_t*) BigBuf_malloc(LEGIC_DMA_BUFFER_SIZE);
1379 int8_t *upTo = dmaBuf;
1380
1381 // Setup and start DMA.
1382 if ( !FpgaSetupSscDma((uint8_t*) dmaBuf, LEGIC_DMA_BUFFER_SIZE) ){
1383 if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting");
1384 return;
1385 }
1386
1387 // Signal field is ON with the appropriate LED:
1388 LED_D_ON();
1389 for(;;) {
1390 int behindBy = lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR;
1391 if(behindBy > max) max = behindBy;
1392
1393 while(((lastRxCounter-AT91C_BASE_PDC_SSC->PDC_RCR) & (LEGIC_DMA_BUFFER_SIZE-1)) > 2) {
1394 ci = upTo[0];
1395 cq = upTo[1];
1396 upTo += 2;
1397 if(upTo >= dmaBuf + LEGIC_DMA_BUFFER_SIZE) {
1398 upTo = dmaBuf;
1399 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo;
1400 AT91C_BASE_PDC_SSC->PDC_RNCR = LEGIC_DMA_BUFFER_SIZE;
1401 }
1402 lastRxCounter -= 2;
1403 if(lastRxCounter <= 0)
1404 lastRxCounter = LEGIC_DMA_BUFFER_SIZE;
1405
1406 samples += 2;
1407
1408 gotFrame = HandleLegicSamplesDemod(ci , cq );
1409 if ( gotFrame )
1410 break;
1411 }
1412
1413 if(samples > n || gotFrame)
1414 break;
1415 }
1416
1417 FpgaDisableSscDma();
1418
1419 if (!quiet && Demod.len == 0) {
1420 Dbprintf("max behindby = %d, samples = %d, gotFrame = %d, Demod.len = %d, Demod.sumI = %d, Demod.sumQ = %d",
1421 max,
1422 samples,
1423 gotFrame,
1424 Demod.len,
1425 Demod.sumI,
1426 Demod.sumQ
1427 );
1428 }
1429
1430 //Tracing
1431 if (Demod.len > 0) {
1432 uint8_t parity[MAX_PARITY_SIZE] = {0x00};
1433 LogTrace(Demod.output, Demod.len, 0, 0, parity, FALSE);
1434 }
1435 }
1436
1437 */
1438
1439 //-----------------------------------------------------------------------------
1440 // Transmit the command (to the tag) that was placed in ToSend[].
1441 //-----------------------------------------------------------------------------
1442 /*
1443 static void TransmitForLegic(void)
1444 {
1445 int c;
1446
1447 FpgaSetupSsc();
1448
1449 while(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY))
1450 AT91C_BASE_SSC->SSC_THR = 0xff;
1451
1452 // Signal field is ON with the appropriate Red LED
1453 LED_D_ON();
1454
1455 // Signal we are transmitting with the Green LED
1456 LED_B_ON();
1457 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
1458
1459 for(c = 0; c < 10;) {
1460 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1461 AT91C_BASE_SSC->SSC_THR = 0xff;
1462 c++;
1463 }
1464 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1465 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
1466 (void)r;
1467 }
1468 WDT_HIT();
1469 }
1470
1471 c = 0;
1472 for(;;) {
1473 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1474 AT91C_BASE_SSC->SSC_THR = ToSend[c];
1475 legic_prng_forward(1); // forward the lfsr
1476 c++;
1477 if(c >= ToSendMax) {
1478 break;
1479 }
1480 }
1481 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1482 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
1483 (void)r;
1484 }
1485 WDT_HIT();
1486 }
1487 LED_B_OFF();
1488 }
1489 */
1490
1491 //-----------------------------------------------------------------------------
1492 // Code a layer 2 command (string of octets, including CRC) into ToSend[],
1493 // so that it is ready to transmit to the tag using TransmitForLegic().
1494 //-----------------------------------------------------------------------------
1495 /*
1496 static void CodeLegicBitsAsReader(const uint8_t *cmd, uint8_t cmdlen, int bits)
1497 {
1498 int i, j;
1499 uint8_t b;
1500
1501 ToSendReset();
1502
1503 // Send SOF
1504 for(i = 0; i < 7; i++)
1505 ToSendStuffBit(1);
1506
1507
1508 for(i = 0; i < cmdlen; i++) {
1509 // Start bit
1510 ToSendStuffBit(0);
1511
1512 // Data bits
1513 b = cmd[i];
1514 for(j = 0; j < bits; j++) {
1515 if(b & 1) {
1516 ToSendStuffBit(1);
1517 } else {
1518 ToSendStuffBit(0);
1519 }
1520 b >>= 1;
1521 }
1522 }
1523
1524 // Convert from last character reference to length
1525 ++ToSendMax;
1526 }
1527 */
1528 /**
1529 Convenience function to encode, transmit and trace Legic comms
1530 **/
1531 /*
1532 static void CodeAndTransmitLegicAsReader(const uint8_t *cmd, uint8_t cmdlen, int bits)
1533 {
1534 CodeLegicBitsAsReader(cmd, cmdlen, bits);
1535 TransmitForLegic();
1536 if (tracing) {
1537 uint8_t parity[1] = {0x00};
1538 LogTrace(cmd, cmdlen, 0, 0, parity, TRUE);
1539 }
1540 }
1541
1542 */
1543 // Set up LEGIC communication
1544 /*
1545 void ice_legic_setup() {
1546
1547 // standard things.
1548 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1549 BigBuf_free(); BigBuf_Clear_ext(false);
1550 clear_trace();
1551 set_tracing(TRUE);
1552 DemodReset();
1553 UartReset();
1554
1555 // Set up the synchronous serial port
1556 FpgaSetupSsc();
1557
1558 // connect Demodulated Signal to ADC:
1559 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1560
1561 // Signal field is on with the appropriate LED
1562 LED_D_ON();
1563 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
1564 SpinDelay(20);
1565 // Start the timer
1566 //StartCountSspClk();
1567
1568 // initalize CRC
1569 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
1570
1571 // initalize prng
1572 legic_prng_init(0);
1573 }
1574 */
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