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1 //-----------------------------------------------------------------------------
2 // Jonathan Westhues, Sept 2005
3 //
4 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
5 // at your option, any later version. See the LICENSE.txt file for the text of
6 // the license.
7 //-----------------------------------------------------------------------------
8 // Utility functions used in many places, not specific to any piece of code.
9 //-----------------------------------------------------------------------------
10
11 #include "../include/proxmark3.h"
12 #include "util.h"
13 #include "string.h"
14 #include "apps.h"
15
16
17
18 void print_result(char *name, uint8_t *buf, size_t len) {
19 uint8_t *p = buf;
20
21 if ( len % 16 == 0 ) {
22 for(; p-buf < len; p += 16)
23 Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
24 name,
25 p-buf,
26 len,
27 p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7],p[8], p[9], p[10], p[11], p[12], p[13], p[14], p[15]
28 );
29 }
30 else {
31 for(; p-buf < len; p += 8)
32 Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x", name, p-buf, len, p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);
33 }
34 }
35
36 size_t nbytes(size_t nbits) {
37 return (nbits/8)+((nbits%8)>0);
38 }
39
40 uint32_t SwapBits(uint32_t value, int nrbits) {
41 int i;
42 uint32_t newvalue = 0;
43 for(i = 0; i < nrbits; i++) {
44 newvalue ^= ((value >> i) & 1) << (nrbits - 1 - i);
45 }
46 return newvalue;
47 }
48
49 void num_to_bytes(uint64_t n, size_t len, uint8_t* dest)
50 {
51 while (len--) {
52 dest[len] = (uint8_t) n;
53 n >>= 8;
54 }
55 }
56
57 uint64_t bytes_to_num(uint8_t* src, size_t len)
58 {
59 uint64_t num = 0;
60 while (len--)
61 {
62 num = (num << 8) | (*src);
63 src++;
64 }
65 return num;
66 }
67
68 // RotateLeft - Ultralight, Desfire
69 void rol(uint8_t *data, const size_t len){
70 uint8_t first = data[0];
71 for (size_t i = 0; i < len-1; i++) {
72 data[i] = data[i+1];
73 }
74 data[len-1] = first;
75 }
76 void lsl (uint8_t *data, size_t len) {
77 for (size_t n = 0; n < len - 1; n++) {
78 data[n] = (data[n] << 1) | (data[n+1] >> 7);
79 }
80 data[len - 1] <<= 1;
81 }
82
83 int32_t le24toh (uint8_t data[3])
84 {
85 return (data[2] << 16) | (data[1] << 8) | data[0];
86 }
87
88 //added here for parity calulations
89 uint8_t oddparity(uint8_t bt)
90 {
91 uint16_t v = bt;
92 v ^= v >> 4;
93 v &= 0xF;
94 return ((0x9669 >> v) & 1);
95 }
96
97 void LEDsoff()
98 {
99 LED_A_OFF();
100 LED_B_OFF();
101 LED_C_OFF();
102 LED_D_OFF();
103 }
104
105 // LEDs: R(C) O(A) G(B) -- R(D) [1, 2, 4 and 8]
106 void LED(int led, int ms)
107 {
108 if (led & LED_RED)
109 LED_C_ON();
110 if (led & LED_ORANGE)
111 LED_A_ON();
112 if (led & LED_GREEN)
113 LED_B_ON();
114 if (led & LED_RED2)
115 LED_D_ON();
116
117 if (!ms)
118 return;
119
120 SpinDelay(ms);
121
122 if (led & LED_RED)
123 LED_C_OFF();
124 if (led & LED_ORANGE)
125 LED_A_OFF();
126 if (led & LED_GREEN)
127 LED_B_OFF();
128 if (led & LED_RED2)
129 LED_D_OFF();
130 }
131
132
133 // Determine if a button is double clicked, single clicked,
134 // not clicked, or held down (for ms || 1sec)
135 // In general, don't use this function unless you expect a
136 // double click, otherwise it will waste 500ms -- use BUTTON_HELD instead
137 int BUTTON_CLICKED(int ms)
138 {
139 // Up to 500ms in between clicks to mean a double click
140 int ticks = (48000 * (ms ? ms : 1000)) >> 10;
141
142 // If we're not even pressed, forget about it!
143 if (!BUTTON_PRESS())
144 return BUTTON_NO_CLICK;
145
146 // Borrow a PWM unit for my real-time clock
147 AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
148 // 48 MHz / 1024 gives 46.875 kHz
149 AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
150 AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
151 AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;
152
153 uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
154
155 int letoff = 0;
156 for(;;)
157 {
158 uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
159
160 // We haven't let off the button yet
161 if (!letoff)
162 {
163 // We just let it off!
164 if (!BUTTON_PRESS())
165 {
166 letoff = 1;
167
168 // reset our timer for 500ms
169 start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
170 ticks = (48000 * (500)) >> 10;
171 }
172
173 // Still haven't let it off
174 else
175 // Have we held down a full second?
176 if (now == (uint16_t)(start + ticks))
177 return BUTTON_HOLD;
178 }
179
180 // We already let off, did we click again?
181 else
182 // Sweet, double click!
183 if (BUTTON_PRESS())
184 return BUTTON_DOUBLE_CLICK;
185
186 // Have we ran out of time to double click?
187 else
188 if (now == (uint16_t)(start + ticks))
189 // At least we did a single click
190 return BUTTON_SINGLE_CLICK;
191
192 WDT_HIT();
193 }
194
195 // We should never get here
196 return BUTTON_ERROR;
197 }
198
199 // Determine if a button is held down
200 int BUTTON_HELD(int ms)
201 {
202 // If button is held for one second
203 int ticks = (48000 * (ms ? ms : 1000)) >> 10;
204
205 // If we're not even pressed, forget about it!
206 if (!BUTTON_PRESS())
207 return BUTTON_NO_CLICK;
208
209 // Borrow a PWM unit for my real-time clock
210 AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
211 // 48 MHz / 1024 gives 46.875 kHz
212 AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
213 AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
214 AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;
215
216 uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
217
218 for(;;)
219 {
220 uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
221
222 // As soon as our button let go, we didn't hold long enough
223 if (!BUTTON_PRESS())
224 return BUTTON_SINGLE_CLICK;
225
226 // Have we waited the full second?
227 else
228 if (now == (uint16_t)(start + ticks))
229 return BUTTON_HOLD;
230
231 WDT_HIT();
232 }
233
234 // We should never get here
235 return BUTTON_ERROR;
236 }
237
238 // attempt at high resolution microsecond timer
239 // beware: timer counts in 21.3uS increments (1024/48Mhz)
240 void SpinDelayUs(int us)
241 {
242 int ticks = (48*us) >> 10;
243
244 // Borrow a PWM unit for my real-time clock
245 AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
246 // 48 MHz / 1024 gives 46.875 kHz
247 AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
248 AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
249 AT91C_BASE_PWMC_CH0->PWMC_CPRDR = 0xffff;
250
251 uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
252
253 for(;;) {
254 uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
255 if (now == (uint16_t)(start + ticks))
256 return;
257
258 WDT_HIT();
259 }
260 }
261
262 void SpinDelay(int ms)
263 {
264 // convert to uS and call microsecond delay function
265 SpinDelayUs(ms*1000);
266 }
267
268 /* Similar to FpgaGatherVersion this formats stored version information
269 * into a string representation. It takes a pointer to the struct version_information,
270 * verifies the magic properties, then stores a formatted string, prefixed by
271 * prefix in dst.
272 */
273 void FormatVersionInformation(char *dst, int len, const char *prefix, void *version_information)
274 {
275 struct version_information *v = (struct version_information*)version_information;
276 dst[0] = 0;
277 strncat(dst, prefix, len-1);
278 if(v->magic != VERSION_INFORMATION_MAGIC) {
279 strncat(dst, "Missing/Invalid version information", len - strlen(dst) - 1);
280 return;
281 }
282 if(v->versionversion != 1) {
283 strncat(dst, "Version information not understood", len - strlen(dst) - 1);
284 return;
285 }
286 if(!v->present) {
287 strncat(dst, "Version information not available", len - strlen(dst) - 1);
288 return;
289 }
290
291 strncat(dst, v->gitversion, len - strlen(dst) - 1);
292 if(v->clean == 0) {
293 strncat(dst, "-unclean", len - strlen(dst) - 1);
294 } else if(v->clean == 2) {
295 strncat(dst, "-suspect", len - strlen(dst) - 1);
296 }
297
298 strncat(dst, " ", len - strlen(dst) - 1);
299 strncat(dst, v->buildtime, len - strlen(dst) - 1);
300 }
301
302 // -------------------------------------------------------------------------
303 // timer lib
304 // -------------------------------------------------------------------------
305 // test procedure:
306 //
307 // ti = GetTickCount();
308 // SpinDelay(1000);
309 // ti = GetTickCount() - ti;
310 // Dbprintf("timer(1s): %d t=%d", ti, GetTickCount());
311
312 void StartTickCount()
313 {
314 // must be 0x40, but on my cpu - included divider is optimal
315 // 0x20 - 1 ms / bit
316 // 0x40 - 2 ms / bit
317
318 AT91C_BASE_RTTC->RTTC_RTMR = AT91C_RTTC_RTTRST + 0x001D; // was 0x003B
319 }
320
321 /*
322 * Get the current count.
323 */
324 uint32_t RAMFUNC GetTickCount(){
325 return AT91C_BASE_RTTC->RTTC_RTVR;// was * 2;
326 }
327
328 // -------------------------------------------------------------------------
329 // microseconds timer
330 // -------------------------------------------------------------------------
331 void StartCountUS()
332 {
333 AT91C_BASE_PMC->PMC_PCER |= (0x1 << 12) | (0x1 << 13) | (0x1 << 14);
334 // AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC1XC1S_TIOA0;
335 AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
336
337 // fast clock
338 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable
339 AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz)/32 -- tick=1.5mks
340 AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR |
341 AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;
342 AT91C_BASE_TC0->TC_RA = 1;
343 AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000
344
345 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // timer disable
346 AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // from timer 0
347
348 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;
349 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;
350 AT91C_BASE_TCB->TCB_BCR = 1;
351 }
352
353 uint32_t RAMFUNC GetCountUS(){
354 return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV / 15) * 10);
355 }
356
357 static uint32_t GlobalUsCounter = 0;
358
359 uint32_t RAMFUNC GetDeltaCountUS(){
360 uint32_t g_cnt = GetCountUS();
361 uint32_t g_res = g_cnt - GlobalUsCounter;
362 GlobalUsCounter = g_cnt;
363 return g_res;
364 }
365
366
367 // -------------------------------------------------------------------------
368 // Timer for iso14443 commands. Uses ssp_clk from FPGA
369 // -------------------------------------------------------------------------
370 void StartCountSspClk()
371 {
372 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0) | (1 << AT91C_ID_TC1) | (1 << AT91C_ID_TC2); // Enable Clock to all timers
373 AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_TIOA1 // XC0 Clock = TIOA1
374 | AT91C_TCB_TC1XC1S_NONE // XC1 Clock = none
375 | AT91C_TCB_TC2XC2S_TIOA0; // XC2 Clock = TIOA0
376
377 // configure TC1 to create a short pulse on TIOA1 when a rising edge on TIOB1 (= ssp_clk from FPGA) occurs:
378 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // disable TC1
379 AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK // TC1 Clock = MCK(48MHz)/2 = 24MHz
380 | AT91C_TC_CPCSTOP // Stop clock on RC compare
381 | AT91C_TC_EEVTEDG_RISING // Trigger on rising edge of Event
382 | AT91C_TC_EEVT_TIOB // Event-Source: TIOB1 (= ssp_clk from FPGA = 13,56MHz/16)
383 | AT91C_TC_ENETRG // Enable external trigger event
384 | AT91C_TC_WAVESEL_UP // Upmode without automatic trigger on RC compare
385 | AT91C_TC_WAVE // Waveform Mode
386 | AT91C_TC_AEEVT_SET // Set TIOA1 on external event
387 | AT91C_TC_ACPC_CLEAR; // Clear TIOA1 on RC Compare
388 AT91C_BASE_TC1->TC_RC = 0x04; // RC Compare value = 0x04
389
390 // use TC0 to count TIOA1 pulses
391 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // disable TC0
392 AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_XC0 // TC0 clock = XC0 clock = TIOA1
393 | AT91C_TC_WAVE // Waveform Mode
394 | AT91C_TC_WAVESEL_UP // just count
395 | AT91C_TC_ACPA_CLEAR // Clear TIOA0 on RA Compare
396 | AT91C_TC_ACPC_SET; // Set TIOA0 on RC Compare
397 AT91C_BASE_TC0->TC_RA = 1; // RA Compare value = 1; pulse width to TC2
398 AT91C_BASE_TC0->TC_RC = 0; // RC Compare value = 0; increment TC2 on overflow
399
400 // use TC2 to count TIOA0 pulses (giving us a 32bit counter (TC0/TC2) clocked by ssp_clk)
401 AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKDIS; // disable TC2
402 AT91C_BASE_TC2->TC_CMR = AT91C_TC_CLKS_XC2 // TC2 clock = XC2 clock = TIOA0
403 | AT91C_TC_WAVE // Waveform Mode
404 | AT91C_TC_WAVESEL_UP; // just count
405
406 AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN; // enable TC0
407 AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN; // enable TC1
408 AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN; // enable TC2
409
410 //
411 // synchronize the counter with the ssp_frame signal. Note: FPGA must be in any iso14446 mode, otherwise the frame signal would not be present
412 //
413 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME)); // wait for ssp_frame to go high (start of frame)
414 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME); // wait for ssp_frame to be low
415 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)); // wait for ssp_clk to go high
416 // note: up to now two ssp_clk rising edges have passed since the rising edge of ssp_frame
417 // it is now safe to assert a sync signal. This sets all timers to 0 on next active clock edge
418 AT91C_BASE_TCB->TCB_BCR = 1; // assert Sync (set all timers to 0 on next active clock edge)
419 // at the next (3rd) ssp_clk rising edge, TC1 will be reset (and not generate a clock signal to TC0)
420 // at the next (4th) ssp_clk rising edge, TC0 (the low word of our counter) will be reset. From now on,
421 // whenever the last three bits of our counter go 0, we can be sure to be in the middle of a frame transfer.
422 // (just started with the transfer of the 4th Bit).
423 // The high word of the counter (TC2) will not reset until the low word (TC0) overflows. Therefore need to wait quite some time before
424 // we can use the counter.
425 while (AT91C_BASE_TC0->TC_CV < 0xFFF0);
426 }
427
428
429 uint32_t RAMFUNC GetCountSspClk(){
430 uint32_t tmp_count;
431 tmp_count = (AT91C_BASE_TC2->TC_CV << 16) | AT91C_BASE_TC0->TC_CV;
432 if ((tmp_count & 0x0000ffff) == 0) { //small chance that we may have missed an increment in TC2
433 return (AT91C_BASE_TC2->TC_CV << 16);
434 }
435 else {
436 return tmp_count;
437 }
438 }
439
440
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