1 //-----------------------------------------------------------------------------
2 // The FPGA is responsible for interfacing between the A/D, the coil drivers,
3 // and the ARM. In the low-frequency modes it passes the data straight
4 // through, so that the ARM gets raw A/D samples over the SSP. In the high-
5 // frequency modes, the FPGA might perform some demodulation first, to
6 // reduce the amount of data that we must send to the ARM.
8 // I am not really an FPGA/ASIC designer, so I am sure that a lot of this
11 // Jonathan Westhues, March 2006
12 // Added ISO14443-A support by Gerhard de Koning Gans, April 2008
13 //-----------------------------------------------------------------------------
16 `include "lo_simulate.v"
17 `include "hi_read_tx.v"
18 `include "hi_read_rx_xcorr.v"
19 `include "hi_simulate.v"
20 `include "hi_iso14443a.v"
24 spck, miso, mosi, ncs,
25 pck0i, ck_1356meg, ck_1356megb,
26 pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
27 adc_d, adc_clk, adc_noe,
28 ssp_frame, ssp_din, ssp_dout, ssp_clk,
32 input spck, mosi, ncs;
34 input pck0i, ck_1356meg, ck_1356megb;
35 output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
37 output adc_clk, adc_noe;
39 output ssp_frame, ssp_din, ssp_clk;
40 input cross_hi, cross_lo;
43 IBUFG #(.IOSTANDARD("DEFAULT") ) pck0b(
47 //assign pck0 = pck0i;
48 //-----------------------------------------------------------------------------
49 // The SPI receiver. This sets up the configuration word, which the rest of
50 // the logic looks at to determine how to connect the A/D and the coil
51 // drivers (i.e., which section gets it). Also assign some symbolic names
52 // to the configuration bits, for use below.
53 //-----------------------------------------------------------------------------
55 reg [7:0] conf_word_shift;
58 // We switch modes between transmitting to the 13.56 MHz tag and receiving
59 // from it, which means that we must make sure that we can do so without
60 // glitching, or else we will glitch the transmitted carrier.
63 conf_word <= conf_word_shift;
66 always @(posedge spck)
70 conf_word_shift[7:1] <= conf_word_shift[6:0];
71 conf_word_shift[0] <= mosi;
75 wire [2:0] major_mode;
76 assign major_mode = conf_word[7:5];
78 // For the low-frequency configuration:
80 assign lo_is_125khz = conf_word[3];
82 // For the high-frequency transmit configuration: modulation depth, either
83 // 100% (just quite driving antenna, steady LOW), or shallower (tri-state
84 // some fraction of the buffers)
85 wire hi_read_tx_shallow_modulation;
86 assign hi_read_tx_shallow_modulation = conf_word[0];
88 // For the high-frequency receive correlator: frequency against which to
90 wire hi_read_rx_xcorr_848;
91 assign hi_read_rx_xcorr_848 = conf_word[0];
92 // and whether to drive the coil (reader) or just short it (snooper)
93 wire hi_read_rx_xcorr_snoop;
94 assign hi_read_rx_xcorr_snoop = conf_word[1];
96 // For the high-frequency simulated tag: what kind of modulation to use.
97 wire [2:0] hi_simulate_mod_type;
98 assign hi_simulate_mod_type = conf_word[2:0];
100 //-----------------------------------------------------------------------------
101 // And then we instantiate the modules corresponding to each of the FPGA's
102 // major modes, and use muxes to connect the outputs of the active mode to
104 //-----------------------------------------------------------------------------
107 pck0, ck_1356meg, ck_1356megb,
108 lr_pwr_lo, lr_pwr_hi, lr_pwr_oe1, lr_pwr_oe2, lr_pwr_oe3, lr_pwr_oe4,
110 lr_ssp_frame, lr_ssp_din, ssp_dout, lr_ssp_clk,
117 pck0, ck_1356meg, ck_1356megb,
118 ls_pwr_lo, ls_pwr_hi, ls_pwr_oe1, ls_pwr_oe2, ls_pwr_oe3, ls_pwr_oe4,
120 ls_ssp_frame, ls_ssp_din, ssp_dout, ls_ssp_clk,
126 pck0, ck_1356meg, ck_1356megb,
127 ht_pwr_lo, ht_pwr_hi, ht_pwr_oe1, ht_pwr_oe2, ht_pwr_oe3, ht_pwr_oe4,
129 ht_ssp_frame, ht_ssp_din, ssp_dout, ht_ssp_clk,
132 hi_read_tx_shallow_modulation
135 hi_read_rx_xcorr hrxc(
136 pck0, ck_1356meg, ck_1356megb,
137 hrxc_pwr_lo, hrxc_pwr_hi, hrxc_pwr_oe1, hrxc_pwr_oe2, hrxc_pwr_oe3, hrxc_pwr_oe4,
139 hrxc_ssp_frame, hrxc_ssp_din, ssp_dout, hrxc_ssp_clk,
142 hi_read_rx_xcorr_848, hi_read_rx_xcorr_snoop
146 pck0, ck_1356meg, ck_1356megb,
147 hs_pwr_lo, hs_pwr_hi, hs_pwr_oe1, hs_pwr_oe2, hs_pwr_oe3, hs_pwr_oe4,
149 hs_ssp_frame, hs_ssp_din, ssp_dout, hs_ssp_clk,
156 pck0, ck_1356meg, ck_1356megb,
157 hisn_pwr_lo, hisn_pwr_hi, hisn_pwr_oe1, hisn_pwr_oe2, hisn_pwr_oe3, hisn_pwr_oe4,
159 hisn_ssp_frame, hisn_ssp_din, ssp_dout, hisn_ssp_clk,
166 // 000 -- LF reader (generic)
167 // 001 -- LF simulated tag (generic)
168 // 010 -- HF reader, transmitting to tag; modulation depth selectable
169 // 011 -- HF reader, receiving from tag, correlating as it goes; frequency selectable
170 // 100 -- HF simulated tag
171 // 101 -- HF ISO14443-A
173 // 111 -- everything off
175 mux8 mux_ssp_clk (major_mode, ssp_clk, lr_ssp_clk, ls_ssp_clk, ht_ssp_clk, hrxc_ssp_clk, hs_ssp_clk, hisn_ssp_clk, 1'b0, 1'b0);
176 mux8 mux_ssp_din (major_mode, ssp_din, lr_ssp_din, ls_ssp_din, ht_ssp_din, hrxc_ssp_din, hs_ssp_din, hisn_ssp_din, 1'b0, 1'b0);
177 mux8 mux_ssp_frame (major_mode, ssp_frame, lr_ssp_frame, ls_ssp_frame, ht_ssp_frame, hrxc_ssp_frame, hs_ssp_frame, hisn_ssp_frame, 1'b0, 1'b0);
178 mux8 mux_pwr_oe1 (major_mode, pwr_oe1, lr_pwr_oe1, ls_pwr_oe1, ht_pwr_oe1, hrxc_pwr_oe1, hs_pwr_oe1, hisn_pwr_oe1, 1'b0, 1'b0);
179 mux8 mux_pwr_oe2 (major_mode, pwr_oe2, lr_pwr_oe2, ls_pwr_oe2, ht_pwr_oe2, hrxc_pwr_oe2, hs_pwr_oe2, hisn_pwr_oe2, 1'b0, 1'b0);
180 mux8 mux_pwr_oe3 (major_mode, pwr_oe3, lr_pwr_oe3, ls_pwr_oe3, ht_pwr_oe3, hrxc_pwr_oe3, hs_pwr_oe3, hisn_pwr_oe3, 1'b0, 1'b0);
181 mux8 mux_pwr_oe4 (major_mode, pwr_oe4, lr_pwr_oe4, ls_pwr_oe4, ht_pwr_oe4, hrxc_pwr_oe4, hs_pwr_oe4, hisn_pwr_oe4, 1'b0, 1'b0);
182 mux8 mux_pwr_lo (major_mode, pwr_lo, lr_pwr_lo, ls_pwr_lo, ht_pwr_lo, hrxc_pwr_lo, hs_pwr_lo, hisn_pwr_lo, 1'b0, 1'b0);
183 mux8 mux_pwr_hi (major_mode, pwr_hi, lr_pwr_hi, ls_pwr_hi, ht_pwr_hi, hrxc_pwr_hi, hs_pwr_hi, hisn_pwr_hi, 1'b0, 1'b0);
184 mux8 mux_adc_clk (major_mode, adc_clk, lr_adc_clk, ls_adc_clk, ht_adc_clk, hrxc_adc_clk, hs_adc_clk, hisn_adc_clk, 1'b0, 1'b0);
185 mux8 mux_dbg (major_mode, dbg, lr_dbg, ls_dbg, ht_dbg, hrxc_dbg, hs_dbg, hisn_dbg, 1'b0, 1'b0);
187 // In all modes, let the ADC's outputs be enabled.
188 assign adc_noe = 1'b0;