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1 /*
2 * LEGIC RF simulation code
3 *
4 * (c) 2009 Henryk Plötz <henryk@ploetzli.ch>
5 */
6
7 #include "proxmark3.h"
8 #include "apps.h"
9 #include "util.h"
10
11 #include "legicrf.h"
12 #include "legic_prng.h"
13 #include "crc.h"
14
15 static struct legic_frame {
16 int bits;
17 uint32_t data;
18 } current_frame;
19
20 static crc_t legic_crc;
21
22 AT91PS_TC timer;
23
24 static void setup_timer(void)
25 {
26 /* Set up Timer 1 to use for measuring time between pulses. Since we're bit-banging
27 * this it won't be terribly accurate but should be good enough.
28 */
29 AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
30 timer = AT91C_BASE_TC1;
31 timer->TC_CCR = AT91C_TC_CLKDIS;
32 timer->TC_CMR = TC_CMR_TCCLKS_TIMER_CLOCK3;
33 timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
34
35 /* At TIMER_CLOCK3 (MCK/32) */
36 #define RWD_TIME_1 150 /* RWD_TIME_PAUSE off, 80us on = 100us */
37 #define RWD_TIME_0 90 /* RWD_TIME_PAUSE off, 40us on = 60us */
38 #define RWD_TIME_PAUSE 30 /* 20us */
39 #define RWD_TIME_FUZZ 20 /* rather generous 13us, since the peak detector + hysteresis fuzz quite a bit */
40 #define TAG_TIME_BIT 150 /* 100us for every bit */
41 #define TAG_TIME_WAIT 490 /* time from RWD frame end to tag frame start, experimentally determined */
42
43 }
44
45 #define FUZZ_EQUAL(value, target, fuzz) ((value) > ((target)-(fuzz)) && (value) < ((target)+(fuzz)))
46
47 /* Send a frame in reader mode, the FPGA must have been set up by
48 * LegicRfReader
49 */
50 static void frame_send_rwd(uint32_t data, int bits)
51 {
52 /* Start clock */
53 timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
54 while(timer->TC_CV > 1) ; /* Wait till the clock has reset */
55
56 int i;
57 for(i=0; i<bits; i++) {
58 int starttime = timer->TC_CV;
59 int pause_end = starttime + RWD_TIME_PAUSE, bit_end;
60 int bit = data & 1;
61 data = data >> 1;
62
63 if(bit ^ legic_prng_get_bit()) {
64 bit_end = starttime + RWD_TIME_1;
65 } else {
66 bit_end = starttime + RWD_TIME_0;
67 }
68
69 /* RWD_TIME_PAUSE time off, then some time on, so that the complete bit time is
70 * RWD_TIME_x, where x is the bit to be transmitted */
71 AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT;
72 while(timer->TC_CV < pause_end) ;
73 AT91C_BASE_PIOA->PIO_SODR = GPIO_SSC_DOUT;
74 legic_prng_forward(1); /* bit duration is longest. use this time to forward the lfsr */
75
76 while(timer->TC_CV < bit_end) ;
77 }
78
79 {
80 /* One final pause to mark the end of the frame */
81 int pause_end = timer->TC_CV + RWD_TIME_PAUSE;
82 AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT;
83 while(timer->TC_CV < pause_end) ;
84 AT91C_BASE_PIOA->PIO_SODR = GPIO_SSC_DOUT;
85 }
86
87 /* Reset the timer, to measure time until the start of the tag frame */
88 timer->TC_CCR = AT91C_TC_SWTRG;
89 while(timer->TC_CV > 1) ; /* Wait till the clock has reset */
90 }
91
92 /* Receive a frame from the card in reader emulation mode, the FPGA and
93 * timer must have been set up by LegicRfReader and frame_send_rwd.
94 *
95 * The LEGIC RF protocol from card to reader does not include explicit
96 * frame start/stop information or length information. The reader must
97 * know beforehand how many bits it wants to receive. (Notably: a card
98 * sending a stream of 0-bits is indistinguishable from no card present.)
99 *
100 * Receive methodology: There is a fancy correlator in hi_read_rx_xcorr, but
101 * I'm not smart enough to use it. Instead I have patched hi_read_tx to output
102 * the ADC signal with hysteresis on SSP_DIN. Bit-bang that signal and look
103 * for edges. Count the edges in each bit interval. If they are approximately
104 * 0 this was a 0-bit, if they are approximately equal to the number of edges
105 * expected for a 212kHz subcarrier, this was a 1-bit. For timing we use the
106 * timer that's still running from frame_send_rwd in order to get a synchronization
107 * with the frame that we just sent.
108 *
109 * FIXME: Because we're relying on the hysteresis to just do the right thing
110 * the range is severely reduced (and you'll probably also need a good antenna).
111 * So this should be fixed some time in the future for a proper receiver.
112 */
113 static void frame_receive_rwd(struct legic_frame * const f, int bits, int crypt)
114 {
115 uint32_t the_bit = 1; /* Use a bitmask to save on shifts */
116 uint32_t data=0;
117 int i, old_level=0, edges=0;
118 int next_bit_at = TAG_TIME_WAIT;
119
120
121 if(bits > 16)
122 bits = 16;
123
124 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
125 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
126
127 /* we have some time now, precompute the cipher
128 * since we cannot compute it on the fly while reading */
129 legic_prng_forward(2);
130
131 if(crypt)
132 {
133 for(i=0; i<bits; i++) {
134 data |= legic_prng_get_bit() << i;
135 legic_prng_forward(1);
136 }
137 }
138
139 while(timer->TC_CV < next_bit_at) ;
140
141 next_bit_at += TAG_TIME_BIT;
142
143 for(i=0; i<bits; i++) {
144 edges = 0;
145
146 while(timer->TC_CV < next_bit_at) {
147 int level = (AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
148 if(level != old_level)
149 edges++;
150 old_level = level;
151 }
152 next_bit_at += TAG_TIME_BIT;
153
154 if(edges > 20 && edges < 60) { /* expected are 42 edges */
155 data ^= the_bit;
156 }
157
158 the_bit <<= 1;
159 }
160
161 f->data = data;
162 f->bits = bits;
163
164 /* Reset the timer, to synchronize the next frame */
165 timer->TC_CCR = AT91C_TC_SWTRG;
166 while(timer->TC_CV > 1) ; /* Wait till the clock has reset */
167 }
168
169 static void frame_clean(struct legic_frame * const f)
170 {
171 f->data = 0;
172 f->bits = 0;
173 }
174
175 static uint32_t perform_setup_phase_rwd(int iv)
176 {
177
178 /* Switch on carrier and let the tag charge for 1ms */
179 AT91C_BASE_PIOA->PIO_SODR = GPIO_SSC_DOUT;
180 SpinDelay(1);
181
182 legic_prng_init(0); /* no keystream yet */
183 frame_send_rwd(iv, 7);
184 legic_prng_init(iv);
185
186 frame_clean(&current_frame);
187 frame_receive_rwd(&current_frame, 6, 1);
188 legic_prng_forward(1); /* we wait anyways */
189 while(timer->TC_CV < 387) ; /* ~ 258us */
190 frame_send_rwd(0x19, 6);
191
192 return current_frame.data;
193 }
194
195 static void LegicCommonInit(void) {
196 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
197 FpgaSetupSsc();
198 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX);
199
200 /* Bitbang the transmitter */
201 AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT;
202 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
203 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
204
205 setup_timer();
206
207 crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
208 }
209
210 static void switch_off_tag_rwd(void)
211 {
212 /* Switch off carrier, make sure tag is reset */
213 AT91C_BASE_PIOA->PIO_CODR = GPIO_SSC_DOUT;
214 SpinDelay(10);
215
216 WDT_HIT();
217 }
218 /* calculate crc for a legic command */
219 static int LegicCRC(int byte_index, int value, int cmd_sz) {
220 crc_clear(&legic_crc);
221 crc_update(&legic_crc, 1, 1); /* CMD_READ */
222 crc_update(&legic_crc, byte_index, cmd_sz-1);
223 crc_update(&legic_crc, value, 8);
224 return crc_finish(&legic_crc);
225 }
226
227 int legic_read_byte(int byte_index, int cmd_sz) {
228 int byte;
229
230 legic_prng_forward(4); /* we wait anyways */
231 while(timer->TC_CV < 387) ; /* ~ 258us + 100us*delay */
232
233 frame_send_rwd(1 | (byte_index << 1), cmd_sz);
234 frame_clean(&current_frame);
235
236 frame_receive_rwd(&current_frame, 12, 1);
237
238 byte = current_frame.data & 0xff;
239 if( LegicCRC(byte_index, byte, cmd_sz) != (current_frame.data >> 8) ) {
240 Dbprintf("!!! crc mismatch: expected %x but got %x !!!", LegicCRC(byte_index, current_frame.data & 0xff, cmd_sz), current_frame.data >> 8);
241 return -1;
242 }
243
244 return byte;
245 }
246
247 /* legic_write_byte() is not included, however it's trivial to implement
248 * and here are some hints on what remains to be done:
249 *
250 * * assemble a write_cmd_frame with crc and send it
251 * * wait until the tag sends back an ACK ('1' bit unencrypted)
252 * * forward the prng based on the timing
253 */
254
255
256 void LegicRfReader(int offset, int bytes) {
257 int byte_index=0, cmd_sz=0, card_sz=0;
258
259 LegicCommonInit();
260
261 memset(BigBuf, 0, 1024);
262
263 DbpString("setting up legic card");
264 uint32_t tag_type = perform_setup_phase_rwd(0x55);
265 switch(tag_type) {
266 case 0x1d:
267 DbpString("MIM 256 card found, reading card ...");
268 cmd_sz = 9;
269 card_sz = 256;
270 break;
271 case 0x3d:
272 DbpString("MIM 1024 card found, reading card ...");
273 cmd_sz = 11;
274 card_sz = 1024;
275 break;
276 default:
277 Dbprintf("Unknown card format: %x",tag_type);
278 switch_off_tag_rwd();
279 return;
280 }
281 if(bytes == -1) {
282 bytes = card_sz;
283 }
284 if(bytes+offset >= card_sz) {
285 bytes = card_sz-offset;
286 }
287
288 switch_off_tag_rwd(); //we lost to mutch time with dprintf
289 perform_setup_phase_rwd(0x55);
290
291 while(byte_index < bytes) {
292 int r = legic_read_byte(byte_index+offset, cmd_sz);
293 if(r == -1) {
294 Dbprintf("aborting");
295 switch_off_tag_rwd();
296 return;
297 }
298 ((uint8_t*)BigBuf)[byte_index] = r;
299 byte_index++;
300 }
301 switch_off_tag_rwd();
302 Dbprintf("Card read, use 'hf legic decode' or 'data hexsamples %d' to view results", (bytes+7) & ~7);
303 }
304
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