cvs.zerfleddert.de Git - proxmark3-svn/blob - fpga/lo_read.v

   1 //-----------------------------------------------------------------------------
   2 // The way that we connect things in low-frequency read mode. In this case
   3 // we are generating the unmodulated low frequency carrier.
   4 // The A/D samples at that same rate and the result is serialized.
   5 //
   6 // Jonathan Westhues, April 2006
   7 //-----------------------------------------------------------------------------
   8
   9 module lo_read(
  10         input pck0, input [7:0] pck_cnt, input pck_divclk,
  11         output pwr_lo, output pwr_hi,
  12         output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
  13         input [7:0] adc_d, output adc_clk,
  14         output ssp_frame, output ssp_din, output ssp_clk,
  15         output dbg
  16 );
  17
  18 reg [7:0] to_arm_shiftreg;
  19
  20 // this task also runs at pck0 frequency (24Mhz) and is used to serialize
  21 // the ADC output which is then clocked into the ARM SSP.
  22
  23 // because pck_divclk always transitions when pck_cnt = 0 we use the
  24 // pck_div counter to sync our other signals off it
  25 // we read the ADC value when pck_cnt=7 and shift it out on counts 8..15
  26 always @(posedge pck0)
  27 begin
  28         if((pck_cnt == 8'd7) && !pck_divclk)
  29                 to_arm_shiftreg <= adc_d;
  30         else begin
  31                 to_arm_shiftreg[7:1] <= to_arm_shiftreg[6:0];
  32                 // simulation showed a glitch occuring due to the LSB of the shifter
  33                 // not being set as we shift bits out
  34                 // this ensures the ssp_din remains low after a transfer and suppresses
  35                 // the glitch that would occur when the last data shifted out ended in
  36                 // a 1 bit and the next data shifted out started with a 0 bit
  37                 to_arm_shiftreg[0] <= 1'b0;
  38         end
  39 end
  40
  41 // ADC samples on falling edge of adc_clk, data available on the rising edge
  42
  43 // example of ssp transfer of binary value 1100101
  44 // start of transfer is indicated by the rise of the ssp_frame signal
  45 // ssp_din changes on the rising edge of the ssp_clk clock and is clocked into
  46 // the ARM by the falling edge of ssp_clk
  47 //             _______________________________
  48 // ssp_frame__|                               |__
  49 //             _______         ___     ___
  50 // ssp_din  __|       |_______|   |___|   |______
  51 //         _   _   _   _   _   _   _   _   _   _
  52 // ssp_clk  |_| |_| |_| |_| |_| |_| |_| |_| |_| |_
  53
  54 // serialized SSP data is gated by ant_lo to suppress unwanted signal
  55 assign ssp_din = to_arm_shiftreg[7] && !pck_divclk;
  56 // SSP clock always runs at 24Mhz
  57 assign ssp_clk = pck0;
  58 // SSP frame is gated by ant_lo and goes high when pck_divider=8..15
  59 assign ssp_frame = (pck_cnt[7:3] == 5'd1) && !pck_divclk;
  60 // unused signals tied low
  61 assign pwr_hi = 1'b0;
  62 assign pwr_oe1 = 1'b0;
  63 assign pwr_oe2 = 1'b0;
  64 assign pwr_oe3 = 1'b0;
  65 assign pwr_oe4 = 1'b0;
  66 // this is the antenna driver signal
  67 assign pwr_lo = pck_divclk;
  68 // ADC clock out of phase with antenna driver
  69 assign adc_clk = ~pck_divclk;
  70 // ADC clock also routed to debug pin
  71 assign dbg = adc_clk;
  72 endmodule