#define TR1 0
// Frame Delay Time PICC to PCD (per 14443-3 Amendment 1)
#define TR2 0
+
+// 4sample
+//#define SEND4STUFFBIT(x) ToSendStuffBit(x);ToSendStuffBit(x);ToSendStuffBit(x);ToSendStuffBit(x);
+#define SEND4STUFFBIT(x) ToSendStuffBit(x);
+
static void switch_off(void);
// the block number for the ISO14443-4 PCB (used with APDUs)
// Send SOF.
// 10-11 ETU * 4times samples ZEROS
- for(i = 0; i < 10; i++) {
- ToSendStuffBit(0);
- ToSendStuffBit(0);
- ToSendStuffBit(0);
- ToSendStuffBit(0);
- }
+ for(i = 0; i < 10; i++) { SEND4STUFFBIT(0); }
// 2-3 ETU * 4times samples ONES
- for(i = 0; i < 3; i++) {
- ToSendStuffBit(1);
- ToSendStuffBit(1);
- ToSendStuffBit(1);
- ToSendStuffBit(1);
- }
+ for(i = 0; i < 3; i++) { SEND4STUFFBIT(1); }
// data
for(i = 0; i < len; ++i) {
// Start bit
- ToSendStuffBit(0);
- ToSendStuffBit(0);
- ToSendStuffBit(0);
- ToSendStuffBit(0);
+ SEND4STUFFBIT(0);
// Data bits
b = cmd[i];
for(j = 0; j < 8; ++j) {
- if(b & 1) {
- ToSendStuffBit(1);
- ToSendStuffBit(1);
- ToSendStuffBit(1);
- ToSendStuffBit(1);
+ if(b & 1) {
+ SEND4STUFFBIT(1);
} else {
- ToSendStuffBit(0);
- ToSendStuffBit(0);
- ToSendStuffBit(0);
- ToSendStuffBit(0);
+ SEND4STUFFBIT(0);
}
b >>= 1;
}
// Stop bit
- ToSendStuffBit(1);
- ToSendStuffBit(1);
- ToSendStuffBit(1);
- ToSendStuffBit(1);
+ SEND4STUFFBIT(1);
// Extra Guard bit
// For PICC it ranges 0-18us (1etu = 9us)
- ToSendStuffBit(1);
- ToSendStuffBit(1);
- ToSendStuffBit(1);
- ToSendStuffBit(1);
+ SEND4STUFFBIT(1);
}
// Send EOF.
// 10-11 ETU * 4 sample rate = ZEROS
- for(i = 0; i < 10; i++) {
- ToSendStuffBit(0);
- ToSendStuffBit(0);
- ToSendStuffBit(0);
- ToSendStuffBit(0);
- }
+ for(i = 0; i < 10; i++) { SEND4STUFFBIT(0); }
// why this?
- for(i = 0; i < 40; i++) {
- ToSendStuffBit(1);
- ToSendStuffBit(1);
- ToSendStuffBit(1);
- ToSendStuffBit(1);
- }
+ for(i = 0; i < 40; i++) { SEND4STUFFBIT(1); }
// Convert from last byte pos to length
++ToSendMax;
// Signal field is off with the appropriate LED
LED_D_OFF();
FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_NO_MODULATION);
-
+
StartCountSspClk();
+ volatile uint8_t b;
+
+ // clear receiving shift register and holding register
+ // What does this loop do? Is it TR1?
+ for(uint8_t c = 0; c < 10;) {
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
+ AT91C_BASE_SSC->SSC_THR = 0xFF;
+ ++c;
+ }
+ }
+
// Now run a `software UART' on the stream of incoming samples.
UartInit(received);
-
- uint8_t mask, b = 0;
+
+ b = 0;
+ uint8_t mask;
while( !BUTTON_PRESS() ) {
WDT_HIT();
return FALSE;
}
+void ClearFpgaShiftingRegisters(void){
+
+ volatile uint8_t b;
+
+ // clear receiving shift register and holding register
+ while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
+ b = AT91C_BASE_SSC->SSC_RHR; (void) b;
+
+ while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
+ b = AT91C_BASE_SSC->SSC_RHR; (void) b;
+
+
+ // wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
+ for (uint8_t j = 0; j < 5; j++) { // allow timeout - better late than never
+ while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
+ if (AT91C_BASE_SSC->SSC_RHR) break;
+ }
+
+ // Clear TXRDY:
+ AT91C_BASE_SSC->SSC_THR = 0xFF;
+}
+
+void WaitForFpgaDelayQueueIsEmpty( uint16_t delay ){
+ // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN again:
+ uint8_t fpga_queued_bits = delay >> 3; // twich /8 ?? >>3,
+ for (uint8_t i = 0; i <= fpga_queued_bits/8 + 1; ) {
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
+ AT91C_BASE_SSC->SSC_THR = 0xFF;
+ i++;
+ }
+ }
+}
static void TransmitFor14443b_AsTag( uint8_t *response, uint16_t len) {
// Signal field is off with the appropriate LED
LED_D_OFF();
+ uint16_t fpgasendQueueDelay = 0;
// Modulate BPSK
FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_BPSK);
- // 8 ETU / 8bits. 8/4= 2 etus.
- AT91C_BASE_SSC->SSC_THR = 0XFF;
-
+ ClearFpgaShiftingRegisters();
+
FpgaSetupSsc();
// Transmit the response.
for(uint16_t i = 0; i < len;) {
if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
- AT91C_BASE_SSC->SSC_THR = response[i];
- ++i;
+ AT91C_BASE_SSC->SSC_THR = response[++i];
+ fpgasendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
}
}
+
+ WaitForFpgaDelayQueueIsEmpty(fpgasendQueueDelay);
}
//-----------------------------------------------------------------------------
// Main loop of simulated tag: receive commands from reader, decide what
// REQ or WUP request in ANY state
// WUP in HALTED state
if (len == 5 ) {
- if ( (receivedCmd[0] == ISO14443B_REQB && (receivedCmd[2] & 0x8)== 0x8 && cardSTATE != SIM_HALTED) ||
- (receivedCmd[0] == ISO14443B_REQB && (receivedCmd[2] & 0x8)== 0) ){
-
- TransmitFor14443b_AsTag( encodedATQB, encodedATQBLen );
- LogTrace(respATQB, sizeof(respATQB), 0, 0, NULL, FALSE);
+ if ( (receivedCmd[0] == ISO14443B_REQB && (receivedCmd[2] & 0x8)== 0x8 && cardSTATE == SIM_HALTED) ||
+ receivedCmd[0] == ISO14443B_REQB ){
+ LogTrace(receivedCmd, len, 0, 0, NULL, TRUE);
cardSTATE = SIM_SELECTING;
- continue;
}
}
* HALT
send halt response ( waiting for wupb )
*/
-
- if ( len == 7 && receivedCmd[0] == ISO14443B_HALT ) {
- cardSTATE = SIM_HALTED;
- } else if ( len == 11 && receivedCmd[0] == ISO14443B_ATTRIB ) {
- cardSTATE = SIM_ACKNOWLEDGE;
- } else {
- // Todo:
- // - SLOT MARKER
- // - ISO7816
- // - emulate with a memory dump
- Dbprintf("new cmd from reader: len=%d, cmdsRecvd=%d", len, cmdsReceived);
-
- // CRC Check
- uint8_t b1, b2;
- if (len >= 3){ // if crc exists
- ComputeCrc14443(CRC_14443_B, receivedCmd, len-2, &b1, &b2);
- if(b1 != receivedCmd[len-2] || b2 != receivedCmd[len-1])
- DbpString("+++CRC fail");
- else
- DbpString("CRC passes");
- }
- cardSTATE = SIM_IDLE;
- }
-
+
switch(cardSTATE){
case SIM_NOFIELD:
case SIM_HALTED:
case SIM_SELECTING: {
TransmitFor14443b_AsTag( encodedATQB, encodedATQBLen );
LogTrace(respATQB, sizeof(respATQB), 0, 0, NULL, FALSE);
- cardSTATE = SIM_IDLE;
+ cardSTATE = SIM_WORK;
break;
}
case SIM_HALTING: {
cardSTATE = SIM_IDLE;
break;
}
- default:
+ case SIM_WORK:{
+ if ( len == 7 && receivedCmd[0] == ISO14443B_HALT ) {
+ cardSTATE = SIM_HALTED;
+ } else if ( len == 11 && receivedCmd[0] == ISO14443B_ATTRIB ) {
+ cardSTATE = SIM_ACKNOWLEDGE;
+ } else {
+ // Todo:
+ // - SLOT MARKER
+ // - ISO7816
+ // - emulate with a memory dump
+ Dbprintf("new cmd from reader: len=%d, cmdsRecvd=%d", len, cmdsReceived);
+
+ // CRC Check
+ uint8_t b1, b2;
+ if (len >= 3){ // if crc exists
+ ComputeCrc14443(CRC_14443_B, receivedCmd, len-2, &b1, &b2);
+ if(b1 != receivedCmd[len-2] || b2 != receivedCmd[len-1])
+ DbpString("+++CRC fail");
+ else
+ DbpString("CRC passes");
+ }
+ cardSTATE = SIM_IDLE;
+ }
break;
+ }
+ default: break;
}
++cmdsReceived;
projects / proxmark3-svn / blobdiff