Added a utility which takes a mifare-dumpfile and creates a html-report visualising...

[proxmark3-svn] / armsrc / util.c

diff --git a/armsrc/util.c b/armsrc/util.c
index 0172754e283a950b47606103719d7a6d8478e261..dc18e5e385247ac727a259c6095bd8e008c0b60f 100644 (file)
--- a/armsrc/util.c
+++ b/armsrc/util.c
@@ -11,6 +11,20 @@
 #include "proxmark3.h"
 #include "util.h"
 #include "string.h"
 #include "proxmark3.h"
 #include "util.h"
 #include "string.h"

+#include "apps.h"
+
+size_t nbytes(size_t nbits) {
+       return (nbits/8)+((nbits%8)>0);
+}
+
+uint32_t SwapBits(uint32_t value, int nrbits) {
+       int i;
+       uint32_t newvalue = 0;
+       for(i = 0; i < nrbits; i++) {
+               newvalue ^= ((value >> i) & 1) << (nrbits - 1 - i);
+       }
+       return newvalue;
+}

 
 void num_to_bytes(uint64_t n, size_t len, uint8_t* dest)
 {
 
 void num_to_bytes(uint64_t n, size_t len, uint8_t* dest)
 {


@@ -259,6 +273,110 @@ void StartTickCount()
 * Get the current count.
 */
 uint32_t RAMFUNC GetTickCount(){
 * Get the current count.
 */
 uint32_t RAMFUNC GetTickCount(){

-       return AT91C_BASE_RTTC->RTTC_RTVR;// * 2;
+       return AT91C_BASE_RTTC->RTTC_RTVR;// was * 2;
+}
+
+//  -------------------------------------------------------------------------
+//  microseconds timer 
+//  -------------------------------------------------------------------------
+void StartCountUS()
+{
+       AT91C_BASE_PMC->PMC_PCER |= (0x1 << 12) | (0x1 << 13) | (0x1 << 14);
+//     AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC1XC1S_TIOA0;
+       AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
+
+       // fast clock
+       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable
+       AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz)/32 -- tick=1.5mks
+                                                                                                               AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR |
+                                                                                                               AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;
+       AT91C_BASE_TC0->TC_RA = 1;
+       AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000
+       
+       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // timer disable  
+       AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // from timer 0
+       
+       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;
+       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;
+       AT91C_BASE_TCB->TCB_BCR = 1;
+       }
+
+uint32_t RAMFUNC GetCountUS(){
+       return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV / 15) * 10);

 }
 
 }
 

+static uint32_t GlobalUsCounter = 0;
+
+uint32_t RAMFUNC GetDeltaCountUS(){
+       uint32_t g_cnt = GetCountUS();
+       uint32_t g_res = g_cnt - GlobalUsCounter;
+       GlobalUsCounter = g_cnt;
+       return g_res;
+}
+
+
+//  -------------------------------------------------------------------------
+//  Mifare timer. Uses ssp_clk from FPGA 
+//  -------------------------------------------------------------------------
+void StartCountMifare()
+{
+       AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0) | (1 << AT91C_ID_TC1) | (1 << AT91C_ID_TC2);  // Enable Clock to all timers
+       AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_TIOA1               // XC0 Clock = TIOA1
+                                                       | AT91C_TCB_TC1XC1S_NONE                // XC1 Clock = none
+                                                       | AT91C_TCB_TC2XC2S_TIOA0;              // XC2 Clock = TIOA0
+
+       // configure TC1 to create a short pulse on TIOA1 when a rising edge on TIOB1 (= ssp_clk from FPGA) occurs:
+       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;                               // disable TC1
+       AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK // TC1 Clock = MCK(48MHz)/2 = 24MHz
+                                                       | AT91C_TC_CPCSTOP                              // Stop clock on RC compare
+                                                       | AT91C_TC_EEVTEDG_RISING               // Trigger on rising edge of Event
+                                                       | AT91C_TC_EEVT_TIOB                    // Event-Source: TIOB1 (= ssc_clk from FPGA = 13,56MHz / 16)
+                                                       | AT91C_TC_ENETRG                               // Enable external trigger event
+                                                       | AT91C_TC_WAVESEL_UP                   // Upmode without automatic trigger on RC compare
+                                                       | AT91C_TC_WAVE                                 // Waveform Mode
+                                                       | AT91C_TC_AEEVT_SET                    // Set TIOA1 on external event
+                                                       | AT91C_TC_ACPC_CLEAR;                  // Clear TIOA1 on RC Compare
+       AT91C_BASE_TC1->TC_RC = 0x04;                                                   // RC Compare value = 0x04
+
+       // use TC0 to count TIOA1 pulses
+       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;                               // disable TC0  
+       AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_XC0                              // TC0 clock = XC0 clock = TIOA1
+                                                       | AT91C_TC_WAVE                                 // Waveform Mode
+                                                       | AT91C_TC_WAVESEL_UP                   // just count
+                                                       | AT91C_TC_ACPA_CLEAR                   // Clear TIOA0 on RA Compare
+                                                       | AT91C_TC_ACPC_SET;                    // Set TIOA0 on RC Compare
+       AT91C_BASE_TC0->TC_RA = 1;                                                              // RA Compare value = 1; pulse width to TC2
+       AT91C_BASE_TC0->TC_RC = 0;                                                              // RC Compare value = 0; increment TC2 on overflow
+
+       // use TC2 to count TIOA0 pulses (giving us a 32bit counter (TC0/TC2) clocked by ssp_clk)
+       AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKDIS;                               // disable TC2  
+       AT91C_BASE_TC2->TC_CMR = AT91C_TC_CLKS_XC2                              // TC2 clock = XC2 clock = TIOA0
+                                                       | AT91C_TC_WAVE                                 // Waveform Mode
+                                                       | AT91C_TC_WAVESEL_UP;                  // just count
+       
+       
+       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;                                // enable TC0
+       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;                                // enable TC1
+       AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN;                                // enable TC2
+
+       // activate the ISO14443 part of the FPGA. We need the clock and frame signals.
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
+
+       // synchronize the counter with the ssp_frame signal.
+       while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME);              // wait for ssp_frame to be low
+       while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME));   // sync on rising edge of ssp_frame (= start of transfer)
+
+       AT91C_BASE_TCB->TCB_BCR = 1;                                                    // assert Sync (set all timers to 0 on next active clock edge)
+}
+
+
+uint32_t RAMFUNC GetCountMifare(){
+       uint32_t tmp_count;
+       tmp_count = (AT91C_BASE_TC2->TC_CV << 16) | AT91C_BASE_TC0->TC_CV;
+       if ((tmp_count & 0xffff) == 0) { //small chance that we may have missed an increment in TC2
+               return (AT91C_BASE_TC2->TC_CV << 16);
+       } 
+       else {
+               return tmp_count;
+       }
+}