CHG: adjusted two arrays in scripting.c to mirror the added models in reveng 1.4.0

[proxmark3-svn] / armsrc / util.c

diff --git a/armsrc/util.c b/armsrc/util.c
index 3d536f396d6205c5d450a88f3cbed62030049b1b..4e74b88dd2eeaa20470c8e3b60c7150bdb188f5c 100644 (file)
--- a/armsrc/util.c
+++ b/armsrc/util.c
@@ -39,9 +39,8 @@ size_t nbytes(size_t nbits) {
 }
 
 uint32_t SwapBits(uint32_t value, int nrbits) {
 }
 
 uint32_t SwapBits(uint32_t value, int nrbits) {

-       int i;

        uint32_t newvalue = 0;
        uint32_t newvalue = 0;

-       for(i = 0; i < nrbits; i++) {
+       for(int i = 0; i < nrbits; i++) {

                newvalue ^= ((value >> i) & 1) << (nrbits - 1 - i);
        }
        return newvalue;
                newvalue ^= ((value >> i) & 1) << (nrbits - 1 - i);
        }
        return newvalue;


@@ -74,6 +73,7 @@ void rol(uint8_t *data, const size_t len){
     }
     data[len-1] = first;
 }
     }
     data[len-1] = first;
 }

+

 void lsl (uint8_t *data, size_t len) {
     for (size_t n = 0; n < len - 1; n++) {
         data[n] = (data[n] << 1) | (data[n+1] >> 7);
 void lsl (uint8_t *data, size_t len) {
     for (size_t n = 0; n < len - 1; n++) {
         data[n] = (data[n] << 1) | (data[n+1] >> 7);


@@ -331,8 +331,8 @@ void StartCountUS()
        // fast clock
        AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable
        AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz)/32 -- tick=1.5mks
        // fast clock
        AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable
        AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz)/32 -- tick=1.5mks

-                                                                                                               AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR |
-                                                                                                               AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;
+                                                               AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR |
+                                                               AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;

        AT91C_BASE_TC0->TC_RA = 1;
        AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000
        
        AT91C_BASE_TC0->TC_RA = 1;
        AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000
        


@@ -421,15 +421,10 @@ void StartCountSspClk()
        while (AT91C_BASE_TC0->TC_CV < 0xFFF0);
 }
 
        while (AT91C_BASE_TC0->TC_CV < 0xFFF0);
 }
 

-

 uint32_t RAMFUNC GetCountSspClk(){
 uint32_t RAMFUNC GetCountSspClk(){

-       uint32_t tmp_count;
-       tmp_count = (AT91C_BASE_TC2->TC_CV << 16) | AT91C_BASE_TC0->TC_CV;
-       if ((tmp_count & 0x0000ffff) == 0) { //small chance that we may have missed an increment in TC2
+       uint32_t tmp_count = (AT91C_BASE_TC2->TC_CV << 16) | AT91C_BASE_TC0->TC_CV;
+       if ((tmp_count & 0x0000ffff) == 0)  //small chance that we may have missed an increment in TC2

                return (AT91C_BASE_TC2->TC_CV << 16);
                return (AT91C_BASE_TC2->TC_CV << 16);

-       } 
-       else {
-               return tmp_count;
-       }
+       return tmp_count;

 }
 
 }