CHG: @Marshmellow42 's fixes. ref: https://github.com/marshmellow42/proxmark3/commi...

[proxmark3-svn] / fpga / hi_simulate.v

diff --git a/fpga/hi_simulate.v b/fpga/hi_simulate.v
index c04ade80b098a474218fa8693c537ebe17729a14..6139cfad2c44689d81526649583acaffc9985021 100644 (file)
--- a/fpga/hi_simulate.v
+++ b/fpga/hi_simulate.v
@@ -50,18 +50,49 @@ begin
     else if(~(| adc_d[7:5])) after_hysteresis = 1'b0;
 end
 
+
 // Divide 13.56 MHz by 32 to produce the SSP_CLK
 // The register is bigger to allow higher division factors of up to /128
-reg [6:0] ssp_clk_divider;
+// FPGA_HF_SIMULATOR_NO_MODULATION             (0<<0) // 0000
+// FPGA_HF_SIMULATOR_MODULATE_BPSK             (1<<0) // 0001
+// FPGA_HF_SIMULATOR_MODULATE_212K             (2<<0) // 0010
+// FPGA_HF_SIMULATOR_MODULATE_424K             (4<<0) // 0100
+// FPGA_HF_SIMULATOR_MODULATE_424K_8BIT        0x5    // 0101
+reg [10:0] ssp_clk_divider;
+
 always @(posedge adc_clk)
     ssp_clk_divider <= (ssp_clk_divider + 1);
-assign ssp_clk = ssp_clk_divider[4];
+
+reg ssp_clk;
+reg ssp_frame;
+always @(negedge adc_clk)
+begin
+    //If we're in 101, we only need a new bit every 8th carrier bit (53Hz). Otherwise, get next bit at 424Khz
+    if(mod_type == 3'b101)
+    begin
+       if(ssp_clk_divider[7:0] == 8'b00000000)
+           ssp_clk <= 1'b0;
+       if(ssp_clk_divider[7:0] == 8'b10000000)
+           ssp_clk <= 1'b1;
+
+    end
+    else
+    begin
+       if(ssp_clk_divider[4:0] == 5'd0)//[4:0] == 5'b00000)
+           ssp_clk <= 1'b1;
+       if(ssp_clk_divider[4:0] == 5'd16) //[4:0] == 5'b10000)
+           ssp_clk <= 1'b0;
+    end
+end
+
+
+//assign ssp_clk = ssp_clk_divider[4];
 
 // Divide SSP_CLK by 8 to produce the byte framing signal; the phase of
 // this is arbitrary, because it's just a bitstream.
 // One nasty issue, though: I can't make it work with both rx and tx at
-// once. The phase wrt ssp_clk must be changed. TODO to find out why
-// that is and make a better fix.
+// once. The phase wrt ssp_clk must be changed. 
+// TODO to find out why that is and make a better fix.
 reg [2:0] ssp_frame_divider_to_arm;
 always @(posedge ssp_clk)
     ssp_frame_divider_to_arm <= (ssp_frame_divider_to_arm + 1);
@@ -69,12 +100,13 @@ reg [2:0] ssp_frame_divider_from_arm;
 always @(negedge ssp_clk)
     ssp_frame_divider_from_arm <= (ssp_frame_divider_from_arm + 1);
 
-reg ssp_frame;
+
+
 always @(ssp_frame_divider_to_arm or ssp_frame_divider_from_arm or mod_type)
     if(mod_type == 3'b000) // not modulating, so listening, to ARM
         ssp_frame = (ssp_frame_divider_to_arm == 3'b000);
     else
-        ssp_frame = (ssp_frame_divider_from_arm == 3'b000);
+       ssp_frame = (ssp_frame_divider_from_arm == 3'b000);
 
 // Synchronize up the after-hysteresis signal, to produce DIN.
 reg ssp_din;
@@ -90,7 +122,7 @@ always @(mod_type or ssp_clk or ssp_dout)
         modulating_carrier <= ssp_dout ^ ssp_clk_divider[3]; // XOR means BPSK
     else if(mod_type == 3'b010)
        modulating_carrier <= ssp_dout & ssp_clk_divider[5]; // switch 212kHz subcarrier on/off
-    else if(mod_type == 3'b100)
+    else if(mod_type == 3'b100 || mod_type == 3'b101)
        modulating_carrier <= ssp_dout & ssp_clk_divider[4]; // switch 424kHz modulation on/off
     else
         modulating_carrier <= 1'b0;                           // yet unused
@@ -106,7 +138,7 @@ assign pwr_oe4 = modulating_carrier;
 // This one is always on, so that we can watch the carrier.
 assign pwr_oe3 = 1'b0;
 
-assign dbg = after_hysteresis;
+assign dbg = modulating_carrier;
 //reg dbg;
 //always @(ssp_dout)
 //    dbg <= ssp_dout;