CHG: temporary disable hitag2_uid detection. Loop times out sometimes.

[proxmark3-svn] / armsrc / lfops.c

diff --git a/armsrc/lfops.c b/armsrc/lfops.c
index 1b922ca006d28725fafa4506a001eb0786d3d6c1..0dc5bcf9cee1f95e34ece58662971fbca7b02942 100644 (file)
--- a/armsrc/lfops.c
+++ b/armsrc/lfops.c
@@ -78,6 +78,8 @@ void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t periods, uint3
 
        // now do the read
        DoAcquisition_config(false);
+       
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 }
 
 /* blank r/w tag data stream
@@ -1369,7 +1371,7 @@ void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT) {
                data[4] = manchesterEncode2Bytes(hi & 0xFFFF);
                data[5] = manchesterEncode2Bytes(lo >> 16);
                data[6] = manchesterEncode2Bytes(lo & 0xFFFF);
-       }       else {
+       } else {
                // Ensure no more than 44 bits supplied
                if (hi > 0xFFF) {
                        DbpString("Tags can only have 44 bits.");
@@ -1389,13 +1391,8 @@ void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT) {
        // data[0] = (((50-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | last_block << T5555_MAXBLOCK_SHIFT;
 
        LED_D_ON();
-       // Program the data blocks for supplied ID
-       // and the block 0 for HID format
        WriteT55xx(data, 0, last_block+1);
-
        LED_D_OFF();
-
-       DbpString("DONE!");
 }
 
 void CopyIOtoT55x7(uint32_t hi, uint32_t lo) {
@@ -1409,7 +1406,6 @@ void CopyIOtoT55x7(uint32_t hi, uint32_t lo) {
        // and the block 0 config
        WriteT55xx(data, 0, 3);
        LED_D_OFF();
-       DbpString("DONE!");
 }
 
 // Clone Indala 64-bit tag by UID to T55x7
@@ -1423,7 +1419,6 @@ void CopyIndala64toT55x7(uint32_t hi, uint32_t lo) {
        WriteT55xx(data, 0, 3);
        //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
        //      T5567WriteBlock(0x603E1042,0);
-       DbpString("DONE!");
 }
 // Clone Indala 224-bit tag by UID to T55x7
 void CopyIndala224toT55x7(uint32_t uid1, uint32_t uid2, uint32_t uid3, uint32_t uid4, uint32_t uid5, uint32_t uid6, uint32_t uid7) {
@@ -1437,7 +1432,6 @@ void CopyIndala224toT55x7(uint32_t uid1, uint32_t uid2, uint32_t uid3, uint32_t
        WriteT55xx(data, 0, 8);
        //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
        //      T5567WriteBlock(0x603E10E2,0);
-       DbpString("DONE!");
 }
 // clone viking tag to T55xx
 void CopyVikingtoT55xx(uint32_t block1, uint32_t block2, uint8_t Q5) {
@@ -1745,3 +1739,54 @@ void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
        LED_D_OFF();
 }
+
+void Cotag() {
+
+//#define WAIT2200     { FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); WaitUS(2035); }
+#define WAIT2200       { FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); WaitUS(2200); }
+       LED_A_ON();
+       
+       //clear buffer now so it does not interfere with timing later
+       BigBuf_Clear_ext(false);
+
+       // Set up FPGA, 132kHz to power up the tag
+       FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
+       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 89);
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
+
+       // Connect the A/D to the peak-detected low-frequency path.
+       SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
+       
+       // Now set up the SSC to get the ADC samples that are now streaming at us.
+       FpgaSetupSsc();
+
+       // start a 1.5ticks is 1us
+       StartTicks();
+       
+       //send start pulse
+       TurnReadLFOn(800);      WAIT2200
+       TurnReadLFOn(3600);     WAIT2200
+       TurnReadLFOn(800);      WAIT2200
+       TurnReadLFOn(3600);     
+       
+/*
+       TurnReadLFOn(740);      WAIT2200
+       TurnReadLFOn(3330);     WAIT2200
+       TurnReadLFOn(740);      WAIT2200
+       TurnReadLFOn(3330);     
+       
+
+burst 800 us,    gap   2.2 msecs
+burst 3.6 msecs  gap   2.2 msecs
+burst 800 us     gap   2.2 msecs
+pulse 3.6 msecs
+*/
+       
+       // Acquisition
+       DoAcquisition_default(-1, true);
+       
+       // Turn the field off
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
+       cmd_send(CMD_ACK,0,0,0,0,0);    
+       LED_A_OFF();
+}