fixup code

[proxmark3-svn] / armsrc / fpgaloader.h

diff --git a/armsrc/fpgaloader.h b/armsrc/fpgaloader.h
index 35f7e37c694e74c6571ea2a77a829234af5c1766..49290dc070dd98aae5f57114721f05f9595dc535 100644 (file)
--- a/armsrc/fpgaloader.h
+++ b/armsrc/fpgaloader.h
@@ -14,6 +14,7 @@ void FpgaSendCommand(uint16_t cmd, uint16_t v);
 void FpgaWriteConfWord(uint8_t v);
 void FpgaDownloadAndGo(int bitstream_version);
 void FpgaGatherVersion(int bitstream_version, char *dst, int len);
 void FpgaWriteConfWord(uint8_t v);
 void FpgaDownloadAndGo(int bitstream_version);
 void FpgaGatherVersion(int bitstream_version, char *dst, int len);

+void FpgaSetupSscExt(uint8_t clearPCER);

 void FpgaSetupSsc(void);
 void SetupSpi(int mode);
 bool FpgaSetupSscDma(uint8_t *buf, int len);
 void FpgaSetupSsc(void);
 void SetupSpi(int mode);
 bool FpgaSetupSscDma(uint8_t *buf, int len);


@@ -28,7 +29,6 @@ void SetAdcMuxFor(uint32_t whichGpio);
 #define FPGA_BITSTREAM_LF 1
 #define FPGA_BITSTREAM_HF 2
 
 #define FPGA_BITSTREAM_LF 1
 #define FPGA_BITSTREAM_HF 2
 

-

 // Definitions for the FPGA commands.
 #define FPGA_CMD_SET_CONFREG                                           (1<<12)
 #define FPGA_CMD_SET_DIVISOR                                           (2<<12)
 // Definitions for the FPGA commands.
 #define FPGA_CMD_SET_CONFREG                                           (1<<12)
 #define FPGA_CMD_SET_DIVISOR                                           (2<<12)


@@ -59,11 +59,12 @@ void SetAdcMuxFor(uint32_t whichGpio);
 #define FPGA_HF_READER_RX_XCORR_SNOOP                          (1<<1)
 #define FPGA_HF_READER_RX_XCORR_QUARTER_FREQ           (1<<2)
 // Options for the HF simulated tag, how to modulate
 #define FPGA_HF_READER_RX_XCORR_SNOOP                          (1<<1)
 #define FPGA_HF_READER_RX_XCORR_QUARTER_FREQ           (1<<2)
 // Options for the HF simulated tag, how to modulate

-#define FPGA_HF_SIMULATOR_NO_MODULATION                                (0<<0)
-#define FPGA_HF_SIMULATOR_MODULATE_BPSK                                (1<<0)
-#define FPGA_HF_SIMULATOR_MODULATE_212K                                (2<<0)
-#define FPGA_HF_SIMULATOR_MODULATE_424K                                (4<<0)
-#define FPGA_HF_SIMULATOR_MODULATE_424K_8BIT           0x5//101
+#define FPGA_HF_SIMULATOR_NO_MODULATION                                (0<<0) // 0000
+#define FPGA_HF_SIMULATOR_MODULATE_BPSK                                (1<<0) // 0001
+#define FPGA_HF_SIMULATOR_MODULATE_212K                                (2<<0) // 0010
+#define FPGA_HF_SIMULATOR_MODULATE_424K                                (4<<0) // 0100
+#define FPGA_HF_SIMULATOR_MODULATE_424K_8BIT           0x5    // 0101
+//  no 848K 

 
 // Options for ISO14443A
 #define FPGA_HF_ISO14443A_SNIFFER                                      (0<<0)
 
 // Options for ISO14443A
 #define FPGA_HF_ISO14443A_SNIFFER                                      (0<<0)