//-----------------------------------------------------------------------------\r
// The way that we connect things in low-frequency read mode. In this case\r
-// we are generating the 134 kHz or 125 kHz carrier, and running the\r
-// unmodulated carrier at that frequency. The A/D samples at that same rate,\r
-// and the result is serialized.\r
+// we are generating the unmodulated low frequency carrier.\r
+// The A/D samples at that same rate and the result is serialized.\r
//\r
// Jonathan Westhues, April 2006\r
//-----------------------------------------------------------------------------\r
output ssp_frame, ssp_din, ssp_clk;\r
input cross_hi, cross_lo;\r
output dbg;\r
- input lo_is_125khz;\r
+ input lo_is_125khz; // redundant signal, no longer used anywhere\r
input [7:0] divisor;\r
\r
-// The low-frequency RFID stuff. This is relatively simple, because most\r
-// of the work happens on the ARM, and we just pass samples through. The\r
-// PCK0 must be divided down to generate the A/D clock, and from there by\r
-// a factor of 8 to generate the carrier (that we apply to the coil drivers).\r
-//\r
-// This is also where we decode the received synchronous serial port words,\r
-// to determine how to drive the output enables.\r
-\r
-// PCK0 will run at (PLL clock) / 4, or 24 MHz. That means that we can do\r
-// 125 kHz by dividing by a further factor of (8*12*2), or ~134 kHz by\r
-// dividing by a factor of (8*11*2) (for 136 kHz, ~2% error, tolerable).\r
-\r
reg [7:0] to_arm_shiftreg;\r
reg [7:0] pck_divider;\r
-reg [6:0] ssp_divider;\r
reg ant_lo;\r
\r
+// this task runs on the rising egde of pck0 clock (24Mhz) and creates ant_lo\r
+// which is high for (divisor+1) pck0 cycles and low for the same duration\r
+// ant_lo is therefore a 50% duty cycle clock signal with a frequency of\r
+// 12Mhz/(divisor+1) which drives the antenna as well as the ADC clock adc_clk\r
always @(posedge pck0)\r
begin\r
- if(pck_divider == 8'd0)\r
+ if(pck_divider == divisor[7:0])\r
begin\r
- pck_divider <= divisor[7:0];\r
+ pck_divider <= 8'd0;\r
ant_lo = !ant_lo;\r
- if(ant_lo == 1'b0)\r
- begin\r
- ssp_divider <= 7'b0011111;\r
- to_arm_shiftreg <= adc_d;\r
- end\r
end\r
else\r
begin\r
- pck_divider <= pck_divider - 1;\r
- if(ssp_divider[6] == 1'b0)\r
- begin\r
- if (ssp_divider[1:0] == 1'b11) to_arm_shiftreg[7:1] <= to_arm_shiftreg[6:0];\r
- ssp_divider <= ssp_divider - 1;\r
- end\r
+ pck_divider <= pck_divider + 1;\r
+ end\r
+end\r
+\r
+// this task also runs at pck0 frequency (24Mhz) and is used to serialize\r
+// the ADC output which is then clocked into the ARM SSP.\r
+\r
+// because ant_lo always transitions when pck_divider = 0 we use the\r
+// pck_divider counter to sync our other signals off it\r
+// we read the ADC value when pck_divider=7 and shift it out on counts 8..15\r
+always @(posedge pck0)\r
+begin\r
+ if((pck_divider == 8'd7) && !ant_lo)\r
+ to_arm_shiftreg <= adc_d;\r
+ else\r
+ begin\r
+ to_arm_shiftreg[7:1] <= to_arm_shiftreg[6:0];\r
+ // simulation showed a glitch occuring due to the LSB of the shifter\r
+ // not being set as we shift bits out\r
+ // this ensures the ssp_din remains low after a transfer and suppresses\r
+ // the glitch that would occur when the last data shifted out ended in\r
+ // a 1 bit and the next data shifted out started with a 0 bit\r
+ to_arm_shiftreg[0] <= 1'b0;\r
end\r
end\r
\r
-assign ssp_din = to_arm_shiftreg[7];\r
-assign ssp_clk = pck_divider[1];\r
-assign ssp_frame = ~ssp_divider[5];\r
+// ADC samples on falling edge of adc_clk, data available on the rising edge\r
+\r
+// example of ssp transfer of binary value 1100101\r
+// start of transfer is indicated by the rise of the ssp_frame signal\r
+// ssp_din changes on the rising edge of the ssp_clk clock and is clocked into\r
+// the ARM by the falling edge of ssp_clk\r
+// _______________________________\r
+// ssp_frame__| |__\r
+// _______ ___ ___\r
+// ssp_din __| |_______| |___| |______\r
+// _ _ _ _ _ _ _ _ _ _\r
+// ssp_clk |_| |_| |_| |_| |_| |_| |_| |_| |_| |_\r
+\r
+// serialized SSP data is gated by ant_lo to suppress unwanted signal\r
+assign ssp_din = to_arm_shiftreg[7] && !ant_lo;\r
+// SSP clock always runs at 24Mhz\r
+assign ssp_clk = pck0;\r
+// SSP frame is gated by ant_lo and goes high when pck_divider=8..15\r
+assign ssp_frame = (pck_divider[7:3] == 5'd1) && !ant_lo;\r
+// unused signals tied low\r
assign pwr_hi = 1'b0;\r
+assign pwr_oe1 = 1'b0;\r
+assign pwr_oe2 = 1'b0;\r
+assign pwr_oe3 = 1'b0;\r
+assign pwr_oe4 = 1'b0;\r
+// this is the antenna driver signal\r
assign pwr_lo = ant_lo;\r
+// ADC clock out of phase with antenna driver\r
assign adc_clk = ~ant_lo;\r
+// ADC clock also routed to debug pin\r
assign dbg = adc_clk;\r
endmodule\r
projects / proxmark3-svn / blobdiff