- uint8_t outBuf[20];
- memset(outBuf, 0, sizeof(outBuf));
- uint8_t mask = 0x01;
- for(;;) {
- int corr0 = 0, corr00 = 0, corr01 = 0, corr1 = 0, corrEOF = 0;
- for(j = 0; j < arraylen(Logic0); j += skip) {
- corr0 += Logic0[j]*dest[i+(j/skip)];
- }
- corr01 = corr00 = corr0;
- for(j = 0; j < arraylen(Logic0); j += skip) {
- corr00 += Logic0[j]*dest[i+arraylen(Logic0)/skip+(j/skip)];
- corr01 += Logic1[j]*dest[i+arraylen(Logic0)/skip+(j/skip)];
- }
- for(j = 0; j < arraylen(Logic1); j += skip) {
- corr1 += Logic1[j]*dest[i+(j/skip)];
- }
- for(j = 0; j < arraylen(FrameEOF); j += skip) {
- corrEOF += FrameEOF[j]*dest[i+(j/skip)];
- }
- // Even things out by the length of the target waveform.
- corr00 *= 2;
- corr01 *= 2;
- corr0 *= 4;
- corr1 *= 4;
-
- if(corrEOF > corr1 && corrEOF > corr00 && corrEOF > corr01) {
- if (DEBUG) Dbprintf("EOF at %d, correlation %d (corr01: %d, corr00: %d, corr1: %d, corr0: %d)",
- i, corrEOF, corr01, corr00, corr1, corr0);
- break;
- } else if(corr1 > corr0) {
- i += arraylen(Logic1)/skip;
- outBuf[k] |= mask;
- } else {
- i += arraylen(Logic0)/skip;
- }
- mask <<= 1;
- if(mask == 0) {
- k++;
- mask = 0x01;
- }
- if((i+(int)arraylen(FrameEOF)/skip) >= 4000) {
- DbpString("ran off end!");
- break;
- }
+ // Set up the demodulator for tag -> reader responses.
+ DemodInit(Demod, response);
+
+ // wait for last transfer to complete
+ while (!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXEMPTY));
+
+ // And put the FPGA in the appropriate mode
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR);
+
+ // Setup and start DMA.
+ FpgaSetupSsc(FPGA_MAJOR_MODE_HF_READER_RX_XCORR);
+ FpgaSetupSscDma((uint8_t*) dmaBuf, ISO15693_DMA_BUFFER_SIZE);
+
+ uint16_t *upTo = dmaBuf;
+ lastRxCounter = ISO15693_DMA_BUFFER_SIZE;
+
+ for(;;) {
+ int behindBy = (lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR) & (ISO15693_DMA_BUFFER_SIZE-1);
+ if(behindBy > maxBehindBy) {
+ maxBehindBy = behindBy;