Hitag fixes (#887)

[proxmark3-svn] / fpga / min_max_tracker.v

diff --git a/fpga/min_max_tracker.v b/fpga/min_max_tracker.v
index 8abd40fba848845d6e6756b707886f69e4fd7382..c47cfd3d289021a939a31217f3bd0f87903f2236 100644 (file)
--- a/fpga/min_max_tracker.v
+++ b/fpga/min_max_tracker.v
@@ -25,7 +25,7 @@ module min_max_tracker(input clk, input [7:0] adc_d, input [7:0] threshold,
        always @(posedge clk)
        begin
                case (state)
-               0:
+               0: // initialize
                        begin
                                if (cur_max_val >= ({1'b0, adc_d} + threshold))
                                        state <= 2;
@@ -36,7 +36,7 @@ module min_max_tracker(input clk, input [7:0] adc_d, input [7:0] threshold,
                                else if (adc_d <= cur_min_val)
                                        cur_min_val <= adc_d;                                   
                        end
-               1:
+               1: // high phase
                        begin
                                if (cur_max_val <= adc_d)
                                        cur_max_val <= adc_d;
@@ -46,7 +46,7 @@ module min_max_tracker(input clk, input [7:0] adc_d, input [7:0] threshold,
                                        max_val <= cur_max_val;
                                end
                        end
-               2:
+               2: // low phase
                        begin
                                if (adc_d <= cur_min_val)
                                        cur_min_val <= adc_d;