Fix for USB uart slowness since PR #720 (#787)

[proxmark3-svn] / armsrc / fpgaloader.c

diff --git a/armsrc/fpgaloader.c b/armsrc/fpgaloader.c
index 77223bd06bcf8f9d8485fe5f496020b6d0db730a..45294d6008fbf47ed628d19b6a92c25778a758b9 100644 (file)
--- a/armsrc/fpgaloader.c
+++ b/armsrc/fpgaloader.c
@@ -112,10 +112,10 @@ void SetupSpi(int mode)
 }
 
 //-----------------------------------------------------------------------------
 }
 
 //-----------------------------------------------------------------------------

-// Set up the synchronous serial port, with the one set of options that we
-// always use when we are talking to the FPGA. Both RX and TX are enabled.
+// Set up the synchronous serial port with the set of options that fits
+// the FPGA mode. Both RX and TX are always enabled.

 //-----------------------------------------------------------------------------
 //-----------------------------------------------------------------------------

-void FpgaSetupSsc(void)
+void FpgaSetupSsc(uint8_t FPGA_mode)

 {
        // First configure the GPIOs, and get ourselves a clock.
        AT91C_BASE_PIOA->PIO_ASR =
 {
        // First configure the GPIOs, and get ourselves a clock.
        AT91C_BASE_PIOA->PIO_ASR =


@@ -134,11 +134,15 @@ void FpgaSetupSsc(void)
        // on RX clock rising edge, sampled on falling edge
        AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(1) | SSC_CLOCK_MODE_START(1);
 
        // on RX clock rising edge, sampled on falling edge
        AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(1) | SSC_CLOCK_MODE_START(1);
 

-       // 8 bits per transfer, no loopback, MSB first, 1 transfer per sync
+       // 8, 16 or 32 bits per transfer, no loopback, MSB first, 1 transfer per sync

        // pulse, no output sync
        // pulse, no output sync

-       AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(8) |     AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);
+       if ((FPGA_mode & 0xe0) == FPGA_MAJOR_MODE_HF_READER_RX_XCORR) {
+               AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(16) | AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);
+       } else {
+               AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(8) | AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);
+       }               

 
 

-       // clock comes from TK pin, no clock output, outputs change on falling
+       // TX clock comes from TK pin, no clock output, outputs change on falling

        // edge of TK, sample on rising edge of TK, start on positive-going edge of sync
        AT91C_BASE_SSC->SSC_TCMR = SSC_CLOCK_MODE_SELECT(2) |   SSC_CLOCK_MODE_START(5);
 
        // edge of TK, sample on rising edge of TK, start on positive-going edge of sync
        AT91C_BASE_SSC->SSC_TCMR = SSC_CLOCK_MODE_SELECT(2) |   SSC_CLOCK_MODE_START(5);
 


@@ -154,17 +158,16 @@ void FpgaSetupSsc(void)
 // ourselves, not to another buffer). The stuff to manipulate those buffers
 // is in apps.h, because it should be inlined, for speed.
 //-----------------------------------------------------------------------------
 // ourselves, not to another buffer). The stuff to manipulate those buffers
 // is in apps.h, because it should be inlined, for speed.
 //-----------------------------------------------------------------------------

-bool FpgaSetupSscDma(uint8_t *buf, int len)
+bool FpgaSetupSscDma(uint8_t *buf, uint16_t sample_count)

 {
        if (buf == NULL) return false;
 
 {
        if (buf == NULL) return false;
 

-       AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;        // Disable DMA Transfer
-       AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) buf;           // transfer to this memory address
-       AT91C_BASE_PDC_SSC->PDC_RCR = len;                                      // transfer this many bytes
-       AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) buf;          // next transfer to same memory address
-       AT91C_BASE_PDC_SSC->PDC_RNCR = len;                                     // ... with same number of bytes
-       AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN;         // go!
-
+       AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;        // Disable DMA Transfer
+       AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) buf;           // transfer to this memory address
+       AT91C_BASE_PDC_SSC->PDC_RCR = sample_count;             // transfer this many samples
+       AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) buf;          // next transfer to same memory address
+       AT91C_BASE_PDC_SSC->PDC_RNCR = sample_count;            // ... with same number of samples      AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN;         // go!
+       AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN;         // go!

        return true;
 }
 
        return true;
 }