+\r
+#define WDT_HIT() AT91C_BASE_WDTC->WDTC_WDCR = 0xa5000001\r
+\r
+#define PWM_CH_MODE_PRESCALER(x) ((x)<<0)\r
+#define PWM_CHANNEL(x) (1<<(x))\r
+\r
+#define TC_CMR_TCCLKS_TIMER_CLOCK1 (0<<0)\r
+#define TC_CMR_TCCLKS_TIMER_CLOCK2 (1<<0)\r
+#define TC_CMR_TCCLKS_TIMER_CLOCK3 (2<<0)\r
+#define TC_CMR_TCCLKS_TIMER_CLOCK4 (3<<0)\r
+#define TC_CMR_TCCLKS_TIMER_CLOCK5 (4<<0)\r
+\r
+#define ADC_CHAN_LF 4\r
+#define ADC_CHAN_HF 5\r
+#define ADC_MODE_PRESCALE(x) ((x)<<8)\r
+#define ADC_MODE_STARTUP_TIME(x) ((x)<<16)\r
+#define ADC_MODE_SAMPLE_HOLD_TIME(x) ((x)<<24)\r
+#define ADC_CHANNEL(x) (1<<(x))\r
+#define ADC_END_OF_CONVERSION(x) (1<<(x))\r
+\r
+#define SSC_CLOCK_MODE_START(x) ((x)<<8)\r
+#define SSC_FRAME_MODE_WORDS_PER_TRANSFER(x) ((x)<<8)\r
+#define SSC_CLOCK_MODE_SELECT(x) ((x)<<0)\r
+#define SSC_FRAME_MODE_BITS_IN_WORD(x) (((x)-1)<<0)\r
+\r
+#define MC_FLASH_COMMAND_KEY ((0x5a)<<24)\r
+#define MC_FLASH_STATUS_READY (1<<0)\r
+#define MC_FLASH_STATUS_LOCKE (1<<2)\r
+#define MC_FLASH_STATUS_PROGE (1<<3)\r
+#define MC_FLASH_MODE_FLASH_WAIT_STATES(x) ((x)<<8)\r
+#define MC_FLASH_MODE_MASTER_CLK_IN_MHZ(x) ((x)<<16)\r
+#define MC_FLASH_COMMAND_PAGEN(x) ((x)<<8)\r
+\r
+#define RST_CONTROL_KEY (0xa5<<24)\r
+\r
+#define PMC_MAIN_OSC_ENABLE (1<<0)\r
+#define PMC_MAIN_OSC_STABILIZED (1<<0)\r
+#define PMC_MAIN_OSC_PLL_LOCK (1<<2)\r
+#define PMC_MAIN_OSC_MCK_READY (1<<3)\r
+\r
+#define PMC_MAIN_OSC_STARTUP_DELAY(x) ((x)<<8)\r
+#define PMC_PLL_DIVISOR(x) (x)\r
+#define PMC_CLK_PRESCALE_DIV_2 (1<<2)\r
+#define PMC_PLL_MULTIPLIER(x) (((x)-1)<<16)\r
+#define PMC_PLL_COUNT_BEFORE_LOCK(x) ((x)<<8)\r
+#define PMC_PLL_FREQUENCY_RANGE(x) ((x)<<14)\r
+#define PMC_PLL_USB_DIVISOR(x) ((x)<<28)\r
+\r
+#define UDP_INTERRUPT_ENDPOINT(x) (1<<(x))\r
+#define UDP_CSR_BYTES_RECEIVED(x) (((x) >> 16) & 0x7ff)\r
+//**************************************************************\r
+\r
+#define LOW(x) AT91C_BASE_PIOA->PIO_CODR = (x)\r
+#define HIGH(x) AT91C_BASE_PIOA->PIO_SODR = (x)\r