CHG: spelling errors, added help texts in cmdhfmfu.c

[proxmark3-svn] / armsrc / lfops.c

diff --git a/armsrc/lfops.c b/armsrc/lfops.c
index 8d4e2dc9c84e903e23d9051cde65eaafd6f07cac..08bae44db615faa756450813062e404923dd7eaf 100644 (file)
--- a/armsrc/lfops.c
+++ b/armsrc/lfops.c
@@ -8,44 +8,66 @@
 // Also routines for raw mode reading/simulating of LF waveform
 //-----------------------------------------------------------------------------
 
 // Also routines for raw mode reading/simulating of LF waveform
 //-----------------------------------------------------------------------------
 

-#include "proxmark3.h"
+#include "../include/proxmark3.h"

 #include "apps.h"
 #include "util.h"
 #include "apps.h"
 #include "util.h"

-#include "hitag2.h"
-#include "crc16.h"
+#include "../common/crc16.h"
+#include "../common/lfdemod.h"

 #include "string.h"
 #include "string.h"

+#include "crapto1.h"
+#include "mifareutil.h"        
+#include "../include/hitag2.h"

 
 

-void AcquireRawAdcSamples125k(int at134khz)
+// Sam7s has several timers, we will use the source TIMER_CLOCK1 (aka AT91C_TC_CLKS_TIMER_DIV1_CLOCK)
+// TIMER_CLOCK1 = MCK/2, MCK is running at 48 MHz, Timer is running at 48/2 = 24 MHz
+// Hitag units (T0) have duration of 8 microseconds (us), which is 1/125000 per second (carrier)
+// T0 = TIMER_CLOCK1 / 125000 = 192
+#define T0 192
+
+#define SHORT_COIL()   LOW(GPIO_SSC_DOUT)
+#define OPEN_COIL()            HIGH(GPIO_SSC_DOUT)
+
+void LFSetupFPGAForADC(int divisor, bool lf_field)

 {
 {

-       if (at134khz)
+       FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
+       if ( (divisor == 1) || (divisor < 0) || (divisor > 255) )

                FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
                FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz

-       else
+       else if (divisor == 0)

                FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
                FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

+       else
+               FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);

 
 

-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | (lf_field ? FPGA_LF_ADC_READER_FIELD : 0));

 
        // Connect the A/D to the peak-detected low-frequency path.
        SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
 
        // Connect the A/D to the peak-detected low-frequency path.
        SetAdcMuxFor(GPIO_MUXSEL_LOPKD);

-
+       

        // Give it a bit of time for the resonant antenna to settle.
        // Give it a bit of time for the resonant antenna to settle.

-       SpinDelay(50);
-
+       SpinDelay(150);
+       

        // Now set up the SSC to get the ADC samples that are now streaming at us.
        FpgaSetupSsc();
        // Now set up the SSC to get the ADC samples that are now streaming at us.
        FpgaSetupSsc();

+}

 
 

-       // Now call the acquisition routine
+void AcquireRawAdcSamples125k(int divisor)
+{
+       LFSetupFPGAForADC(divisor, true);

        DoAcquisition125k();
 }
 
        DoAcquisition125k();
 }
 

+void SnoopLFRawAdcSamples(int divisor, int trigger_threshold)
+{
+       LFSetupFPGAForADC(divisor, false);
+       DoAcquisition125k_threshold(trigger_threshold);
+}
+

 // split into two routines so we can avoid timing issues after sending commands //
 // split into two routines so we can avoid timing issues after sending commands //

-void DoAcquisition125k(void)
+void DoAcquisition125k_internal(int trigger_threshold, bool silent)

 {
        uint8_t *dest = (uint8_t *)BigBuf;
 {
        uint8_t *dest = (uint8_t *)BigBuf;

-       int n = sizeof(BigBuf);
-       int i;
+       uint16_t i = 0;
+       memset(dest, 0x00, BIGBUF_SIZE);

 
 

-       memset(dest, 0, n);
-       i = 0;

        for(;;) {
                if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
                        AT91C_BASE_SSC->SSC_THR = 0x43;
        for(;;) {
                if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
                        AT91C_BASE_SSC->SSC_THR = 0x43;


@@ -53,39 +75,42 @@ void DoAcquisition125k(void)
                }
                if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
                        dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
                }
                if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
                        dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;

-                       i++;

                        LED_D_OFF();
                        LED_D_OFF();

-                       if (i >= n) break;
+                       if (trigger_threshold != -1 && dest[i] < trigger_threshold)
+                               continue;
+                       else
+                               trigger_threshold = -1;
+                       if (++i >= BIGBUF_SIZE) break;

                }
        }
                }
        }

-       Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",
+       if (!silent){
+               Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",

                        dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]);
                        dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]);

+       }

 }
 }

-
+void DoAcquisition125k_threshold(int trigger_threshold) {
+        DoAcquisition125k_internal(trigger_threshold, true);
+}
+void DoAcquisition125k() {
+        DoAcquisition125k_internal(-1, true);
+}      
+       

 void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
 {
 void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
 {

-       int at134khz;
-
+       FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
+       

        /* Make sure the tag is reset */
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
        SpinDelay(2500);
 
        /* Make sure the tag is reset */
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
        SpinDelay(2500);
 

+       int divisor = 95; // 125 KHz

        // see if 'h' was specified
        if (command[strlen((char *) command) - 1] == 'h')
        // see if 'h' was specified
        if (command[strlen((char *) command) - 1] == 'h')

-               at134khz = TRUE;
-       else
-               at134khz = FALSE;
-
-       if (at134khz)
-               FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
-       else
-               FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-
-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+               divisor = 88; // 134.8 KHz

 
 

+       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor); 
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

        // Give it a bit of time for the resonant antenna to settle.
        // Give it a bit of time for the resonant antenna to settle.

-       SpinDelay(50);
-       // And a little more time for the tag to fully power up

        SpinDelay(2000);
 
        // Now set up the SSC to get the ADC samples that are now streaming at us.
        SpinDelay(2000);
 
        // Now set up the SSC to get the ADC samples that are now streaming at us.


@@ -96,12 +121,9 @@ void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1,
                FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
                LED_D_OFF();
                SpinDelayUs(delay_off);
                FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
                LED_D_OFF();
                SpinDelayUs(delay_off);

-               if (at134khz)
-                       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
-               else
-                       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
+               FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor); 

 
 

-               FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+               FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

                LED_D_ON();
                if(*(command++) == '0')
                        SpinDelayUs(period_0);
                LED_D_ON();
                if(*(command++) == '0')
                        SpinDelayUs(period_0);


@@ -111,15 +133,11 @@ void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1,
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
        LED_D_OFF();
        SpinDelayUs(delay_off);
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
        LED_D_OFF();
        SpinDelayUs(delay_off);

-       if (at134khz)
-               FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
-       else
-               FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-
-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor); 
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

 
        // now do the read
 
        // now do the read

-       DoAcquisition125k();
+       DoAcquisition125k(-1);

 }
 
 /* blank r/w tag data stream
 }
 
 /* blank r/w tag data stream


@@ -143,8 +161,6 @@ void ReadTItag(void)
 
        signed char *dest = (signed char *)BigBuf;
        int n = sizeof(BigBuf);
 
        signed char *dest = (signed char *)BigBuf;
        int n = sizeof(BigBuf);

-//     int *dest = GraphBuffer;
-//     int n = GraphTraceLen;

 
        // 128 bit shift register [shift3:shift2:shift1:shift0]
        uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
 
        // 128 bit shift register [shift3:shift2:shift1:shift0]
        uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;


@@ -156,6 +172,7 @@ void ReadTItag(void)
        uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
 
        // TI tags charge at 134.2Khz
        uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
 
        // TI tags charge at 134.2Khz

+       FpgaDownloadAndGo(FPGA_BITSTREAM_LF);

        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
 
        // Place FPGA in passthrough mode, in this mode the CROSS_LO line
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
 
        // Place FPGA in passthrough mode, in this mode the CROSS_LO line


@@ -272,17 +289,17 @@ void WriteTIbyte(uint8_t b)
        {
                if (b&(1<<i)) {
                        // stop modulating antenna
        {
                if (b&(1<<i)) {
                        // stop modulating antenna

-                       LOW(GPIO_SSC_DOUT);
+                       SHORT_COIL();

                        SpinDelayUs(1000);
                        // modulate antenna
                        SpinDelayUs(1000);
                        // modulate antenna

-                       HIGH(GPIO_SSC_DOUT);
+                       OPEN_COIL();

                        SpinDelayUs(1000);
                } else {
                        // stop modulating antenna
                        SpinDelayUs(1000);
                } else {
                        // stop modulating antenna

-                       LOW(GPIO_SSC_DOUT);
+                       SHORT_COIL();

                        SpinDelayUs(300);
                        // modulate antenna
                        SpinDelayUs(300);
                        // modulate antenna

-                       HIGH(GPIO_SSC_DOUT);
+                       OPEN_COIL();

                        SpinDelayUs(1700);
                }
        }
                        SpinDelayUs(1700);
                }
        }


@@ -363,6 +380,7 @@ void AcquireTiType(void)
 // if not provided a valid crc will be computed from the data and written.
 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
 {
 // if not provided a valid crc will be computed from the data and written.
 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
 {

+       FpgaDownloadAndGo(FPGA_BITSTREAM_LF);   

        if(crc == 0) {
                crc = update_crc16(crc, (idlo)&0xff);
                crc = update_crc16(crc, (idlo>>8)&0xff);
        if(crc == 0) {
                crc = update_crc16(crc, (idlo)&0xff);
                crc = update_crc16(crc, (idlo>>8)&0xff);


@@ -429,59 +447,166 @@ void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
        DbpString("Now use tiread to check");
 }
 
        DbpString("Now use tiread to check");
 }
 

-void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
+
+        
+// PIO_CODR = Clear Output Data Register
+// PIO_SODR = Set Output Data Register
+//#define LOW(x)        AT91C_BASE_PIOA->PIO_CODR = (x)
+//#define HIGH(x)       AT91C_BASE_PIOA->PIO_SODR = (x)
+void SimulateTagLowFrequency( uint16_t period, uint32_t gap, uint8_t ledcontrol)

 {
 {

-       int i;
-       uint8_t *tab = (uint8_t *)BigBuf;
-    
-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
-    
-       AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
-    
+       LED_D_ON();
+
+       uint16_t i = 0;
+       uint8_t send = 0;
+       
+       //int overflow = 0;
+       uint8_t *buf = (uint8_t *)BigBuf;
+
+       FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD); 
+       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
+       SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
+       RELAY_OFF();
+       
+       // Configure output pin that is connected to the FPGA (for modulating)

        AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
        AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;

-       AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
-    
-#define SHORT_COIL()   LOW(GPIO_SSC_DOUT)
-#define OPEN_COIL()            HIGH(GPIO_SSC_DOUT)
-    
-       i = 0;
-       for(;;) {
-               while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
-                       if(BUTTON_PRESS()) {
-                               DbpString("Stopped");
-                               return;
+       AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
+
+       SHORT_COIL();
+
+       // Enable Peripheral Clock for TIMER_CLOCK0, used to measure exact timing before answering
+       AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0);
+       
+       // Enable Peripheral Clock for TIMER_CLOCK1, used to capture edges of the reader frames
+       AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
+       AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME;
+       
+    // Disable timer during configuration      
+       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
+       
+       // Capture mode, default timer source = MCK/2 (TIMER_CLOCK1), TIOA is external trigger,
+       // external trigger rising edge, load RA on rising edge of TIOA.
+       AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK | AT91C_TC_ETRGEDG_RISING | AT91C_TC_ABETRG | AT91C_TC_LDRA_RISING;
+       
+       // Enable and reset counter
+       //AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+
+       while(!BUTTON_PRESS()) { 
+               WDT_HIT();
+               
+               // Receive frame, watch for at most T0*EOF periods
+               while (AT91C_BASE_TC1->TC_CV < T0 * 55) {
+
+               // Check if rising edge in modulation is detected
+                       if(AT91C_BASE_TC1->TC_SR & AT91C_TC_LDRAS) {
+                               // Retrieve the new timing values 
+                               //int ra = (AT91C_BASE_TC1->TC_RA/T0) + overflow;
+                               //Dbprintf("Timing value - %d  %d", ra, overflow);
+                               //overflow = 0;
+
+                               // Reset timer every frame, we have to capture the last edge for timing
+                               AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+                               send = 1;
+                               
+                               LED_B_ON();

                        }
                        }

-                       WDT_HIT();
-               }
-        
-               if (ledcontrol)
-                       LED_D_ON();
-        
-               if(tab[i])
-                       OPEN_COIL();
-               else
-                       SHORT_COIL();
-        
-               if (ledcontrol)
-                       LED_D_OFF();
-        
-               while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
-                       if(BUTTON_PRESS()) {
-                               DbpString("Stopped");
-                               return;
+               } 
+
+               if ( send ) {
+                       // Disable timer 1 with external trigger to avoid triggers during our own modulation
+                       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
+                       
+                       // Wait for HITAG_T_WAIT_1 carrier periods after the last reader bit,
+                       // not that since the clock counts since the rising edge, but T_Wait1 is
+                       // with respect to the falling edge, we need to wait actually (T_Wait1 - T_Low)
+                       // periods. The gap time T_Low varies (4..10). All timer values are in 
+                       // terms of T0 units
+                       while(AT91C_BASE_TC0->TC_CV < T0 * 16  );
+                       
+                       // datat kommer in som 1 bit för varje position i arrayn
+                       for(i = 0; i < period; ++i) {
+                               
+                               // Reset clock for the next bit 
+                               AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;
+
+                               if ( buf[i] > 0 )
+                                       HIGH(GPIO_SSC_DOUT);
+                               else
+                                       LOW(GPIO_SSC_DOUT);
+                               
+                               while(AT91C_BASE_TC0->TC_CV < T0 * 1 );

                        }
                        }

-                       WDT_HIT();
+                       // Drop modulation
+                       LOW(GPIO_SSC_DOUT);
+                                                       
+                       // Enable and reset external trigger in timer for capturing future frames
+                       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+                       LED_B_OFF();

                }
                }

-        
-               i++;
-               if(i == period) {
-                       i = 0;
-                       if (gap) {
-                               SHORT_COIL();
-                               SpinDelayUs(gap);
+               
+               send = 0;
+               
+               // Save the timer overflow, will be 0 when frame was received
+               //overflow += (AT91C_BASE_TC1->TC_CV/T0);
+               
+               // Reset the timer to restart while-loop that receives frames
+               AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG;
+       }
+       
+       LED_B_OFF();
+       LED_D_OFF();
+       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
+       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+       
+       DbpString("Sim Stopped");
+}
+
+
+void SimulateTagLowFrequencyA(int len, int gap)
+{
+       uint8_t *buf = (uint8_t *)BigBuf;
+
+       FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
+       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_TOGGLE_MODE); // new izsh toggle mode!
+       
+       // Connect the A/D to the peak-detected low-frequency path.
+       SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
+
+       // Now set up the SSC to get the ADC samples that are now streaming at us.
+       FpgaSetupSsc();
+       SpinDelay(5);
+       
+       AT91C_BASE_SSC->SSC_THR = 0x00;
+       
+       int i = 0;
+       while(!BUTTON_PRESS()) { 
+               WDT_HIT();
+               if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
+                       
+                       if ( buf[i] > 0 )
+                               AT91C_BASE_SSC->SSC_THR = 0x43;
+                       else
+                               AT91C_BASE_SSC->SSC_THR = 0x00;
+
+                       ++i;
+                       LED_A_ON();
+                       if (i >= len){
+                               i = 0;

                        }
                }
                        }
                }

+               
+               if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
+                       volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
+                       (void)r;
+                       LED_A_OFF();
+               }

        }
        }

+       DbpString("lf simulate stopped");
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);

 }
 
 #define DEBUG_FRAME_CONTENTS 1
 }
 
 #define DEBUG_FRAME_CONTENTS 1


@@ -490,12 +615,12 @@ void SimulateTagLowFrequencyBidir(int divisor, int t0)
 }
 
 // compose fc/8 fc/10 waveform
 }
 
 // compose fc/8 fc/10 waveform

-static void fc(int c, int *n) {
+static void fc(int c, uint16_t *n) {

        uint8_t *dest = (uint8_t *)BigBuf;
        int idx;
 
        // for when we want an fc8 pattern every 4 logical bits
        uint8_t *dest = (uint8_t *)BigBuf;
        int idx;
 
        // for when we want an fc8 pattern every 4 logical bits

-       if(c==0) {
+       if(c == 0) {

                dest[((*n)++)]=1;
                dest[((*n)++)]=1;
                dest[((*n)++)]=0;
                dest[((*n)++)]=1;
                dest[((*n)++)]=1;
                dest[((*n)++)]=0;


@@ -506,7 +631,7 @@ static void fc(int c, int *n) {
                dest[((*n)++)]=0;
        }
        //      an fc/8  encoded bit is a bit pattern of  11000000  x6 = 48 samples
                dest[((*n)++)]=0;
        }
        //      an fc/8  encoded bit is a bit pattern of  11000000  x6 = 48 samples

-       if(c==8) {
+       if(c == 8) {

                for (idx=0; idx<6; idx++) {
                        dest[((*n)++)]=1;
                        dest[((*n)++)]=1;
                for (idx=0; idx<6; idx++) {
                        dest[((*n)++)]=1;
                        dest[((*n)++)]=1;


@@ -520,8 +645,8 @@ static void fc(int c, int *n) {
        }
 
        //      an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples
        }
 
        //      an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples

-       if(c==10) {
-               for (idx=0; idx<5; idx++) {
+       if(c == 10) {
+               for (idx = 0; idx < 5; idx++) {

                        dest[((*n)++)]=1;
                        dest[((*n)++)]=1;
                        dest[((*n)++)]=1;
                        dest[((*n)++)]=1;
                        dest[((*n)++)]=1;
                        dest[((*n)++)]=1;


@@ -538,9 +663,9 @@ static void fc(int c, int *n) {
 
 // prepare a waveform pattern in the buffer based on the ID given then
 // simulate a HID tag until the button is pressed
 
 // prepare a waveform pattern in the buffer based on the ID given then
 // simulate a HID tag until the button is pressed

-void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
+void CmdHIDsimTAG(int hi, int lo, uint8_t ledcontrol)

 {
 {

-       int n=0, i=0;
+       uint16_t n = 0, i = 0;

        /*
         HID tag bitstream format
         The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
        /*
         HID tag bitstream format
         The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits


@@ -551,11 +676,11 @@ void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
         nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
        */
 
         nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
        */
 

-       if (hi>0xFFF) {
+       if (hi > 0xFFF) {

                DbpString("Tags can only have 44 bits.");
                return;
        }
                DbpString("Tags can only have 44 bits.");
                return;
        }

-       fc(0,&n);
+       fc(0, &n);

        // special start of frame marker containing invalid bit sequences
        fc(8,  &n);     fc(8,  &n);     // invalid
        fc(8,  &n);     fc(10, &n); // logical 0
        // special start of frame marker containing invalid bit sequences
        fc(8,  &n);     fc(8,  &n);     // invalid
        fc(8,  &n);     fc(10, &n); // logical 0


@@ -564,9 +689,9 @@ void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
 
        WDT_HIT();
        // manchester encode bits 43 to 32
 
        WDT_HIT();
        // manchester encode bits 43 to 32

-       for (i=11; i>=0; i--) {
-               if ((i%4)==3) fc(0,&n);
-               if ((hi>>i)&1) {
+       for (i = 11; i >= 0; i--) {
+               if ((i % 4) == 3) fc(0, &n);
+               if ((hi >> i) & 1) {

                        fc(10, &n);     fc(8,  &n);             // low-high transition
                } else {
                        fc(8,  &n);     fc(10, &n);             // high-low transition
                        fc(10, &n);     fc(8,  &n);             // low-high transition
                } else {
                        fc(8,  &n);     fc(10, &n);             // high-low transition


@@ -575,9 +700,9 @@ void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
 
        WDT_HIT();
        // manchester encode bits 31 to 0
 
        WDT_HIT();
        // manchester encode bits 31 to 0

-       for (i=31; i>=0; i--) {
-               if ((i%4)==3) fc(0,&n);
-               if ((lo>>i)&1) {
+       for (i = 31; i >= 0; i--) {
+               if ((i % 4 ) == 3) fc(0, &n);
+               if ((lo >> i ) & 1) {

                        fc(10, &n);     fc(8,  &n);             // low-high transition
                } else {
                        fc(8,  &n);     fc(10, &n);             // high-low transition
                        fc(10, &n);     fc(8,  &n);             // low-high transition
                } else {
                        fc(8,  &n);     fc(10, &n);             // high-low transition


@@ -586,223 +711,223 @@ void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
 
        if (ledcontrol)
                LED_A_ON();
 
        if (ledcontrol)
                LED_A_ON();

+       

        SimulateTagLowFrequency(n, 0, ledcontrol);
 
        if (ledcontrol)
                LED_A_OFF();
 }
 
        SimulateTagLowFrequency(n, 0, ledcontrol);
 
        if (ledcontrol)
                LED_A_OFF();
 }
 

-
-// loop to capture raw HID waveform then FSK demodulate the TAG ID from it
+// loop to get raw HID waveform then FSK demodulate the TAG ID from it

 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
 {
        uint8_t *dest = (uint8_t *)BigBuf;
 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
 {
        uint8_t *dest = (uint8_t *)BigBuf;

-       int m=0, n=0, i=0, idx=0, found=0, lastval=0;
-  uint32_t hi2=0, hi=0, lo=0;
+       uint32_t hi2 = 0, hi = 0, lo = 0;

 
 

-       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+       // Configure to go in 125Khz listen mode
+       LFSetupFPGAForADC(0, true);

 
 

-       // Connect the A/D to the peak-detected low-frequency path.
-       SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
+       while(!BUTTON_PRESS()) {

 
 

-       // Give it a bit of time for the resonant antenna to settle.
-       SpinDelay(50);
+               WDT_HIT();
+               if (ledcontrol) LED_A_ON();

 
 

-       // Now set up the SSC to get the ADC samples that are now streaming at us.
-       FpgaSetupSsc();
+               DoAcquisition125k_internal(-1,true);
+
+               // FSK demodulator
+               int bitLen = HIDdemodFSK(dest,BIGBUF_SIZE,&hi2,&hi,&lo);

 
 

-       for(;;) {

                WDT_HIT();
                WDT_HIT();

-               if (ledcontrol)
-                       LED_A_ON();
-               if(BUTTON_PRESS()) {
-                       DbpString("Stopped");
-                       if (ledcontrol)
-                               LED_A_OFF();
-                       return;
-               }

 
 

-               i = 0;
-               m = sizeof(BigBuf);
-               memset(dest,128,m);
-               for(;;) {
-                       if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
-                               AT91C_BASE_SSC->SSC_THR = 0x43;
-                               if (ledcontrol)
-                                       LED_D_ON();
-                       }
-                       if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
-                               dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
-                               // we don't care about actual value, only if it's more or less than a
-                               // threshold essentially we capture zero crossings for later analysis
-                               if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
-                               i++;
-                               if (ledcontrol)
-                                       LED_D_OFF();
-                               if(i >= m) {
-                                       break;
+               if (bitLen > 0 && lo > 0){
+
+               // final loop, go over previously decoded manchester data and decode into usable tag ID
+               // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
+
+                       if (hi2 != 0){ 
+                               //extra large HID tags
+                               Dbprintf("TAG ID: %x%08x%08x (%d)",
+                                        (unsigned int) hi2,
+                                        (unsigned int) hi,
+                                        (unsigned int) lo,
+                                        (unsigned int) (lo >> 1) & 0xFFFF);
+                                        
+                       } else {
+                               //standard HID tags <38 bits
+                               uint8_t bitlen = 0;
+                               uint32_t fc = 0;
+                               uint32_t cardnum = 0;
+
+                               if ((( hi >> 5 ) & 1) ==1){//if bit 38 is set then < 37 bit format is used
+                                       uint32_t lo2 = 0;
+                                       lo2 = (((hi & 31) << 12) | (lo >> 20)); //get bits 21-37 to check for format len bit                                    
+                                       uint8_t idx3 = 1;
+                                       while(lo2 > 1){ //find last bit set to 1 (format len bit)
+                                               lo2 = lo2 >> 1;
+                                               idx3++;
+                                       }
+                                       bitlen =idx3 + 19;  
+                                       fc = 0;
+                                       cardnum = 0;
+                                       if(bitlen == 26){
+                                               cardnum = (lo >> 1) & 0xFFFF;
+                                               fc = (lo >> 17) & 0xFF;
+                                       }
+                                       if(bitlen == 37){
+                                               cardnum = (lo >> 1) & 0x7FFFF;
+                                               fc = ((hi & 0xF) << 12)|( lo >> 20);
+                                       }
+                                       if(bitlen == 34){
+                                               cardnum = (lo >> 1) & 0xFFFF;
+                                               fc = ((hi & 1) << 15) | (lo >> 17);
+                                       }
+                                       if(bitlen == 35){
+                                               cardnum = (lo >> 1 ) & 0xFFFFF;
+                                               fc = ((hi & 1) << 11 ) | ( lo >> 21);
+                                       }

                                }
                                }

+                               else { //if bit 38 is not set then 37 bit format is used
+                                       bitlen = 37;
+                                       fc = 0;
+                                       cardnum = 0;
+                                       if(bitlen == 37){
+                                               cardnum = ( lo >> 1) & 0x7FFFF;
+                                               fc = ((hi & 0xF) << 12 ) |(lo >> 20);
+                                       }
+                               }
+                               Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
+                                       (unsigned int) hi,
+                                       (unsigned int) lo,
+                                       (unsigned int) (lo >> 1) & 0xFFFF,
+                                       (unsigned int) bitlen,
+                                       (unsigned int) fc,
+                                       (unsigned int) cardnum);

                        }
                        }

+                       if (findone){
+                               if (ledcontrol) LED_A_OFF();
+                               return;
+                       }
+                       // reset
+                       hi2 = hi = lo = 0;

                }
                }

+               WDT_HIT();
+       }       
+       DbpString("Stopped");
+       if (ledcontrol) LED_A_OFF();
+}
+
+void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
+{
+       uint8_t *dest = (uint8_t *)BigBuf;
+       uint32_t bitLen = 0;
+       int clk = 0, invert = 0, errCnt  = 0;
+       uint64_t lo = 0;
+       
+       // Configure to go in 125Khz listen mode
+       LFSetupFPGAForADC(0, true);

 
 

+       while(!BUTTON_PRESS()) {
+
+               WDT_HIT();
+               if (ledcontrol) LED_A_ON();
+
+               DoAcquisition125k_internal(-1,true);
+       

                // FSK demodulator
                // FSK demodulator

+               bitLen = BIGBUF_SIZE;
+               errCnt = askmandemod(dest,&bitLen,&clk,&invert); 
+               if ( errCnt < 0 ) continue;

 
 

-               // sync to first lo-hi transition
-               for( idx=1; idx<m; idx++) {
-                       if (dest[idx-1]<dest[idx])
-                               lastval=idx;
-                               break;
+               WDT_HIT();
+               
+               lo = Em410xDecode(dest,bitLen);
+               
+               if ( lo <= 0) continue;
+                               
+               Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
+                       (uint32_t)(lo >> 32),
+                       (uint32_t)lo,
+                       (uint32_t)(lo & 0xFFFF),
+                       (uint32_t)((lo >> 16LL) & 0xFF),
+                       (uint32_t)(lo & 0xFFFFFF)
+               );
+
+               if (findone){
+                       if (ledcontrol) LED_A_OFF();
+                               return;

                }
                }

+               

                WDT_HIT();
                WDT_HIT();

+               lo = clk = invert = errCnt = 0;
+       }
+       DbpString("Stopped");
+       if (ledcontrol) LED_A_OFF();
+}

 
 

-               // count cycles between consecutive lo-hi transitions, there should be either 8 (fc/8)
-               // or 10 (fc/10) cycles but in practice due to noise etc we may end up with with anywhere
-               // between 7 to 11 cycles so fuzz it by treat anything <9 as 8 and anything else as 10
-               for( i=0; idx<m; idx++) {
-                       if (dest[idx-1]<dest[idx]) {
-                               dest[i]=idx-lastval;
-                               if (dest[i] <= 8) {
-                                               dest[i]=1;
-                               } else {
-                                               dest[i]=0;
-                               }
+void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
+{
+       uint8_t *dest = (uint8_t *)BigBuf;
+       int idx = 0;
+       uint32_t code = 0, code2 = 0;
+       uint8_t version = 0;
+       uint8_t facilitycode = 0;
+       uint16_t number = 0;
+
+       LFSetupFPGAForADC(0, true);
+
+       while(!BUTTON_PRESS()) {

 
 

-                               lastval=idx;
-                               i++;
-                       }
-               }
-               m=i;

                WDT_HIT();
                WDT_HIT();

+               if (ledcontrol) LED_A_ON();

 
 

-               // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
-               lastval=dest[0];
-               idx=0;
-               i=0;
-               n=0;
-               for( idx=0; idx<m; idx++) {
-                       if (dest[idx]==lastval) {
-                               n++;
-                       } else {
-                               // a bit time is five fc/10 or six fc/8 cycles so figure out how many bits a pattern width represents,
-                               // an extra fc/8 pattern preceeds every 4 bits (about 200 cycles) just to complicate things but it gets
-                               // swallowed up by rounding
-                               // expected results are 1 or 2 bits, any more and it's an invalid manchester encoding
-                               // special start of frame markers use invalid manchester states (no transitions) by using sequences
-                               // like 111000
-                               if (dest[idx-1]) {
-                                       n=(n+1)/6;                      // fc/8 in sets of 6
-                               } else {
-                                       n=(n+1)/5;                      // fc/10 in sets of 5
-                               }
-                               switch (n) {                    // stuff appropriate bits in buffer
-                                       case 0:
-                                       case 1: // one bit
-                                               dest[i++]=dest[idx-1];
-                                               break;
-                                       case 2: // two bits
-                                               dest[i++]=dest[idx-1];
-                                               dest[i++]=dest[idx-1];
-                                               break;
-                                       case 3: // 3 bit start of frame markers
-                                               dest[i++]=dest[idx-1];
-                                               dest[i++]=dest[idx-1];
-                                               dest[i++]=dest[idx-1];
-                                               break;
-                                       // When a logic 0 is immediately followed by the start of the next transmisson
-                                       // (special pattern) a pattern of 4 bit duration lengths is created.
-                                       case 4:
-                                               dest[i++]=dest[idx-1];
-                                               dest[i++]=dest[idx-1];
-                                               dest[i++]=dest[idx-1];
-                                               dest[i++]=dest[idx-1];
-                                               break;
-                                       default:        // this shouldn't happen, don't stuff any bits
-                                               break;
-                               }
-                               n=0;
-                               lastval=dest[idx];
-                       }
-               }
-               m=i;
+               DoAcquisition125k_internal(-1, true);
+
+               idx = IOdemodFSK(dest, BIGBUF_SIZE);
+               
+               if ( idx < 0 )
+                       continue;
+                       

                WDT_HIT();
 
                WDT_HIT();
 

-               // final loop, go over previously decoded manchester data and decode into usable tag ID
-               // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
-               for( idx=0; idx<m-6; idx++) {
-                       // search for a start of frame marker
-                       if ( dest[idx] && dest[idx+1] && dest[idx+2] && (!dest[idx+3]) && (!dest[idx+4]) && (!dest[idx+5]) )
-                       {
-                               found=1;
-                               idx+=6;
-        if (found && (hi2|hi|lo)) {
-          if (hi2 != 0){
-            Dbprintf("TAG ID: %x%08x%08x (%d)",
-                     (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
-          }
-          else {
-            Dbprintf("TAG ID: %x%08x (%d)",
-                     (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
-          }
-                                       /* if we're only looking for one tag */
-                                       if (findone)
-                                       {
-                                               *high = hi;
-                                               *low = lo;
-                                               return;
-                                       }
-          hi2=0;
-                                       hi=0;
-                                       lo=0;
-                                       found=0;
-                               }
-                       }
-                       if (found) {
-                               if (dest[idx] && (!dest[idx+1]) ) {
-          hi2=(hi2<<1)|(hi>>31);
-                                       hi=(hi<<1)|(lo>>31);
-                                       lo=(lo<<1)|0;
-                               } else if ( (!dest[idx]) && dest[idx+1]) {
-          hi2=(hi2<<1)|(hi>>31);
-                                       hi=(hi<<1)|(lo>>31);
-                                       lo=(lo<<1)|1;
-                               } else {
-                                       found=0;
-          hi2=0;
-                                       hi=0;
-                                       lo=0;
-                               }
-                               idx++;
-                       }
-                       if ( dest[idx] && dest[idx+1] && dest[idx+2] && (!dest[idx+3]) && (!dest[idx+4]) && (!dest[idx+5]) )
-                       {
-                               found=1;
-                               idx+=6;
-                               if (found && (hi|lo)) {
-          if (hi2 != 0){
-            Dbprintf("TAG ID: %x%08x%08x (%d)",
-                     (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
-          }
-          else {
-            Dbprintf("TAG ID: %x%08x (%d)",
-                     (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
-          }
-                                       /* if we're only looking for one tag */
-                                       if (findone)
-                                       {
-                                               *high = hi;
-                                               *low = lo;
-                                               return;
-                                       }
-          hi2=0;
-                                       hi=0;
-                                       lo=0;
-                                       found=0;
-                               }
-                       }
+               //Index map
+               //0 10 20 30 40 50 60
+               //| | | | | | |
+               //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
+               //-----------------------------------------------------------------------------
+               //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 ???????? 11
+               //
+               //XSF(version)facility:codeone+codetwo
+               //Handle the data
+
+               if(findone){ //only print binary if we are doing one
+                       Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
+                       Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
+                       Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
+                       Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
+                       Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
+                       Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
+                       Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);

                }
                }

-               WDT_HIT();
+
+               code = bytebits_to_byte(dest+idx,32);
+               code2 = bytebits_to_byte(dest+idx+32,32);
+               version = bytebits_to_byte(dest+idx+27,8); //14,4
+               facilitycode = bytebits_to_byte(dest+idx+18,8) ;
+               number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
+
+               Dbprintf("XSF(%02d)%02x:%05d (%08x%08x)", version, facilitycode, number, code, code2);                  
+               if (findone){
+                       if (ledcontrol) LED_A_OFF();
+                               return;
+               }
+               code = code2 = 0;
+               version = facilitycode = 0;
+               number = 0;
+               idx = 0;

        }
        }

+
+       DbpString("Stopped");
+       if (ledcontrol) LED_A_OFF();

 }
 
 /*------------------------------
 }
 
 /*------------------------------


@@ -811,14 +936,14 @@ void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
  */
 
 /* T55x7 configuration register definitions */
  */
 
 /* T55x7 configuration register definitions */

-#define T55x7_POR_DELAY                        0x00000001
-#define T55x7_ST_TERMINATOR            0x00000008
-#define T55x7_PWD                      0x00000010
+#define T55x7_POR_DELAY                                0x00000001
+#define T55x7_ST_TERMINATOR                    0x00000008
+#define T55x7_PWD                                      0x00000010

 #define T55x7_MAXBLOCK_SHIFT           5
 #define T55x7_MAXBLOCK_SHIFT           5

-#define T55x7_AOR                      0x00000200
-#define T55x7_PSKCF_RF_2               0
-#define T55x7_PSKCF_RF_4               0x00000400
-#define T55x7_PSKCF_RF_8               0x00000800
+#define T55x7_AOR                                      0x00000200
+#define T55x7_PSKCF_RF_2                       0
+#define T55x7_PSKCF_RF_4                       0x00000400
+#define T55x7_PSKCF_RF_8                       0x00000800

 #define T55x7_MODULATION_DIRECT                0
 #define T55x7_MODULATION_PSK1          0x00001000
 #define T55x7_MODULATION_PSK2          0x00002000
 #define T55x7_MODULATION_DIRECT                0
 #define T55x7_MODULATION_PSK1          0x00001000
 #define T55x7_MODULATION_PSK2          0x00002000


@@ -829,17 +954,17 @@ void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
 #define T55x7_MODULATION_FSK2a         0x00007000
 #define T55x7_MODULATION_MANCHESTER    0x00008000
 #define T55x7_MODULATION_BIPHASE       0x00010000
 #define T55x7_MODULATION_FSK2a         0x00007000
 #define T55x7_MODULATION_MANCHESTER    0x00008000
 #define T55x7_MODULATION_BIPHASE       0x00010000

-#define T55x7_BITRATE_RF_8             0
-#define T55x7_BITRATE_RF_16            0x00040000
-#define T55x7_BITRATE_RF_32            0x00080000
-#define T55x7_BITRATE_RF_40            0x000C0000
-#define T55x7_BITRATE_RF_50            0x00100000
-#define T55x7_BITRATE_RF_64            0x00140000
+#define T55x7_BITRATE_RF_8                     0
+#define T55x7_BITRATE_RF_16                    0x00040000
+#define T55x7_BITRATE_RF_32                    0x00080000
+#define T55x7_BITRATE_RF_40                    0x000C0000
+#define T55x7_BITRATE_RF_50                    0x00100000
+#define T55x7_BITRATE_RF_64                    0x00140000

 #define T55x7_BITRATE_RF_100           0x00180000
 #define T55x7_BITRATE_RF_128           0x001C0000
 
 /* T5555 (Q5) configuration register definitions */
 #define T55x7_BITRATE_RF_100           0x00180000
 #define T55x7_BITRATE_RF_128           0x001C0000
 
 /* T5555 (Q5) configuration register definitions */

-#define T5555_ST_TERMINATOR            0x00000001
+#define T5555_ST_TERMINATOR                    0x00000001

 #define T5555_MAXBLOCK_SHIFT           0x00000001
 #define T5555_MODULATION_MANCHESTER    0
 #define T5555_MODULATION_PSK1          0x00000010
 #define T5555_MAXBLOCK_SHIFT           0x00000001
 #define T5555_MODULATION_MANCHESTER    0
 #define T5555_MODULATION_PSK1          0x00000010


@@ -849,32 +974,43 @@ void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
 #define T5555_MODULATION_FSK2          0x00000050
 #define T5555_MODULATION_BIPHASE       0x00000060
 #define T5555_MODULATION_DIRECT                0x00000070
 #define T5555_MODULATION_FSK2          0x00000050
 #define T5555_MODULATION_BIPHASE       0x00000060
 #define T5555_MODULATION_DIRECT                0x00000070

-#define T5555_INVERT_OUTPUT            0x00000080
-#define T5555_PSK_RF_2                 0
-#define T5555_PSK_RF_4                 0x00000100
-#define T5555_PSK_RF_8                 0x00000200
-#define T5555_USE_PWD                  0x00000400
-#define T5555_USE_AOR                  0x00000800
-#define T5555_BITRATE_SHIFT            12
-#define T5555_FAST_WRITE               0x00004000
-#define T5555_PAGE_SELECT              0x00008000
+#define T5555_INVERT_OUTPUT                    0x00000080
+#define T5555_PSK_RF_2                         0
+#define T5555_PSK_RF_4                         0x00000100
+#define T5555_PSK_RF_8                         0x00000200
+#define T5555_USE_PWD                          0x00000400
+#define T5555_USE_AOR                          0x00000800
+#define T5555_BITRATE_SHIFT                    12
+#define T5555_FAST_WRITE                       0x00004000
+#define T5555_PAGE_SELECT                      0x00008000

 
 /*
  * Relevant times in microsecond
  * To compensate antenna falling times shorten the write times
  * and enlarge the gap ones.
  */
 
 /*
  * Relevant times in microsecond
  * To compensate antenna falling times shorten the write times
  * and enlarge the gap ones.
  */

-#define START_GAP 250
-#define WRITE_GAP 160
-#define WRITE_0   144 // 192
-#define WRITE_1   400 // 432 for T55x7; 448 for E5550
+#define START_GAP 30*8 // 10 - 50fc 250
+#define WRITE_GAP 20*8 //  8 - 30fc
+#define WRITE_0   24*8 // 16 - 31fc 24fc 192
+#define WRITE_1   54*8 // 48 - 63fc 54fc 432 for T55x7; 448 for E5550
+
+//  VALUES TAKEN FROM EM4x function: SendForward
+//  START_GAP = 440;       (55*8) cycles at 125Khz (8us = 1cycle)
+//  WRITE_GAP = 128;       (16*8)
+//  WRITE_1   = 256 32*8;  (32*8) 
+
+//  These timings work for 4469/4269/4305 (with the 55*8 above)
+//  WRITE_0 = 23*8 , 9*8  SpinDelayUs(23*8); 
+
+#define T55xx_SAMPLES_SIZE             12000 // 32 x 32 x 10  (32 bit times numofblock (7), times clock skip..)

 
 // Write one bit to card
 void T55xxWriteBit(int bit)
 {
 
 // Write one bit to card
 void T55xxWriteBit(int bit)
 {

+       FpgaDownloadAndGo(FPGA_BITSTREAM_LF);

        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
-       if (bit == 0)
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
+       if (!bit)

                SpinDelayUs(WRITE_0);
        else
                SpinDelayUs(WRITE_1);
                SpinDelayUs(WRITE_0);
        else
                SpinDelayUs(WRITE_1);


@@ -885,14 +1021,11 @@ void T55xxWriteBit(int bit)
 // Write one card block in page 0, no lock
 void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
 {
 // Write one card block in page 0, no lock
 void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
 {

-       unsigned int i;
+       uint32_t i = 0;

 
 

-       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
-
-       // Give it a bit of time for the resonant antenna to settle.
-       // And for the tag to fully power up
-       SpinDelay(150);
+       // Set up FPGA, 125kHz
+       // Wait for config.. (192+8190xPOW)x8 == 67ms
+       LFSetupFPGAForADC(0, true);

 
        // Now start writting
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 
        // Now start writting
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);


@@ -901,11 +1034,11 @@ void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMod
        // Opcode
        T55xxWriteBit(1);
        T55xxWriteBit(0); //Page 0
        // Opcode
        T55xxWriteBit(1);
        T55xxWriteBit(0); //Page 0

-  if (PwdMode == 1){
-    // Pwd
-    for (i = 0x80000000; i != 0; i >>= 1)
-      T55xxWriteBit(Pwd & i);
-  }
+       if (PwdMode == 1){
+               // Pwd
+               for (i = 0x80000000; i != 0; i >>= 1)
+                       T55xxWriteBit(Pwd & i);
+       }

        // Lock bit
        T55xxWriteBit(0);
 
        // Lock bit
        T55xxWriteBit(0);
 


@@ -920,7 +1053,7 @@ void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMod
        // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
        // so wait a little more)
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
        // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
        // so wait a little more)
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

        SpinDelay(20);
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 }
        SpinDelay(20);
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 }


@@ -928,26 +1061,17 @@ void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMod
 // Read one card block in page 0
 void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
 {
 // Read one card block in page 0
 void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
 {

-       uint8_t *dest = (uint8_t *)BigBuf;
-       int m=0, i=0;
-  
-       m = sizeof(BigBuf);
-  // Clear destination buffer before sending the command
-       memset(dest, 128, m);
-       // Connect the A/D to the peak-detected low-frequency path.
-       SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
-       // Now set up the SSC to get the ADC samples that are now streaming at us.
-       FpgaSetupSsc();
-  
-       LED_D_ON();
-       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
-  
-       // Give it a bit of time for the resonant antenna to settle.
-       // And for the tag to fully power up
-       SpinDelay(150);
-  
-       // Now start writting
+       uint8_t *dest =  get_bigbufptr_recvrespbuf();
+       uint16_t bufferlength = T55xx_SAMPLES_SIZE;
+       uint32_t i = 0;
+
+       // Clear destination buffer before sending the command  0x80 = average.
+       memset(dest, 0x80, bufferlength);
+
+       // Set up FPGA, 125kHz
+       // Wait for config.. (192+8190xPOW)x8 == 67ms
+       LFSetupFPGAForADC(0, true);
+

        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
        SpinDelayUs(START_GAP);
   
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
        SpinDelayUs(START_GAP);
   


@@ -965,53 +1089,41 @@ void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
        for (i = 0x04; i != 0; i >>= 1)
                T55xxWriteBit(Block & i);
   
        for (i = 0x04; i != 0; i >>= 1)
                T55xxWriteBit(Block & i);
   

-  // Turn field on to read the response
-       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+       // Turn field on to read the response
+       TurnReadLFOn();

   
        // Now do the acquisition
        i = 0;
        for(;;) {
                if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
                        AT91C_BASE_SSC->SSC_THR = 0x43;
   
        // Now do the acquisition
        i = 0;
        for(;;) {
                if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
                        AT91C_BASE_SSC->SSC_THR = 0x43;

+                       //AT91C_BASE_SSC->SSC_THR = 0xff;
+                       LED_D_ON();

                }
                if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
                        dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
                }
                if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
                        dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;

-                       // we don't care about actual value, only if it's more or less than a
-                       // threshold essentially we capture zero crossings for later analysis
-      //                       if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
-                       i++;
-                       if (i >= m) break;
+                       ++i;
+                       LED_D_OFF();
+                       if (i >= bufferlength) break;

                }
        }
                }
        }

-  
-  FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
+ 
+       cmd_send(CMD_ACK,0,0,0,0,0);
+    FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off

        LED_D_OFF();
        LED_D_OFF();

-       DbpString("DONE!");

 }
 
 // Read card traceability data (page 1)
 void T55xxReadTrace(void){
 }
 
 // Read card traceability data (page 1)
 void T55xxReadTrace(void){

-       uint8_t *dest = (uint8_t *)BigBuf;
-       int m=0, i=0;
-  
-       m = sizeof(BigBuf);
-  // Clear destination buffer before sending the command
-       memset(dest, 128, m);
-       // Connect the A/D to the peak-detected low-frequency path.
-       SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
-       // Now set up the SSC to get the ADC samples that are now streaming at us.
-       FpgaSetupSsc();
-  
-       LED_D_ON();
-       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+       uint8_t *dest =  get_bigbufptr_recvrespbuf();
+       uint16_t bufferlength = T55xx_SAMPLES_SIZE;
+       uint32_t i = 0;
+       
+       // Clear destination buffer before sending the command 0x80 = average
+       memset(dest, 0x80, bufferlength);  

   
   

-       // Give it a bit of time for the resonant antenna to settle.
-       // And for the tag to fully power up
-       SpinDelay(150);
+       LFSetupFPGAForADC(0, true);

   
   

-       // Now start writting

        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
        SpinDelayUs(START_GAP);
   
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
        SpinDelayUs(START_GAP);
   


@@ -1019,26 +1131,35 @@ void T55xxReadTrace(void){
        T55xxWriteBit(1);
        T55xxWriteBit(1); //Page 1
   
        T55xxWriteBit(1);
        T55xxWriteBit(1); //Page 1
   

-  // Turn field on to read the response
-       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+       // Turn field on to read the response
+       TurnReadLFOn();

   
        // Now do the acquisition
   
        // Now do the acquisition

-       i = 0;

        for(;;) {
                if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
                        AT91C_BASE_SSC->SSC_THR = 0x43;
        for(;;) {
                if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
                        AT91C_BASE_SSC->SSC_THR = 0x43;

+                       LED_D_ON();

                }
                if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
                        dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
                }
                if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
                        dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;

-                       i++;
-                       if (i >= m) break;
+                       ++i;
+                       LED_D_OFF();
+               
+                       if (i >= bufferlength) break;

                }
        }
   
                }
        }
   

-  FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
+       cmd_send(CMD_ACK,0,0,0,0,0);
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off

        LED_D_OFF();
        LED_D_OFF();

-       DbpString("DONE!");
+}
+
+void TurnReadLFOn(){
+       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
+       // Give it a bit of time for the resonant antenna to settle.
+       //SpinDelay(30);
+       SpinDelayUs(8*150);

 }
 
 /*-------------- Cloning routines -----------*/
 }
 
 /*-------------- Cloning routines -----------*/


@@ -1154,7 +1275,7 @@ void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
   }
   
        // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
   }
   
        // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)

-       T55xxWriteBlock(T55x7_BITRATE_RF_50    |
+       T55xxWriteBlock(T55x7_BITRATE_RF_50  |

                   T55x7_MODULATION_FSK2a |
                   last_block << T55x7_MAXBLOCK_SHIFT,
                   0,0,0);
                   T55x7_MODULATION_FSK2a |
                   last_block << T55x7_MAXBLOCK_SHIFT,
                   0,0,0);


@@ -1164,6 +1285,26 @@ void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
        DbpString("DONE!");
 }
 
        DbpString("DONE!");
 }
 

+void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
+{
+   int data1=0, data2=0; //up to six blocks for long format
+       
+    data1 = hi;  // load preamble
+    data2 = lo;
+    
+    LED_D_ON();
+    // Program the data blocks for supplied ID
+    // and the block 0 for HID format
+    T55xxWriteBlock(data1,1,0,0);
+    T55xxWriteBlock(data2,2,0,0);
+       
+    //Config Block
+    T55xxWriteBlock(0x00147040,0,0,0);
+    LED_D_OFF();
+       
+    DbpString("DONE!");
+}
+

 // Define 9bit header for EM410x tags
 #define EM410X_HEADER          0x1FF
 #define EM410X_ID_LENGTH       40
 // Define 9bit header for EM410x tags
 #define EM410X_HEADER          0x1FF
 #define EM410X_ID_LENGTH       40


@@ -1175,6 +1316,7 @@ void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
        uint64_t rev_id = 0;    // reversed ID
        int c_parity[4];        // column parity
        int r_parity = 0;       // row parity
        uint64_t rev_id = 0;    // reversed ID
        int c_parity[4];        // column parity
        int r_parity = 0;       // row parity

+       uint32_t clock = 0;

 
        // Reverse ID bits given as parameter (for simpler operations)
        for (i = 0; i < EM410X_ID_LENGTH; ++i) {
 
        // Reverse ID bits given as parameter (for simpler operations)
        for (i = 0; i < EM410X_ID_LENGTH; ++i) {


@@ -1232,12 +1374,35 @@ void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
        T55xxWriteBlock((uint32_t)id, 2, 0, 0);
 
        // Config for EM410x (RF/64, Manchester, Maxblock=2)
        T55xxWriteBlock((uint32_t)id, 2, 0, 0);
 
        // Config for EM410x (RF/64, Manchester, Maxblock=2)

-       if (card)
+       if (card) {
+               // Clock rate is stored in bits 8-15 of the card value
+               clock = (card & 0xFF00) >> 8;
+               Dbprintf("Clock rate: %d", clock);
+               switch (clock)
+               {
+                       case 32:
+                               clock = T55x7_BITRATE_RF_32;
+                               break;
+                       case 16:
+                               clock = T55x7_BITRATE_RF_16;
+                               break;
+                       case 0:
+                               // A value of 0 is assumed to be 64 for backwards-compatibility
+                               // Fall through...
+                       case 64:
+                               clock = T55x7_BITRATE_RF_64;
+                               break;      
+                       default:
+                               Dbprintf("Invalid clock rate: %d", clock);
+                               return;
+               }
+

                // Writing configuration for T55x7 tag
                // Writing configuration for T55x7 tag

-               T55xxWriteBlock(T55x7_BITRATE_RF_64         |
+               T55xxWriteBlock(clock       |

                                T55x7_MODULATION_MANCHESTER |
                                2 << T55x7_MAXBLOCK_SHIFT,
                                0, 0, 0);
                                T55x7_MODULATION_MANCHESTER |
                                2 << T55x7_MAXBLOCK_SHIFT,
                                0, 0, 0);

+  }

        else
                // Writing configuration for T5555(Q5) tag
                T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
        else
                // Writing configuration for T5555(Q5) tag
                T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |


@@ -1253,7 +1418,6 @@ void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
 // Clone Indala 64-bit tag by UID to T55x7
 void CopyIndala64toT55x7(int hi, int lo)
 {
 // Clone Indala 64-bit tag by UID to T55x7
 void CopyIndala64toT55x7(int hi, int lo)
 {

-

        //Program the 2 data blocks for supplied 64bit UID
        // and the block 0 for Indala64 format
        T55xxWriteBlock(hi,1,0,0);
        //Program the 2 data blocks for supplied 64bit UID
        // and the block 0 for Indala64 format
        T55xxWriteBlock(hi,1,0,0);


@@ -1264,15 +1428,13 @@ void CopyIndala64toT55x7(int hi, int lo)
                        2 << T55x7_MAXBLOCK_SHIFT,
                        0, 0, 0);
        //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
                        2 << T55x7_MAXBLOCK_SHIFT,
                        0, 0, 0);
        //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)

-//     T5567WriteBlock(0x603E1042,0);
+       //      T5567WriteBlock(0x603E1042,0);

 
        DbpString("DONE!");
 
        DbpString("DONE!");

-

 }      
 
 void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
 {
 }      
 
 void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
 {

-

        //Program the 7 data blocks for supplied 224bit UID
        // and the block 0 for Indala224 format
        T55xxWriteBlock(uid1,1,0,0);
        //Program the 7 data blocks for supplied 224bit UID
        // and the block 0 for Indala224 format
        T55xxWriteBlock(uid1,1,0,0);


@@ -1288,10 +1450,9 @@ void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int
                        7 << T55x7_MAXBLOCK_SHIFT,
                        0,0,0);
        //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
                        7 << T55x7_MAXBLOCK_SHIFT,
                        0,0,0);
        //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)

-//     T5567WriteBlock(0x603E10E2,0);
+       //      T5567WriteBlock(0x603E10E2,0);

 
        DbpString("DONE!");
 
        DbpString("DONE!");

-

 }
 
 
 }
 
 


@@ -1409,9 +1570,12 @@ int DemodPCF7931(uint8_t **outBlocks) {
         block_done = 0;
         half_switch = 0;
       }
         block_done = 0;
         half_switch = 0;
       }

+             if(i < GraphTraceLen)
+             {

       if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;
       else dir = 1;
     }
       if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;
       else dir = 1;
     }

+           }

     if(bitidx==255)
       bitidx=0;
     warnings = 0;
     if(bitidx==255)
       bitidx=0;
     warnings = 0;


@@ -1438,7 +1602,6 @@ int IsBlock1PCF7931(uint8_t *Block) {
        
        return 0;
 }
        
        return 0;
 }

-

 #define ALLOC 16
 
 void ReadPCF7931() {
 #define ALLOC 16
 
 void ReadPCF7931() {


@@ -1666,8 +1829,9 @@ void SendForward(uint8_t fwd_bit_count) {
   LED_D_ON();
   
   //Field on
   LED_D_ON();
   
   //Field on

+  FpgaDownloadAndGo(FPGA_BITSTREAM_LF);

   FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
   FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

-  FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+  FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

   
   // Give it a bit of time for the resonant antenna to settle.
   // And for the tag to fully power up
   
   // Give it a bit of time for the resonant antenna to settle.
   // And for the tag to fully power up


@@ -1679,7 +1843,7 @@ void SendForward(uint8_t fwd_bit_count) {
   FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
   SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
   FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
   FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
   SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
   FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

-  FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);//field on
+  FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on

   SpinDelayUs(16*8); //16 cycles on (8us each)
   
   // now start writting
   SpinDelayUs(16*8); //16 cycles on (8us each)
   
   // now start writting


@@ -1691,12 +1855,13 @@ void SendForward(uint8_t fwd_bit_count) {
       FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
       SpinDelayUs(23*8); //16-4 cycles off (8us each)
       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
       FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
       SpinDelayUs(23*8); //16-4 cycles off (8us each)
       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

-      FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);//field on
+      FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on

       SpinDelayUs(9*8); //16 cycles on (8us each)
     }
   }
 }
 
       SpinDelayUs(9*8); //16 cycles on (8us each)
     }
   }
 }
 

+

 void EM4xLogin(uint32_t Password) {
   
   uint8_t fwd_bit_count;
 void EM4xLogin(uint32_t Password) {
   
   uint8_t fwd_bit_count;


@@ -1714,41 +1879,48 @@ void EM4xLogin(uint32_t Password) {
 
 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
   
 
 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
   

-  uint8_t fwd_bit_count;
-  uint8_t *dest = (uint8_t *)BigBuf;
-  int m=0, i=0;
+       uint8_t *dest =   (uint8_t *)BigBuf;
+       uint16_t bufferlength = 12000;
+       uint32_t i = 0;
+
+       // Clear destination buffer before sending the command  0x80 = average.
+       memset(dest, 0x80, bufferlength);
+       
+       uint8_t fwd_bit_count;

   
   

-  //If password mode do login
-  if (PwdMode == 1) EM4xLogin(Pwd);
+       //If password mode do login
+       if (PwdMode == 1) EM4xLogin(Pwd);

   
   

-  forward_ptr = forwardLink_data;
-  fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
-  fwd_bit_count += Prepare_Addr( Address );
+       forward_ptr = forwardLink_data;
+       fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
+       fwd_bit_count += Prepare_Addr( Address );

   
   

-  m = sizeof(BigBuf);
-  // Clear destination buffer before sending the command
-  memset(dest, 128, m);
-  // Connect the A/D to the peak-detected low-frequency path.
-  SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
-  // Now set up the SSC to get the ADC samples that are now streaming at us.
-  FpgaSetupSsc();
+       // Connect the A/D to the peak-detected low-frequency path.
+       SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
+       // Now set up the SSC to get the ADC samples that are now streaming at us.
+       FpgaSetupSsc();

   
   

-  SendForward(fwd_bit_count);
+       SendForward(fwd_bit_count);

   
   

-  // Now do the acquisition
-  i = 0;
-  for(;;) {
-    if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
-      AT91C_BASE_SSC->SSC_THR = 0x43;
-    }
-    if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
-      dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
-      i++;
-      if (i >= m) break;
-    }
-  }
-  FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
-  LED_D_OFF();
+       // // Turn field on to read the response
+       // TurnReadLFOn();
+       
+       // Now do the acquisition
+       i = 0;
+       for(;;) {
+               if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
+                       AT91C_BASE_SSC->SSC_THR = 0x43;
+               }
+               if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
+                       dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
+                       ++i;
+                       if (i >= bufferlength) break;
+               }
+       }
+  
+       cmd_send(CMD_ACK,0,0,0,0,0);
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
+       LED_D_OFF();

 }
 
 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
 }
 
 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {