CHG: lowered the timout again, but re-added the spindelay since 14a requires 5ms...

[proxmark3-svn] / armsrc / fpgaloader.h

diff --git a/armsrc/fpgaloader.h b/armsrc/fpgaloader.h
index 0bad38094b62d355dc6cd13fb427b8c3c9310876..5c0f802e4123340453011b1d984b3d21f05b8ae9 100644 (file)
--- a/armsrc/fpgaloader.h
+++ b/armsrc/fpgaloader.h
@@ -17,6 +17,7 @@ void FpgaGatherVersion(int bitstream_version, char *dst, int len);
 void FpgaSetupSsc(void);
 void SetupSpi(int mode);
 bool FpgaSetupSscDma(uint8_t *buf, int len);
 void FpgaSetupSsc(void);
 void SetupSpi(int mode);
 bool FpgaSetupSscDma(uint8_t *buf, int len);

+void Fpga_print_status();

 #define FpgaDisableSscDma(void)        AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;
 #define FpgaEnableSscDma(void) AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN;
 void SetAdcMuxFor(uint32_t whichGpio);
 #define FpgaDisableSscDma(void)        AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;
 #define FpgaEnableSscDma(void) AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN;
 void SetAdcMuxFor(uint32_t whichGpio);


@@ -42,6 +43,7 @@ void SetAdcMuxFor(uint32_t whichGpio);
 #define FPGA_MAJOR_MODE_HF_READER_RX_XCORR                     (1<<5)
 #define FPGA_MAJOR_MODE_HF_SIMULATOR                           (2<<5)
 #define FPGA_MAJOR_MODE_HF_ISO14443A                           (3<<5)
 #define FPGA_MAJOR_MODE_HF_READER_RX_XCORR                     (1<<5)
 #define FPGA_MAJOR_MODE_HF_SIMULATOR                           (2<<5)
 #define FPGA_MAJOR_MODE_HF_ISO14443A                           (3<<5)

+#define FPGA_MAJOR_MODE_HF_SNOOP                                   (4<<5)

 // BOTH
 #define FPGA_MAJOR_MODE_OFF                                                    (7<<5)
 // Options for LF_ADC
 // BOTH
 #define FPGA_MAJOR_MODE_OFF                                                    (7<<5)
 // Options for LF_ADC


@@ -62,6 +64,7 @@ void SetAdcMuxFor(uint32_t whichGpio);
 #define FPGA_HF_SIMULATOR_MODULATE_212K                                (2<<0)
 #define FPGA_HF_SIMULATOR_MODULATE_424K                                (4<<0)
 #define FPGA_HF_SIMULATOR_MODULATE_424K_8BIT           0x5//101
 #define FPGA_HF_SIMULATOR_MODULATE_212K                                (2<<0)
 #define FPGA_HF_SIMULATOR_MODULATE_424K                                (4<<0)
 #define FPGA_HF_SIMULATOR_MODULATE_424K_8BIT           0x5//101

+//  no 848K 

 
 // Options for ISO14443A
 #define FPGA_HF_ISO14443A_SNIFFER                                      (0<<0)
 
 // Options for ISO14443A
 #define FPGA_HF_ISO14443A_SNIFFER                                      (0<<0)