Fixed some compile warnings in client, minor tidy up with some dbprintf statements

[proxmark3-svn] / fpga / hi_simulate.v

diff --git a/fpga/hi_simulate.v b/fpga/hi_simulate.v
index d0a711764abea2a729c3b2fb40d3bd3586fdff1d..05662e53aa3d830ff2e74a75dd36321e95096317 100644 (file)
--- a/fpga/hi_simulate.v
+++ b/fpga/hi_simulate.v
@@ -51,7 +51,8 @@ begin
 end\r
 \r
 // Divide 13.56 MHz by 32 to produce the SSP_CLK\r
 end\r
 \r
 // Divide 13.56 MHz by 32 to produce the SSP_CLK\r

-reg [4:0] ssp_clk_divider;\r
+// The register is bigger to allow higher division factors of up to /128\r
+reg [6:0] ssp_clk_divider;\r

 always @(posedge adc_clk)\r
     ssp_clk_divider <= (ssp_clk_divider + 1);\r
 assign ssp_clk = ssp_clk_divider[4];\r
 always @(posedge adc_clk)\r
     ssp_clk_divider <= (ssp_clk_divider + 1);\r
 assign ssp_clk = ssp_clk_divider[4];\r


@@ -87,6 +88,8 @@ always @(mod_type or ssp_clk or ssp_dout)
         modulating_carrier <= 1'b0;                          // no modulation\r
     else if(mod_type == 3'b001)\r
         modulating_carrier <= ssp_dout ^ ssp_clk_divider[3]; // XOR means BPSK\r
         modulating_carrier <= 1'b0;                          // no modulation\r
     else if(mod_type == 3'b001)\r
         modulating_carrier <= ssp_dout ^ ssp_clk_divider[3]; // XOR means BPSK\r

+    else if(mod_type == 3'b010)\r
+        modulating_carrier <= ssp_dout & ssp_clk_divider[5]; // switch 212kHz subcarrier on/off\r

     else\r
         modulating_carrier <= 1'b0;                           // yet unused\r
 \r
     else\r
         modulating_carrier <= 1'b0;                           // yet unused\r
 \r