Merge pull request #98 from marshmellow42/master

[proxmark3-svn] / fpga / util.v

diff --git a/fpga/util.v b/fpga/util.v
index c500edb4c6b03b0be3d9b591db82645d3ba80c46..0842ac64f4a7f7f786aea047bc31c9fe0dd8e053 100644 (file)
--- a/fpga/util.v
+++ b/fpga/util.v
@@ -1,27 +1,27 @@
-//-----------------------------------------------------------------------------\r
-// General-purpose miscellany.\r
-//\r
-// Jonathan Westhues, April 2006.\r
-//-----------------------------------------------------------------------------\r
-\r
-module mux8(sel, y, x0, x1, x2, x3, x4, x5, x6, x7);\r
-    input [2:0] sel;\r
-    input x0, x1, x2, x3, x4, x5, x6, x7;\r
-    output y;\r
-    reg y;\r
-\r
-always @(x0 or x1 or x2 or x3 or x4 or x5 or x6 or x7 or sel)\r
-begin\r
-    case (sel)\r
-        3'b000: y = x0;\r
-        3'b001: y = x1;\r
-        3'b010: y = x2;\r
-        3'b011: y = x3;\r
-        3'b100: y = x4;\r
-        3'b101: y = x5;\r
-        3'b110: y = x6;\r
-        3'b111: y = x7;\r
-    endcase\r
-end\r
-\r
-endmodule\r
+//-----------------------------------------------------------------------------
+// General-purpose miscellany.
+//
+// Jonathan Westhues, April 2006.
+//-----------------------------------------------------------------------------
+
+module mux8(sel, y, x0, x1, x2, x3, x4, x5, x6, x7);
+    input [2:0] sel;
+    input x0, x1, x2, x3, x4, x5, x6, x7;
+    output y;
+    reg y;
+
+always @(x0 or x1 or x2 or x3 or x4 or x5 or x6 or x7 or sel)
+begin
+    case (sel)
+        3'b000: y = x0;
+        3'b001: y = x1;
+        3'b010: y = x2;
+        3'b011: y = x3;
+        3'b100: y = x4;
+        3'b101: y = x5;
+        3'b110: y = x6;
+        3'b111: y = x7;
+    endcase
+end
+
+endmodule