fix 'data load' filename pointer

[proxmark3-svn] / fpga / testbed_lo_read.v

diff --git a/fpga/testbed_lo_read.v b/fpga/testbed_lo_read.v
index 11908d77a824efb30d55ba29cc12dbf617bb2488..cb0f119c937684e810101c14e2b203b1cf593446 100644 (file)
--- a/fpga/testbed_lo_read.v
+++ b/fpga/testbed_lo_read.v
@@ -1,5 +1,4 @@
 `include "lo_read.v"\r
 `include "lo_read.v"\r

-\r

 /*\r
        pck0                    - input main 24Mhz clock (PLL / 4)\r
        [7:0] adc_d             - input data from A/D converter\r
 /*\r
        pck0                    - input main 24Mhz clock (PLL / 4)\r
        [7:0] adc_d             - input data from A/D converter\r


@@ -29,6 +28,7 @@ module testbed_lo_read;
        reg  pck0;\r
        reg  [7:0] adc_d;\r
        reg  lo_is_125khz;\r
        reg  pck0;\r
        reg  [7:0] adc_d;\r
        reg  lo_is_125khz;\r

+       reg [15:0] divisor;\r

 \r
        wire pwr_lo;\r
        wire adc_clk;\r
 \r
        wire pwr_lo;\r
        wire adc_clk;\r


@@ -37,7 +37,7 @@ module testbed_lo_read;
        wire ssp_frame;\r
        wire ssp_din;\r
        wire ssp_clk;\r
        wire ssp_frame;\r
        wire ssp_din;\r
        wire ssp_clk;\r

-       wire ssp_dout;\r
+       reg ssp_dout;\r

        wire pwr_hi;\r
        wire pwr_oe1;\r
        wire pwr_oe2;\r
        wire pwr_hi;\r
        wire pwr_oe1;\r
        wire pwr_oe2;\r


@@ -47,7 +47,7 @@ module testbed_lo_read;
        wire cross_hi;\r
        wire dbg;\r
 \r
        wire cross_hi;\r
        wire dbg;\r
 \r

-       lo_read #(5,200) dut(\r
+       lo_read #(5,10) dut(\r

        .pck0(pck0),\r
        .ck_1356meg(ck_1356meg),\r
        .ck_1356megb(ck_1356megb),\r
        .pck0(pck0),\r
        .ck_1356meg(ck_1356meg),\r
        .ck_1356megb(ck_1356megb),\r


@@ -66,19 +66,20 @@ module testbed_lo_read;
        .cross_hi(cross_hi),\r
        .cross_lo(cross_lo),\r
        .dbg(dbg),\r
        .cross_hi(cross_hi),\r
        .cross_lo(cross_lo),\r
        .dbg(dbg),\r

-       .lo_is_125khz(lo_is_125khz)\r
+       .lo_is_125khz(lo_is_125khz),\r
+       .divisor(divisor)\r

        );\r
 \r
        );\r
 \r

-       integer idx, i;\r
+       integer idx, i, adc_val=8;\r

 \r
        // main clock\r
        always #5 pck0 = !pck0;\r
 \r
 \r
        // main clock\r
        always #5 pck0 = !pck0;\r
 \r

-       //new A/D value available from ADC on positive edge\r

        task crank_dut;\r
        begin\r
                @(posedge adc_clk) ;\r
        task crank_dut;\r
        begin\r
                @(posedge adc_clk) ;\r

-               adc_d = $random;\r
+               adc_d = adc_val;\r
+               adc_val = (adc_val *2) + 53;\r

        end\r
        endtask\r
 \r
        end\r
        endtask\r
 \r


@@ -87,19 +88,14 @@ module testbed_lo_read;
                // init inputs\r
                pck0 = 0;\r
                adc_d = 0;\r
                // init inputs\r
                pck0 = 0;\r
                adc_d = 0;\r

-\r
-               // simulate 4 A/D cycles at 134Khz\r
-               lo_is_125khz=0;\r
-               for (i = 0 ;  i < 4 ;  i = i + 1) begin\r
-                       crank_dut;\r
-               end\r
+               ssp_dout = 0;\r
+               lo_is_125khz = 1;\r
+               divisor = 255;  //min 16, 95=125Khz, max 255\r

 \r
                // simulate 4 A/D cycles at 125Khz\r
 \r
                // simulate 4 A/D cycles at 125Khz\r

-               lo_is_125khz=1;\r
-               for (i = 0 ;  i < 4 ;  i = i + 1) begin\r
+               for (i = 0 ;  i < 8 ;  i = i + 1) begin\r

                        crank_dut;\r
                end\r
                $finish;\r
        end\r
                        crank_dut;\r
                end\r
                $finish;\r
        end\r

-       \r

 endmodule // main\r
 endmodule // main\r