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[proxmark3-svn] / armsrc / appmain.c

diff --git a/armsrc/appmain.c b/armsrc/appmain.c
index 303127548619488912b0eabd96cb9ac75582b3d2..18b8d64a6b10e1e32fd25c4d71d51d5c492b0121 100644 (file)
--- a/armsrc/appmain.c
+++ b/armsrc/appmain.c
@@ -4,10 +4,14 @@
 // Jonathan Westhues, Mar 2006\r
 // Edits by Gerhard de Koning Gans, Sep 2007 (##)\r
 //-----------------------------------------------------------------------------\r
 // Jonathan Westhues, Mar 2006\r
 // Edits by Gerhard de Koning Gans, Sep 2007 (##)\r
 //-----------------------------------------------------------------------------\r

+\r
+\r

 #include <proxmark3.h>\r
 #include "apps.h"\r
 #include <proxmark3.h>\r
 #include "apps.h"\r

+#ifdef WITH_LCD\r

 #include "fonts.h"\r
 #include "LCD.h"\r
 #include "fonts.h"\r
 #include "LCD.h"\r

+#endif\r

 \r
 // The large multi-purpose buffer, typically used to hold A/D samples,\r
 // maybe pre-processed in some way.\r
 \r
 // The large multi-purpose buffer, typically used to hold A/D samples,\r
 // maybe pre-processed in some way.\r


@@ -87,8 +91,10 @@ void AcquireRawAdcSamples125k(BOOL at134khz)
        memset(dest,0,n);\r
 \r
        if(at134khz) {\r
        memset(dest,0,n);\r
 \r
        if(at134khz) {\r

+               FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r

                FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | FPGA_LF_READER_USE_134_KHZ);\r
        } else {\r
                FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | FPGA_LF_READER_USE_134_KHZ);\r
        } else {\r

+               FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r

                FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | FPGA_LF_READER_USE_125_KHZ);\r
        }\r
 \r
                FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | FPGA_LF_READER_USE_125_KHZ);\r
        }\r
 \r


@@ -121,7 +127,7 @@ void AcquireRawAdcSamples125k(BOOL at134khz)
 \r
 //-----------------------------------------------------------------------------\r
 // Read an ADC channel and block till it completes, then return the result\r
 \r
 //-----------------------------------------------------------------------------\r
 // Read an ADC channel and block till it completes, then return the result\r

-// in ADC units (0 to 1023). Also a routine to average sixteen samples and\r
+// in ADC units (0 to 1023). Also a routine to average 32 samples and\r

 // return that.\r
 //-----------------------------------------------------------------------------\r
 static int ReadAdc(int ch)\r
 // return that.\r
 //-----------------------------------------------------------------------------\r
 static int ReadAdc(int ch)\r


@@ -152,6 +158,29 @@ static int AvgAdc(int ch)
 \r
        return (a + 15) >> 5;\r
 }\r
 \r
        return (a + 15) >> 5;\r
 }\r

+
+/*
+ * Sweeps the useful LF range of the proxmark from
+ * 46.8kHz (divisor=255) to 600kHz (divisor=19) and
+ * reads the voltage in the antenna: the result is a graph
+ * which should clearly show the resonating frequency of your
+ * LF antenna ( hopefully around 90 if it is tuned to 125kHz!)
+ */\r
+void SweepLFrange()\r
+{\r
+       BYTE *dest = (BYTE *)BigBuf;\r
+       int i;\r
+\r
+       // clear buffer\r
+       memset(BigBuf,0,sizeof(BigBuf));\r
+\r
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
+       for (i=255; i>19; i--) {\r
+               FpgaSendCommand(FPGA_CMD_SET_DIVISOR, i);\r
+               SpinDelay(20);\r
+               dest[i] = (137500 * AvgAdc(4)) >> 18;\r
+       }\r
+}\r

 \r
 void MeasureAntennaTuning(void)\r
 {\r
 \r
 void MeasureAntennaTuning(void)\r
 {\r


@@ -164,6 +193,7 @@ void MeasureAntennaTuning(void)
        UsbCommand c;\r
 \r
        // Let the FPGA drive the low-frequency antenna around 125 kHz.\r
        UsbCommand c;\r
 \r
        // Let the FPGA drive the low-frequency antenna around 125 kHz.\r

+       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r

        FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | FPGA_LF_READER_USE_125_KHZ);\r
        SpinDelay(20);\r
        vLf125 = AvgAdc(4);\r
        FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | FPGA_LF_READER_USE_125_KHZ);\r
        SpinDelay(20);\r
        vLf125 = AvgAdc(4);\r


@@ -172,6 +202,7 @@ void MeasureAntennaTuning(void)
        vLf125 = (137500 * vLf125) >> 10;\r
 \r
        // Let the FPGA drive the low-frequency antenna around 134 kHz.\r
        vLf125 = (137500 * vLf125) >> 10;\r
 \r
        // Let the FPGA drive the low-frequency antenna around 134 kHz.\r

+       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r

        FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | FPGA_LF_READER_USE_134_KHZ);\r
        SpinDelay(20);\r
        vLf134 = AvgAdc(4);\r
        FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | FPGA_LF_READER_USE_134_KHZ);\r
        SpinDelay(20);\r
        vLf134 = AvgAdc(4);\r


@@ -207,7 +238,7 @@ void SimulateTagLowFrequency(int period)
        PIO_OUTPUT_DISABLE = (1 << GPIO_SSC_CLK);\r
 \r
 #define SHORT_COIL()   LOW(GPIO_SSC_DOUT)\r
        PIO_OUTPUT_DISABLE = (1 << GPIO_SSC_CLK);\r
 \r
 #define SHORT_COIL()   LOW(GPIO_SSC_DOUT)\r

-#define OPEN_COIL()            HIGH(GPIO_SSC_DOUT)\r
+#define OPEN_COIL()    HIGH(GPIO_SSC_DOUT)\r

 \r
        i = 0;\r
        for(;;) {\r
 \r
        i = 0;\r
        for(;;) {\r


@@ -345,6 +376,7 @@ static void CmdHIDdemodFSK(void)
        int m=0, n=0, i=0, idx=0, found=0, lastval=0;\r
        DWORD hi=0, lo=0;\r
 \r
        int m=0, n=0, i=0, idx=0, found=0, lastval=0;\r
        DWORD hi=0, lo=0;\r
 \r

+       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r

        FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | FPGA_LF_READER_USE_125_KHZ);\r
 \r
        // Connect the A/D to the peak-detected low-frequency path.\r
        FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | FPGA_LF_READER_USE_125_KHZ);\r
 \r
        // Connect the A/D to the peak-detected low-frequency path.\r


@@ -448,7 +480,7 @@ static void CmdHIDdemodFSK(void)
                                                dest[i++]=dest[idx-1];\r
                                                dest[i++]=dest[idx-1];\r
                                                break;\r
                                                dest[i++]=dest[idx-1];\r
                                                dest[i++]=dest[idx-1];\r
                                                break;\r

-                                       // When a logic 0 is immediately followed by the start of the next transmisson \r
+                                       // When a logic 0 is immediately followed by the start of the next transmisson\r

                                        // (special pattern) a pattern of 4 bit duration lengths is created.\r
                                        case 4:\r
                                                dest[i++]=dest[idx-1];\r
                                        // (special pattern) a pattern of 4 bit duration lengths is created.\r
                                        case 4:\r
                                                dest[i++]=dest[idx-1];\r


@@ -573,20 +605,23 @@ void UsbPacketReceived(BYTE *packet, int len)
                        break;\r
 \r
                case CMD_READER_ISO_15693:\r
                        break;\r
 \r
                case CMD_READER_ISO_15693:\r

-                       ReaderIso15693(c->ext1); \r
+                       ReaderIso15693(c->ext1);\r

                        break;\r
 \r
                case CMD_SIMTAG_ISO_15693:\r
                        break;\r
 \r
                case CMD_SIMTAG_ISO_15693:\r

-                       SimTagIso15693(c->ext1); \r
+                       SimTagIso15693(c->ext1);\r

                        break;\r
 \r
                        break;\r
 \r

-\r

                case CMD_ACQUIRE_RAW_ADC_SAMPLES_ISO_14443:\r
                        AcquireRawAdcSamplesIso14443(c->ext1);\r
                        break;\r
                case CMD_ACQUIRE_RAW_ADC_SAMPLES_ISO_14443:\r
                        AcquireRawAdcSamplesIso14443(c->ext1);\r
                        break;\r

+
+               case CMD_READ_SRI512_TAG:
+                       ReadSRI512Iso14443(c->ext1);
+                       break;

 \r
                case CMD_READER_ISO_14443a:\r
 \r
                case CMD_READER_ISO_14443a:\r

-                       ReaderIso14443a(c->ext1); \r
+                       ReaderIso14443a(c->ext1);\r

                        break;\r
 \r
                case CMD_SNOOP_ISO_14443:\r
                        break;\r
 \r
                case CMD_SNOOP_ISO_14443:\r


@@ -622,10 +657,9 @@ void UsbPacketReceived(BYTE *packet, int len)
                        break;\r
 \r
                case CMD_FPGA_MAJOR_MODE_OFF:           // ## FPGA Control\r
                        break;\r
 \r
                case CMD_FPGA_MAJOR_MODE_OFF:           // ## FPGA Control\r

-                       LED_C_ON();\r

                        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
                        SpinDelay(200);\r
                        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
                        SpinDelay(200);\r

-                       LED_C_OFF();\r
+                       LED_D_OFF(); // LED D indicates field ON or OFF\r

                        break;\r
 \r
                case CMD_DOWNLOAD_RAW_ADC_SAMPLES_125K:\r
                        break;\r
 \r
                case CMD_DOWNLOAD_RAW_ADC_SAMPLES_125K:\r


@@ -651,17 +685,26 @@ void UsbPacketReceived(BYTE *packet, int len)
                        SimulateTagLowFrequency(c->ext1);\r
                        LED_A_OFF();\r
                        break;\r
                        SimulateTagLowFrequency(c->ext1);\r
                        LED_A_OFF();\r
                        break;\r

-\r
+#ifdef WITH_LCD\r

                case CMD_LCD_RESET:\r
                        LCDReset();\r
                        break;\r
                case CMD_LCD_RESET:\r
                        LCDReset();\r
                        break;\r

+#endif\r
+               case CMD_SWEEP_LF:\r
+                       SweepLFrange();\r
+                       break;\r

 \r
 \r

+               case CMD_SET_LF_DIVISOR:\r
+                       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, c->ext1);\r
+                       break;\r
+#ifdef WITH_LCD\r

                case CMD_LCD:\r
                        LCDSend(c->ext1);\r
                        break;\r
                case CMD_LCD:\r
                        LCDSend(c->ext1);\r
                        break;\r

-\r
+#endif\r

         case CMD_SETUP_WRITE:\r
                case CMD_FINISH_WRITE:\r
         case CMD_SETUP_WRITE:\r
                case CMD_FINISH_WRITE:\r

+               case CMD_HARDWARE_RESET:\r

                        USB_D_PLUS_PULLUP_OFF();\r
                        SpinDelay(1000);\r
                        SpinDelay(1000);\r
                        USB_D_PLUS_PULLUP_OFF();\r
                        SpinDelay(1000);\r
                        SpinDelay(1000);\r


@@ -671,6 +714,7 @@ void UsbPacketReceived(BYTE *packet, int len)
                        }\r
                        break;\r
 \r
                        }\r
                        break;\r
 \r

+\r

                default:\r
                        DbpString("unknown command");\r
                        break;\r
                default:\r
                        DbpString("unknown command");\r
                        break;\r


@@ -706,6 +750,8 @@ void AppMain(void)
        // Load the FPGA image, which we have stored in our flash.\r
        FpgaDownloadAndGo();\r
 \r
        // Load the FPGA image, which we have stored in our flash.\r
        FpgaDownloadAndGo();\r
 \r

+#ifdef WITH_LCD\r
+\r

        LCDInit();\r
 \r
        // test text on different colored backgrounds\r
        LCDInit();\r
 \r
        // test text on different colored backgrounds\r


@@ -728,6 +774,8 @@ void AppMain(void)
        LCDFill(0, 1+8*14, 132, 8, CYAN);\r
        LCDFill(0, 1+8*15, 132, 8, MAGENTA);\r
 \r
        LCDFill(0, 1+8*14, 132, 8, CYAN);\r
        LCDFill(0, 1+8*15, 132, 8, MAGENTA);\r
 \r

+#endif\r
+\r

        for(;;) {\r
                UsbPoll(FALSE);\r
                WDT_HIT();\r
        for(;;) {\r
                UsbPoll(FALSE);\r
                WDT_HIT();\r