//-----------------------------------------------------------------------------\r
\r
`include "lo_read.v"\r
+`include "lo_passthru.v"\r
`include "lo_simulate.v"\r
`include "hi_read_tx.v"\r
`include "hi_read_rx_xcorr.v"\r
`include "util.v"\r
\r
module fpga(\r
- spck, miso, mosi, ncs,\r
+ spcki, miso, mosi, ncs,\r
pck0i, ck_1356meg, ck_1356megb,\r
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,\r
adc_d, adc_clk, adc_noe,\r
cross_hi, cross_lo,\r
dbg\r
);\r
- input spck, mosi, ncs;\r
+ input spcki, mosi, ncs;\r
output miso;\r
input pck0i, ck_1356meg, ck_1356megb;\r
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;\r
input cross_hi, cross_lo;\r
output dbg;\r
\r
+//assign pck0 = pck0i;\r
IBUFG #(.IOSTANDARD("DEFAULT") ) pck0b(\r
.O(pck0),\r
.I(pck0i)\r
);\r
-//assign pck0 = pck0i;\r
+//assign spck = spcki;\r
+ IBUFG #(.IOSTANDARD("DEFAULT") ) spckb(\r
+ .O(spck),\r
+ .I(spcki)\r
+ );\r
//-----------------------------------------------------------------------------\r
// The SPI receiver. This sets up the configuration word, which the rest of\r
// the logic looks at to determine how to connect the A/D and the coil\r
// to the configuration bits, for use below.\r
//-----------------------------------------------------------------------------\r
\r
-reg [7:0] conf_word_shift;\r
+reg [15:0] shift_reg;\r
+reg [7:0] divisor;\r
reg [7:0] conf_word;\r
\r
// We switch modes between transmitting to the 13.56 MHz tag and receiving\r
// glitching, or else we will glitch the transmitted carrier.\r
always @(posedge ncs)\r
begin\r
- conf_word <= conf_word_shift;\r
+ case(shift_reg[15:12])\r
+ 4'b0001: conf_word <= shift_reg[7:0];\r
+ 4'b0010: divisor <= shift_reg[7:0];\r
+ endcase\r
end\r
\r
always @(posedge spck)\r
begin\r
if(~ncs)\r
begin\r
- conf_word_shift[7:1] <= conf_word_shift[6:0];\r
- conf_word_shift[0] <= mosi;\r
+ shift_reg[15:1] <= shift_reg[14:0];\r
+ shift_reg[0] <= mosi;\r
end\r
end\r
\r
lr_ssp_frame, lr_ssp_din, ssp_dout, lr_ssp_clk,\r
cross_hi, cross_lo,\r
lr_dbg,\r
- lo_is_125khz\r
+ lo_is_125khz, divisor\r
+);\r
+\r
+lo_passthru lp(\r
+ pck0, ck_1356meg, ck_1356megb,\r
+ lp_pwr_lo, lp_pwr_hi, lp_pwr_oe1, lp_pwr_oe2, lp_pwr_oe3, lp_pwr_oe4,\r
+ adc_d, lp_adc_clk,\r
+ lp_ssp_frame, lp_ssp_din, ssp_dout, lp_ssp_clk,\r
+ cross_hi, cross_lo,\r
+ lp_dbg, divisor\r
);\r
\r
lo_simulate ls(\r
adc_d, ls_adc_clk,\r
ls_ssp_frame, ls_ssp_din, ssp_dout, ls_ssp_clk,\r
cross_hi, cross_lo,\r
- ls_dbg\r
+ ls_dbg, divisor\r
);\r
\r
hi_read_tx ht(\r
// 011 -- HF reader, receiving from tag, correlating as it goes; frequency selectable\r
// 100 -- HF simulated tag\r
// 101 -- HF ISO14443-A\r
-// 110 -- unused\r
+// 110 -- LF passthrough\r
// 111 -- everything off\r
\r
-mux8 mux_ssp_clk (major_mode, ssp_clk, lr_ssp_clk, ls_ssp_clk, ht_ssp_clk, hrxc_ssp_clk, hs_ssp_clk, hisn_ssp_clk, 1'b0, 1'b0);\r
-mux8 mux_ssp_din (major_mode, ssp_din, lr_ssp_din, ls_ssp_din, ht_ssp_din, hrxc_ssp_din, hs_ssp_din, hisn_ssp_din, 1'b0, 1'b0);\r
-mux8 mux_ssp_frame (major_mode, ssp_frame, lr_ssp_frame, ls_ssp_frame, ht_ssp_frame, hrxc_ssp_frame, hs_ssp_frame, hisn_ssp_frame, 1'b0, 1'b0);\r
-mux8 mux_pwr_oe1 (major_mode, pwr_oe1, lr_pwr_oe1, ls_pwr_oe1, ht_pwr_oe1, hrxc_pwr_oe1, hs_pwr_oe1, hisn_pwr_oe1, 1'b0, 1'b0);\r
-mux8 mux_pwr_oe2 (major_mode, pwr_oe2, lr_pwr_oe2, ls_pwr_oe2, ht_pwr_oe2, hrxc_pwr_oe2, hs_pwr_oe2, hisn_pwr_oe2, 1'b0, 1'b0);\r
-mux8 mux_pwr_oe3 (major_mode, pwr_oe3, lr_pwr_oe3, ls_pwr_oe3, ht_pwr_oe3, hrxc_pwr_oe3, hs_pwr_oe3, hisn_pwr_oe3, 1'b0, 1'b0);\r
-mux8 mux_pwr_oe4 (major_mode, pwr_oe4, lr_pwr_oe4, ls_pwr_oe4, ht_pwr_oe4, hrxc_pwr_oe4, hs_pwr_oe4, hisn_pwr_oe4, 1'b0, 1'b0);\r
-mux8 mux_pwr_lo (major_mode, pwr_lo, lr_pwr_lo, ls_pwr_lo, ht_pwr_lo, hrxc_pwr_lo, hs_pwr_lo, hisn_pwr_lo, 1'b0, 1'b0);\r
-mux8 mux_pwr_hi (major_mode, pwr_hi, lr_pwr_hi, ls_pwr_hi, ht_pwr_hi, hrxc_pwr_hi, hs_pwr_hi, hisn_pwr_hi, 1'b0, 1'b0);\r
-mux8 mux_adc_clk (major_mode, adc_clk, lr_adc_clk, ls_adc_clk, ht_adc_clk, hrxc_adc_clk, hs_adc_clk, hisn_adc_clk, 1'b0, 1'b0);\r
-mux8 mux_dbg (major_mode, dbg, lr_dbg, ls_dbg, ht_dbg, hrxc_dbg, hs_dbg, hisn_dbg, 1'b0, 1'b0);\r
+mux8 mux_ssp_clk (major_mode, ssp_clk, lr_ssp_clk, ls_ssp_clk, ht_ssp_clk, hrxc_ssp_clk, hs_ssp_clk, hisn_ssp_clk, lp_ssp_clk, 1'b0);\r
+mux8 mux_ssp_din (major_mode, ssp_din, lr_ssp_din, ls_ssp_din, ht_ssp_din, hrxc_ssp_din, hs_ssp_din, hisn_ssp_din, lp_ssp_din, 1'b0);\r
+mux8 mux_ssp_frame (major_mode, ssp_frame, lr_ssp_frame, ls_ssp_frame, ht_ssp_frame, hrxc_ssp_frame, hs_ssp_frame, hisn_ssp_frame, lp_ssp_frame, 1'b0);\r
+mux8 mux_pwr_oe1 (major_mode, pwr_oe1, lr_pwr_oe1, ls_pwr_oe1, ht_pwr_oe1, hrxc_pwr_oe1, hs_pwr_oe1, hisn_pwr_oe1, lp_pwr_oe1, 1'b0);\r
+mux8 mux_pwr_oe2 (major_mode, pwr_oe2, lr_pwr_oe2, ls_pwr_oe2, ht_pwr_oe2, hrxc_pwr_oe2, hs_pwr_oe2, hisn_pwr_oe2, lp_pwr_oe2, 1'b0);\r
+mux8 mux_pwr_oe3 (major_mode, pwr_oe3, lr_pwr_oe3, ls_pwr_oe3, ht_pwr_oe3, hrxc_pwr_oe3, hs_pwr_oe3, hisn_pwr_oe3, lp_pwr_oe3, 1'b0);\r
+mux8 mux_pwr_oe4 (major_mode, pwr_oe4, lr_pwr_oe4, ls_pwr_oe4, ht_pwr_oe4, hrxc_pwr_oe4, hs_pwr_oe4, hisn_pwr_oe4, lp_pwr_oe4, 1'b0);\r
+mux8 mux_pwr_lo (major_mode, pwr_lo, lr_pwr_lo, ls_pwr_lo, ht_pwr_lo, hrxc_pwr_lo, hs_pwr_lo, hisn_pwr_lo, lp_pwr_lo, 1'b0);\r
+mux8 mux_pwr_hi (major_mode, pwr_hi, lr_pwr_hi, ls_pwr_hi, ht_pwr_hi, hrxc_pwr_hi, hs_pwr_hi, hisn_pwr_hi, lp_pwr_hi, 1'b0);\r
+mux8 mux_adc_clk (major_mode, adc_clk, lr_adc_clk, ls_adc_clk, ht_adc_clk, hrxc_adc_clk, hs_adc_clk, hisn_adc_clk, lp_adc_clk, 1'b0);\r
+mux8 mux_dbg (major_mode, dbg, lr_dbg, ls_dbg, ht_dbg, hrxc_dbg, hs_dbg, hisn_dbg, lp_dbg, 1'b0);\r
\r
// In all modes, let the ADC's outputs be enabled.\r
assign adc_noe = 1'b0;\r
projects / proxmark3-svn / blobdiff