end\r
\r
// Divide 13.56 MHz by 32 to produce the SSP_CLK\r
-reg [4:0] ssp_clk_divider;\r
+// The register is bigger to allow higher division factors of up to /128\r
+reg [6:0] ssp_clk_divider;\r
always @(posedge adc_clk)\r
ssp_clk_divider <= (ssp_clk_divider + 1);\r
assign ssp_clk = ssp_clk_divider[4];\r
modulating_carrier <= 1'b0; // no modulation\r
else if(mod_type == 3'b001)\r
modulating_carrier <= ssp_dout ^ ssp_clk_divider[3]; // XOR means BPSK\r
+ else if(mod_type == 3'b010)\r
+ modulating_carrier <= ssp_dout & ssp_clk_divider[5]; // switch 212kHz subcarrier on/off\r
else\r
modulating_carrier <= 1'b0; // yet unused\r
\r