//-----------------------------------------------------------------------------
void RAMFUNC SnoopIClass(void)
{
-
-
// We won't start recording the frames that we acquire until we trigger;
// a good trigger condition to get started is probably when we see a
// response from the tag.
// The DMA buffer, used to stream samples from the FPGA
uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
- set_tracing(TRUE);
clear_trace();
+ set_tracing(TRUE);
+
iso14a_set_trigger(FALSE);
int lastRxCounter;
FpgaSetupSsc();
upTo = dmaBuf;
lastRxCounter = DMA_BUFFER_SIZE;
- FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE);
+ // Setup and start DMA.
+ if ( !FpgaSetupSscDma((uint8_t*) dmaBuf, DMA_BUFFER_SIZE) ){
+ if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting");
+ return;
+ }
// And the reader -> tag commands
memset(&Uart, 0, sizeof(Uart));
for(;;) {
LED_A_ON();
WDT_HIT();
- int behindBy = (lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR) &
- (DMA_BUFFER_SIZE-1);
- if(behindBy > maxBehindBy) {
+ int behindBy = (lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR) & (DMA_BUFFER_SIZE-1);
+
+ if ( behindBy > maxBehindBy) {
maxBehindBy = behindBy;
- if(behindBy > (9 * DMA_BUFFER_SIZE / 10)) {
+ if ( behindBy > (9 * DMA_BUFFER_SIZE / 10)) {
Dbprintf("blew circular buffer! behindBy=0x%x", behindBy);
goto done;
}
}
- if(behindBy < 1) continue;
+ if( behindBy < 1) continue;
- LED_A_OFF();
+ LED_A_OFF();
smpl = upTo[0];
upTo++;
lastRxCounter -= 1;
- if(upTo - dmaBuf > DMA_BUFFER_SIZE) {
+ if (upTo - dmaBuf > DMA_BUFFER_SIZE) {
upTo -= DMA_BUFFER_SIZE;
lastRxCounter += DMA_BUFFER_SIZE;
AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo;
}
//samples += 4;
- samples += 1;
+ samples += 1;
- if(smpl & 0xF) {
- decbyte ^= (1 << (3 - div));
- }
+ if(smpl & 0xF)
+ decbyte ^= (1 << (3 - div));
+
- // FOR READER SIDE COMMUMICATION...
+ // FOR READER SIDE COMMUMICATION...
- decbyter <<= 2;
- decbyter ^= (smpl & 0x30);
+ decbyter <<= 2;
+ decbyter ^= (smpl & 0x30);
- div++;
+ ++div;
- if((div + 1) % 2 == 0) {
- smpl = decbyter;
- if(OutOfNDecoding((smpl & 0xF0) >> 4)) {
- rsamples = samples - Uart.samples;
- time_stop = (GetCountSspClk()-time_0) << 4;
- LED_C_ON();
-
- //if(!LogTrace(Uart.output,Uart.byteCnt, rsamples, Uart.parityBits,TRUE)) break;
- //if(!LogTrace(NULL, 0, Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER, 0, TRUE)) break;
- if(tracing) {
- uint8_t parity[MAX_PARITY_SIZE];
- GetParity(Uart.output, Uart.byteCnt, parity);
- LogTrace(Uart.output,Uart.byteCnt, time_start, time_stop, parity, TRUE);
- }
-
+ if (( div + 1) % 2 == 0) {
+ smpl = decbyter;
+ if ( OutOfNDecoding((smpl & 0xF0) >> 4)) {
+ rsamples = samples - Uart.samples;
+ time_stop = (GetCountSspClk()-time_0) << 4;
+ LED_C_ON();
+
+ //if(!LogTrace(Uart.output,Uart.byteCnt, rsamples, Uart.parityBits,TRUE)) break;
+ //if(!LogTrace(NULL, 0, Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER, 0, TRUE)) break;
+ if(tracing) {
+ uint8_t parity[MAX_PARITY_SIZE];
+ GetParity(Uart.output, Uart.byteCnt, parity);
+ LogTrace(Uart.output,Uart.byteCnt, time_start, time_stop, parity, TRUE);
+ }
- /* And ready to receive another command. */
- Uart.state = STATE_UNSYNCD;
- /* And also reset the demod code, which might have been */
- /* false-triggered by the commands from the reader. */
- Demod.state = DEMOD_UNSYNCD;
- LED_B_OFF();
- Uart.byteCnt = 0;
- }else{
- time_start = (GetCountSspClk()-time_0) << 4;
+ /* And ready to receive another command. */
+ Uart.state = STATE_UNSYNCD;
+ /* And also reset the demod code, which might have been */
+ /* false-triggered by the commands from the reader. */
+ Demod.state = DEMOD_UNSYNCD;
+ LED_B_OFF();
+ Uart.byteCnt = 0;
+ } else {
+ time_start = (GetCountSspClk()-time_0) << 4;
+ }
+ decbyter = 0;
}
- decbyter = 0;
- }
- if(div > 3) {
- smpl = decbyte;
- if(ManchesterDecoding(smpl & 0x0F)) {
- time_stop = (GetCountSspClk()-time_0) << 4;
+ if(div > 3) {
+ smpl = decbyte;
+ if(ManchesterDecoding(smpl & 0x0F)) {
+ time_stop = (GetCountSspClk()-time_0) << 4;
- rsamples = samples - Demod.samples;
- LED_B_ON();
+ rsamples = samples - Demod.samples;
+ LED_B_ON();
- if(tracing) {
- uint8_t parity[MAX_PARITY_SIZE];
- GetParity(Demod.output, Demod.len, parity);
- LogTrace(Demod.output, Demod.len, time_start, time_stop, parity, FALSE);
- }
+ if(tracing) {
+ uint8_t parity[MAX_PARITY_SIZE];
+ GetParity(Demod.output, Demod.len, parity);
+ LogTrace(Demod.output, Demod.len, time_start, time_stop, parity, FALSE);
+ }
- // And ready to receive another response.
- memset(&Demod, 0, sizeof(Demod));
- Demod.output = tagToReaderResponse;
- Demod.state = DEMOD_UNSYNCD;
- LED_C_OFF();
- }else{
- time_start = (GetCountSspClk()-time_0) << 4;
+ // And ready to receive another response.
+ memset(&Demod, 0, sizeof(Demod));
+ Demod.output = tagToReaderResponse;
+ Demod.state = DEMOD_UNSYNCD;
+ LED_C_OFF();
+ } else {
+ time_start = (GetCountSspClk()-time_0) << 4;
+ }
+
+ div = 0;
+ decbyte = 0x00;
}
-
- div = 0;
- decbyte = 0x00;
- }
- //}
- if(BUTTON_PRESS()) {
+ if (BUTTON_PRESS()) {
DbpString("cancelled_a");
goto done;
}
Dbprintf("%x %x %x", Uart.byteCntMax, BigBuf_get_traceLen(), (int)Uart.output[0]);
done:
- AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;
+ FpgaDisableSscDma();
Dbprintf("%x %x %x", maxBehindBy, Uart.state, Uart.byteCnt);
Dbprintf("%x %x %x", Uart.byteCntMax, BigBuf_get_traceLen(), (int)Uart.output[0]);
- LED_A_OFF();
- LED_B_OFF();
- LED_C_OFF();
- LED_D_OFF();
+ LEDsoff();
set_tracing(FALSE);
}
void rotateCSN(uint8_t* originalCSN, uint8_t* rotatedCSN) {
int i;
- for(i = 0; i < 8; i++) {
+ for(i = 0; i < 8; i++)
rotatedCSN[i] = (originalCSN[i] >> 3) | (originalCSN[(i+1)%8] << 5);
- }
}
//-----------------------------------------------------------------------------
* The mode FPGA_HF_SIMULATOR_MODULATE_424K_8BIT which we use to simulate tag,
* works like this.
* - A 1-bit input to the FPGA becomes 8 pulses on 423.5kHz (fc/32) (18.88us).
- * - A 0-bit inptu to the FPGA becomes an unmodulated time of 18.88us
+ * - A 0-bit input to the FPGA becomes an unmodulated time of 18.88us
*
* In this mode the SOF can be written as 00011101 = 0x1D
* The EOF can be written as 10111000 = 0xb8
FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
// Enable and clear the trace
- set_tracing(TRUE);
clear_trace();
+ set_tracing(TRUE);
+
//Use the emulator memory for SIM
uint8_t *emulator = BigBuf_get_EM_addr();
receivedCmd[3], receivedCmd[4], receivedCmd[5],
receivedCmd[6], receivedCmd[7], receivedCmd[8]);
// Do not respond
- modulated_response = resp_sof; modulated_response_size = 0; //order = 0;
+ modulated_response = resp_sof;
+ modulated_response_size = 0; //order = 0;
trace_data = NULL;
trace_data_size = 0;
}
GetParity(trace_data, trace_data_size, parity);
LogTrace(trace_data, trace_data_size, (t2r_time-time_0) << 4, (t2r_time-time_0) << 4, parity, FALSE);
}
- if(!tracing) {
+ if(!tracing)
DbpString("Trace full");
- //break;
- }
}
}
- //Dbprintf("%x", cmdsRecvd);
- LED_A_OFF();
- LED_B_OFF();
- LED_C_OFF();
-
+ LEDsoff();
+
if(buttonPressed)
- {
DbpString("Button pressed");
- }
+
return buttonPressed;
}
//-----------------------------------------------------------------------------
static void TransmitIClassCommand(const uint8_t *cmd, int len, int *samples, int *wait)
{
- int c;
- FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
- AT91C_BASE_SSC->SSC_THR = 0x00;
- FpgaSetupSsc();
-
- if (wait)
- {
- if(*wait < 10) *wait = 10;
-
- for(c = 0; c < *wait;) {
- if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
- AT91C_BASE_SSC->SSC_THR = 0x00; // For exact timing!
- c++;
- }
- if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
- volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
- (void)r;
- }
- WDT_HIT();
- }
+ int c;
+ volatile uint32_t r;
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
+ AT91C_BASE_SSC->SSC_THR = 0x00;
+ FpgaSetupSsc();
- }
+ if (wait) {
+ if(*wait < 10) *wait = 10;
+ for(c = 0; c < *wait;) {
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
+ AT91C_BASE_SSC->SSC_THR = 0x00; // For exact timing!
+ c++;
+ }
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
+ r = AT91C_BASE_SSC->SSC_RHR;
+ (void)r;
+ }
+ WDT_HIT();
+ }
+ }
- uint8_t sendbyte;
- bool firstpart = TRUE;
- c = 0;
- for(;;) {
- if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
- // DOUBLE THE SAMPLES!
- if(firstpart) {
- sendbyte = (cmd[c] & 0xf0) | (cmd[c] >> 4);
- }
- else {
- sendbyte = (cmd[c] & 0x0f) | (cmd[c] << 4);
- c++;
- }
- if(sendbyte == 0xff) {
- sendbyte = 0xfe;
- }
- AT91C_BASE_SSC->SSC_THR = sendbyte;
- firstpart = !firstpart;
+ uint8_t sendbyte;
+ bool firstpart = TRUE;
+ c = 0;
+ for(;;) {
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
- if(c >= len) {
- break;
- }
- }
- if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
- volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
- (void)r;
- }
- WDT_HIT();
- }
- if (samples) *samples = (c + *wait) << 3;
-}
+ // DOUBLE THE SAMPLES!
+ if(firstpart) {
+ sendbyte = (cmd[c] & 0xf0) | (cmd[c] >> 4);
+ }
+ else {
+ sendbyte = (cmd[c] & 0x0f) | (cmd[c] << 4);
+ c++;
+ }
+
+ if(sendbyte == 0xff)
+ sendbyte = 0xfe;
+ AT91C_BASE_SSC->SSC_THR = sendbyte;
+ firstpart = !firstpart;
+
+ if(c >= len) break;
+
+ }
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
+ r = AT91C_BASE_SSC->SSC_RHR;
+ (void)r;
+ }
+
+ WDT_HIT();
+ }
+ if (samples && wait) *samples = (c + *wait) << 3;
+}
//-----------------------------------------------------------------------------
// Prepare iClass reader command to send to FPGA
if (elapsed) (*elapsed)++;
}
if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
- if(c < timeout) { c++; } else { return FALSE; }
+ if(c < timeout)
+ c++;
+ else
+ return FALSE;
+
b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
+
skip = !skip;
+
if(skip) continue;
if(ManchesterDecoding(b & 0x0f)) {
{
FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
// Reset trace buffer
- set_tracing(TRUE);
clear_trace();
-
+ set_tracing(TRUE);
+
// Setup SSC
FpgaSetupSsc();
// Start from off (no field generated)
while(!BUTTON_PRESS())
{
if (try_once && tryCnt > 5) break;
+
tryCnt++;
+
if(!tracing) {
DbpString("Trace full");
break;
projects / proxmark3-svn / blobdiff