always @(posedge clk)
begin
case (state)
- 0:
+ 0: // initialize
begin
if (cur_max_val >= ({1'b0, adc_d} + threshold))
state <= 2;
else if (adc_d <= cur_min_val)
cur_min_val <= adc_d;
end
- 1:
+ 1: // high phase
begin
if (cur_max_val <= adc_d)
cur_max_val <= adc_d;
max_val <= cur_max_val;
end
end
- 2:
+ 2: // low phase
begin
if (adc_d <= cur_min_val)
cur_min_val <= adc_d;