+static void CodeIso14443bAsTag(const uint8_t *cmd, int len) {
+ /* ISO 14443 B
+ *
+ * Reader to card | ASK - Amplitude Shift Keying Modulation (PCD to PICC for Type B) (NRZ-L encodig)
+ * Card to reader | BPSK - Binary Phase Shift Keying Modulation, (PICC to PCD for Type B)
+ *
+ * fc - carrier frequency 13.56mHz
+ * TR0 - Guard Time per 14443-2
+ * TR1 - Synchronization Time per 14443-2
+ * TR2 - PICC to PCD Frame Delay Time (per 14443-3 Amendment 1)
+ *
+ * Elementary Time Unit (ETU) is
+ * - 128 Carrier Cycles (9.4395 µS) = 8 Subcarrier Units
+ * - 1 ETU = 1 bit
+ * - 10 ETU = 1 startbit, 8 databits, 1 stopbit (10bits length)
+ * - startbit is a 0
+ * - stopbit is a 1
+ *
+ * Start of frame (SOF) is
+ * - [10-11] ETU of ZEROS, unmodulated time
+ * - [2-3] ETU of ONES,
+ *
+ * End of frame (EOF) is
+ * - [10-11] ETU of ZEROS, unmodulated time
+ *
+ * -TO VERIFY THIS BELOW-
+ * The mode FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_BPSK which we use to simulate tag
+ * works like this:
+ * - A 1-bit input to the FPGA becomes 8 pulses at 847.5kHz (9.44µS)
+ * - A 0-bit input to the FPGA becomes an unmodulated time of 9.44µS
+ *
+ *
+ *
+ * Card sends data ub 847.e kHz subcarrier
+ * 848k = 9.44µS = 128 fc
+ * 424k = 18.88µS = 256 fc
+ * 212k = 37.76µS = 512 fc
+ * 106k = 75.52µS = 1024 fc
+ *
+ * Reader data transmission:
+ * - no modulation ONES
+ * - SOF
+ * - Command, data and CRC_B
+ * - EOF
+ * - no modulation ONES
+ *
+ * Card data transmission
+ * - TR1
+ * - SOF
+ * - data (each bytes is: 1startbit, 8bits, 1stopbit)
+ * - CRC_B
+ * - EOF
+ *
+ * FPGA implementation :
+ * At this point only Type A is implemented. This means that we are using a
+ * bit rate of 106 kbit/s, or fc/128. Oversample by 4, which ought to make
+ * things practical for the ARM (fc/32, 423.8 kbits/s, ~50 kbytes/s)
+ *
+ */
+
+ int i,j;
+ uint8_t b;
+