// use lf config settings
sample_config *sc = getSamplingConfig();
- // clear read buffer
- BigBuf_Clear_keep_EM();
- /* Make sure the tag is reset */
+ // Make sure the tag is reset
FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
WaitMS(2500);
+ // clear read buffer (after fpga bitstream loaded...)
+ BigBuf_Clear_keep_EM();
+
// power on
LFSetupFPGAForADC(sc->divisor, 1);
uint8_t wavesPerClock = clock/fc;
uint8_t mod = clock % fc; //modifier
uint8_t modAdj = fc/mod; //how often to apply modifier
- bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=TRUE;
+ bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=true;
// loop through clock - step field clock
for (uint8_t idx=0; idx < wavesPerClock; idx++){
// put 1/2 FC length 1's and 1/2 0's per field clock wave (to create the wave)
for (i=0; i<size; i++){
if (BitStream[i] == curPhase){
- pskSimBit(carrier, &n, clk, &curPhase, FALSE);
+ pskSimBit(carrier, &n, clk, &curPhase, false);
} else {
- pskSimBit(carrier, &n, clk, &curPhase, TRUE);
+ pskSimBit(carrier, &n, clk, &curPhase, true);
}
}
Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n);