Add: simple Application enum.

[proxmark3-svn] / armsrc / lfops.c

diff --git a/armsrc/lfops.c b/armsrc/lfops.c
index a0fa870b62bf7e1e5e4a5dca76682406a8d83f1b..11fc8c50a7864ee1f8a28d442dee66e7ac1a7af3 100644 (file)
--- a/armsrc/lfops.c
+++ b/armsrc/lfops.c
@@ -8,14 +8,16 @@
 // Also routines for raw mode reading/simulating of LF waveform
 //-----------------------------------------------------------------------------
 
 // Also routines for raw mode reading/simulating of LF waveform
 //-----------------------------------------------------------------------------
 

-#include "proxmark3.h"
+#include "../include/proxmark3.h"

 #include "apps.h"
 #include "util.h"
 #include "apps.h"
 #include "util.h"

-#include "hitag2.h"
-#include "crc16.h"
+#include "../include/hitag2.h"
+#include "../common/crc16.h"

 #include "string.h"
 #include "string.h"

+#include "crapto1.h"
+#include "mifareutil.h"

 
 

-void AcquireRawAdcSamples125k(int divisor)
+void LFSetupFPGAForADC(int divisor, bool lf_field)

 {
        FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
        if ( (divisor == 1) || (divisor < 0) || (divisor > 255) )
 {
        FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
        if ( (divisor == 1) || (divisor < 0) || (divisor > 255) )


@@ -25,23 +27,30 @@ void AcquireRawAdcSamples125k(int divisor)
        else
                FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
 
        else
                FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
 

-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | (lf_field ? FPGA_LF_ADC_READER_FIELD : 0));

 
        // Connect the A/D to the peak-detected low-frequency path.
        SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
 
        // Connect the A/D to the peak-detected low-frequency path.
        SetAdcMuxFor(GPIO_MUXSEL_LOPKD);

-

        // Give it a bit of time for the resonant antenna to settle.
        SpinDelay(50);
        // Give it a bit of time for the resonant antenna to settle.
        SpinDelay(50);

-

        // Now set up the SSC to get the ADC samples that are now streaming at us.
        FpgaSetupSsc();
        // Now set up the SSC to get the ADC samples that are now streaming at us.
        FpgaSetupSsc();

+}
+
+void AcquireRawAdcSamples125k(int divisor)
+{
+       LFSetupFPGAForADC(divisor, true);
+       DoAcquisition125k(-1);
+}

 
 

-       // Now call the acquisition routine
-       DoAcquisition125k();
+void SnoopLFRawAdcSamples(int divisor, int trigger_threshold)
+{
+       LFSetupFPGAForADC(divisor, false);
+       DoAcquisition125k(trigger_threshold);

 }
 
 // split into two routines so we can avoid timing issues after sending commands //
 }
 
 // split into two routines so we can avoid timing issues after sending commands //

-void DoAcquisition125k(void)
+void DoAcquisition125k(int trigger_threshold)

 {
        uint8_t *dest = (uint8_t *)BigBuf;
        int n = sizeof(BigBuf);
 {
        uint8_t *dest = (uint8_t *)BigBuf;
        int n = sizeof(BigBuf);


@@ -56,9 +65,12 @@ void DoAcquisition125k(void)
                }
                if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
                        dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
                }
                if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
                        dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;

-                       i++;

                        LED_D_OFF();
                        LED_D_OFF();

-                       if (i >= n) break;
+                       if (trigger_threshold != -1 && dest[i] < trigger_threshold)
+                               continue;
+                       else
+                               trigger_threshold = -1;
+                       if (++i >= n) break;

                }
        }
        Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",
                }
        }
        Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",


@@ -85,7 +97,7 @@ void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1,
        else
                FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
 
        else
                FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
 

-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

 
        // Give it a bit of time for the resonant antenna to settle.
        SpinDelay(50);
 
        // Give it a bit of time for the resonant antenna to settle.
        SpinDelay(50);


@@ -105,7 +117,7 @@ void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1,
                else
                        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
 
                else
                        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
 

-               FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+               FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

                LED_D_ON();
                if(*(command++) == '0')
                        SpinDelayUs(period_0);
                LED_D_ON();
                if(*(command++) == '0')
                        SpinDelayUs(period_0);


@@ -120,10 +132,10 @@ void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1,
        else
                FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
 
        else
                FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
 

-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

 
        // now do the read
 
        // now do the read

-       DoAcquisition125k();
+       DoAcquisition125k(-1);

 }
 
 /* blank r/w tag data stream
 }
 
 /* blank r/w tag data stream


@@ -609,7 +621,7 @@ void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
 
        FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
 
        FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

 
        // Connect the A/D to the peak-detected low-frequency path.
        SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
 
        // Connect the A/D to the peak-detected low-frequency path.
        SetAdcMuxFor(GPIO_MUXSEL_LOPKD);


@@ -823,7 +835,7 @@ void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
 
        FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
 
        FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

 
        // Connect the A/D to the peak-detected low-frequency path.
        SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
 
        // Connect the A/D to the peak-detected low-frequency path.
        SetAdcMuxFor(GPIO_MUXSEL_LOPKD);


@@ -1136,12 +1148,21 @@ void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
 #define WRITE_0   144 // 192
 #define WRITE_1   400 // 432 for T55x7; 448 for E5550
 
 #define WRITE_0   144 // 192
 #define WRITE_1   400 // 432 for T55x7; 448 for E5550
 

+// VALUES TAKEN FROM EM4x function: SendForward
+//  START_GAP = 440; //(55*8)
+//  WRITE_GAP = 128; //(16*8)
+//  WRITE_1 = 256 32*8; //32 cycles at 125Khz (8us each) 1
+//    //These timings work for 4469/4269/4305 (with the 55*8 above)
+//  WRITE_0 = 23*8 , 9*8  SpinDelayUs(23*8); // (8us each) 0
+
+
+

 // Write one bit to card
 void T55xxWriteBit(int bit)
 {
        FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
 // Write one bit to card
 void T55xxWriteBit(int bit)
 {
        FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

        if (bit == 0)
                SpinDelayUs(WRITE_0);
        else
        if (bit == 0)
                SpinDelayUs(WRITE_0);
        else


@@ -1157,7 +1178,7 @@ void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMod
 
        FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
 
        FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

 
        // Give it a bit of time for the resonant antenna to settle.
        // And for the tag to fully power up
 
        // Give it a bit of time for the resonant antenna to settle.
        // And for the tag to fully power up


@@ -1189,7 +1210,7 @@ void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMod
        // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
        // so wait a little more)
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
        // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
        // so wait a little more)
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

        SpinDelay(20);
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 }
        SpinDelay(20);
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 }


@@ -1197,13 +1218,15 @@ void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMod
 // Read one card block in page 0
 void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
 {
 // Read one card block in page 0
 void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
 {

-       uint8_t *dest = (uint8_t *)BigBuf;
-       int m=0, i=0;
+       uint8_t *dest =  mifare_get_bigbufptr();
+       uint16_t bufferlength = 16000;
+       uint32_t i = 0;
+
+       // Clear destination buffer before sending the command  0x80 = average.
+       memset(dest, 0x80, bufferlength);

   
        FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
   
        FpgaDownloadAndGo(FPGA_BITSTREAM_LF);

-       m = sizeof(BigBuf);
-  // Clear destination buffer before sending the command
-       memset(dest, 128, m);
+       

        // Connect the A/D to the peak-detected low-frequency path.
        SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
        // Now set up the SSC to get the ADC samples that are now streaming at us.
        // Connect the A/D to the peak-detected low-frequency path.
        SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
        // Now set up the SSC to get the ADC samples that are now streaming at us.


@@ -1211,7 +1234,7 @@ void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
   
        LED_D_ON();
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
   
        LED_D_ON();
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

   
        // Give it a bit of time for the resonant antenna to settle.
        // And for the tag to fully power up
   
        // Give it a bit of time for the resonant antenna to settle.
        // And for the tag to fully power up


@@ -1237,38 +1260,40 @@ void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
   
   // Turn field on to read the response
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
   
   // Turn field on to read the response
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

   
        // Now do the acquisition
        i = 0;
        for(;;) {
                if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
                        AT91C_BASE_SSC->SSC_THR = 0x43;
   
        // Now do the acquisition
        i = 0;
        for(;;) {
                if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
                        AT91C_BASE_SSC->SSC_THR = 0x43;

+                       LED_D_ON();

                }
                if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
                        dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
                }
                if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
                        dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;

-                       // we don't care about actual value, only if it's more or less than a
-                       // threshold essentially we capture zero crossings for later analysis
-      //                       if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
-                       i++;
-                       if (i >= m) break;
+                       LED_D_OFF();
+                       ++i;
+                       if (i > bufferlength) break;

                }
        }
                }
        }

+ 
+       cmd_send(CMD_ACK,0,0,0,0,0);

   
   FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
        LED_D_OFF();
   
   FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
        LED_D_OFF();

-       DbpString("DONE!");

 }
 
 // Read card traceability data (page 1)
 void T55xxReadTrace(void){
 }
 
 // Read card traceability data (page 1)
 void T55xxReadTrace(void){

-       uint8_t *dest = (uint8_t *)BigBuf;
-       int m=0, i=0;
+       uint8_t *dest =  mifare_get_bigbufptr();
+       uint16_t bufferlength = 16000;
+       int i=0;
+       
+       // Clear destination buffer before sending the command 0x80 = average
+       memset(dest, 0x80, bufferlength);  

   
        FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
   
        FpgaDownloadAndGo(FPGA_BITSTREAM_LF);

-       m = sizeof(BigBuf);
-  // Clear destination buffer before sending the command
-       memset(dest, 128, m);
+               

        // Connect the A/D to the peak-detected low-frequency path.
        SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
        // Now set up the SSC to get the ADC samples that are now streaming at us.
        // Connect the A/D to the peak-detected low-frequency path.
        SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
        // Now set up the SSC to get the ADC samples that are now streaming at us.


@@ -1276,7 +1301,7 @@ void T55xxReadTrace(void){
   
        LED_D_ON();
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
   
        LED_D_ON();
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

   
        // Give it a bit of time for the resonant antenna to settle.
        // And for the tag to fully power up
   
        // Give it a bit of time for the resonant antenna to settle.
        // And for the tag to fully power up


@@ -1292,24 +1317,27 @@ void T55xxReadTrace(void){
   
   // Turn field on to read the response
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
   
   // Turn field on to read the response
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

   
        // Now do the acquisition
        i = 0;
        for(;;) {
                if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
                        AT91C_BASE_SSC->SSC_THR = 0x43;
   
        // Now do the acquisition
        i = 0;
        for(;;) {
                if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
                        AT91C_BASE_SSC->SSC_THR = 0x43;

+                       LED_D_ON();

                }
                if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
                        dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
                }
                if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
                        dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;

-                       i++;
-                       if (i >= m) break;
+                       LED_D_OFF();
+                       ++i;                    
+                       if (i >= bufferlength) break;

                }
        }
   
                }
        }
   

+       cmd_send(CMD_ACK,0,0,0,0,0);
+  

   FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
        LED_D_OFF();
   FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
        LED_D_OFF();

-       DbpString("DONE!");

 }
 
 /*-------------- Cloning routines -----------*/
 }
 
 /*-------------- Cloning routines -----------*/


@@ -1753,7 +1781,6 @@ int IsBlock1PCF7931(uint8_t *Block) {
        
        return 0;
 }
        
        return 0;
 }

-

 #define ALLOC 16
 
 void ReadPCF7931() {
 #define ALLOC 16
 
 void ReadPCF7931() {


@@ -1983,7 +2010,7 @@ void SendForward(uint8_t fwd_bit_count) {
   //Field on
   FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
   FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
   //Field on
   FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
   FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

-  FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+  FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

   
   // Give it a bit of time for the resonant antenna to settle.
   // And for the tag to fully power up
   
   // Give it a bit of time for the resonant antenna to settle.
   // And for the tag to fully power up


@@ -1995,7 +2022,7 @@ void SendForward(uint8_t fwd_bit_count) {
   FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
   SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
   FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
   FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
   SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
   FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

-  FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);//field on
+  FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on

   SpinDelayUs(16*8); //16 cycles on (8us each)
   
   // now start writting
   SpinDelayUs(16*8); //16 cycles on (8us each)
   
   // now start writting


@@ -2007,12 +2034,13 @@ void SendForward(uint8_t fwd_bit_count) {
       FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
       SpinDelayUs(23*8); //16-4 cycles off (8us each)
       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
       FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
       SpinDelayUs(23*8); //16-4 cycles off (8us each)
       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

-      FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);//field on
+      FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on

       SpinDelayUs(9*8); //16 cycles on (8us each)
     }
   }
 }
 
       SpinDelayUs(9*8); //16 cycles on (8us each)
     }
   }
 }
 

+

 void EM4xLogin(uint32_t Password) {
   
   uint8_t fwd_bit_count;
 void EM4xLogin(uint32_t Password) {
   
   uint8_t fwd_bit_count;


@@ -2030,9 +2058,14 @@ void EM4xLogin(uint32_t Password) {
 
 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
   
 
 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
   

+       uint8_t *dest =  mifare_get_bigbufptr();
+       uint16_t bufferlength = 16000;
+       uint32_t i = 0;
+
+       // Clear destination buffer before sending the command  0x80 = average.
+       memset(dest, 0x80, bufferlength);
+       

   uint8_t fwd_bit_count;
   uint8_t fwd_bit_count;

-  uint8_t *dest = (uint8_t *)BigBuf;
-  int m=0, i=0;

   
   //If password mode do login
   if (PwdMode == 1) EM4xLogin(Pwd);
   
   //If password mode do login
   if (PwdMode == 1) EM4xLogin(Pwd);


@@ -2041,9 +2074,6 @@ void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
   fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
   fwd_bit_count += Prepare_Addr( Address );
   
   fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
   fwd_bit_count += Prepare_Addr( Address );
   

-  m = sizeof(BigBuf);
-  // Clear destination buffer before sending the command
-  memset(dest, 128, m);

   // Connect the A/D to the peak-detected low-frequency path.
   SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
   // Now set up the SSC to get the ADC samples that are now streaming at us.
   // Connect the A/D to the peak-detected low-frequency path.
   SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
   // Now set up the SSC to get the ADC samples that are now streaming at us.


@@ -2059,10 +2089,12 @@ void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
     }
     if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
       dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
     }
     if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
       dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;

-      i++;
-      if (i >= m) break;
+               ++i;
+      if (i >= bufferlength) break;

     }
   }
     }
   }

+  
+       cmd_send(CMD_ACK,0,0,0,0,0);

   FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
   LED_D_OFF();
 }
   FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
   LED_D_OFF();
 }