//-----------------------------------------------------------------------------\r
#include <proxmark3.h>\r
#include "apps.h"\r
+#include "hitag2.h"\r
#include "../common/crc16.c"\r
\r
void AcquireRawAdcSamples125k(BOOL at134khz)\r
{\r
BOOL at134khz;\r
\r
+ /* Make sure the tag is reset */\r
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
+ SpinDelay(2500);\r
+ \r
// see if 'h' was specified\r
if(command[strlen((char *) command) - 1] == 'h')\r
at134khz= TRUE;\r
\r
// Give it a bit of time for the resonant antenna to settle.\r
SpinDelay(50);\r
+ // And a little more time for the tag to fully power up\r
+ SpinDelay(2000);\r
\r
// Now set up the SSC to get the ADC samples that are now streaming at us.\r
FpgaSetupSsc();\r
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
}\r
LED_D_ON();\r
- if(*(command++) == '0')\r
+ if(*(command++) == '0') {\r
SpinDelayUs(period_0);\r
- else\r
+ } else {\r
SpinDelayUs(period_1);\r
}\r
+ }\r
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
LED_D_OFF();\r
SpinDelayUs(delay_off);\r
DoAcquisition125k(at134khz);\r
}\r
\r
+/* blank r/w tag data stream\r
+...0000000000000000 01111111\r
+1010101010101010101010101010101010101010101010101010101010101010\r
+0011010010100001\r
+01111111\r
+101010101010101[0]000...\r
+\r
+[5555fe852c5555555555555555fe0000]\r
+*/\r
+void ReadTItag()\r
+{\r
+ // some hardcoded initial params\r
+ // when we read a TI tag we sample the zerocross line at 2Mhz\r
+ // TI tags modulate a 1 as 16 cycles of 123.2Khz\r
+ // TI tags modulate a 0 as 16 cycles of 134.2Khz\r
+ #define FSAMPLE 2000000\r
+ #define FREQLO 123200\r
+ #define FREQHI 134200\r
+\r
+ signed char *dest = (signed char *)BigBuf;\r
+ int n = sizeof(BigBuf);\r
+// int *dest = GraphBuffer;\r
+// int n = GraphTraceLen;\r
+\r
+ // 128 bit shift register [shift3:shift2:shift1:shift0]\r
+ DWORD shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;\r
+\r
+ int i, cycles=0, samples=0;\r
+ // how many sample points fit in 16 cycles of each frequency\r
+ DWORD sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;\r
+ // when to tell if we're close enough to one freq or another\r
+ DWORD threshold = (sampleslo - sampleshi + 1)>>1;\r
+\r
+ // TI tags charge at 134.2Khz\r
+ FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r
+\r
+ // Place FPGA in passthrough mode, in this mode the CROSS_LO line\r
+ // connects to SSP_DIN and the SSP_DOUT logic level controls\r
+ // whether we're modulating the antenna (high)\r
+ // or listening to the antenna (low)\r
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);\r
+\r
+ // get TI tag data into the buffer\r
+ AcquireTiType();\r
+\r
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
+\r
+ for (i=0; i<n-1; i++) {\r
+ // count cycles by looking for lo to hi zero crossings\r
+ if ( (dest[i]<0) && (dest[i+1]>0) ) {\r
+ cycles++;\r
+ // after 16 cycles, measure the frequency\r
+ if (cycles>15) {\r
+ cycles=0;\r
+ samples=i-samples; // number of samples in these 16 cycles\r
+\r
+ // TI bits are coming to us lsb first so shift them\r
+ // right through our 128 bit right shift register\r
+ shift0 = (shift0>>1) | (shift1 << 31);\r
+ shift1 = (shift1>>1) | (shift2 << 31);\r
+ shift2 = (shift2>>1) | (shift3 << 31);\r
+ shift3 >>= 1;\r
+\r
+ // check if the cycles fall close to the number\r
+ // expected for either the low or high frequency\r
+ if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {\r
+ // low frequency represents a 1\r
+ shift3 |= (1<<31);\r
+ } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {\r
+ // high frequency represents a 0\r
+ } else {\r
+ // probably detected a gay waveform or noise\r
+ // use this as gaydar or discard shift register and start again\r
+ shift3 = shift2 = shift1 = shift0 = 0;\r
+ }\r
+ samples = i;\r
+\r
+ // for each bit we receive, test if we've detected a valid tag\r
+\r
+ // if we see 17 zeroes followed by 6 ones, we might have a tag\r
+ // remember the bits are backwards\r
+ if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {\r
+ // if start and end bytes match, we have a tag so break out of the loop\r
+ if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {\r
+ cycles = 0xF0B; //use this as a flag (ugly but whatever)\r
+ break;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ // if flag is set we have a tag\r
+ if (cycles!=0xF0B) {\r
+ DbpString("Info: No valid tag detected.");\r
+ } else {\r
+ // put 64 bit data into shift1 and shift0\r
+ shift0 = (shift0>>24) | (shift1 << 8);\r
+ shift1 = (shift1>>24) | (shift2 << 8);\r
+\r
+ // align 16 bit crc into lower half of shift2\r
+ shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;\r
+\r
+ // if r/w tag, check ident match\r
+ if ( shift3&(1<<15) ) {\r
+ DbpString("Info: TI tag is rewriteable");\r
+ // only 15 bits compare, last bit of ident is not valid\r
+ if ( ((shift3>>16)^shift0)&0x7fff ) {\r
+ DbpString("Error: Ident mismatch!");\r
+ } else {\r
+ DbpString("Info: TI tag ident is valid");\r
+ }\r
+ } else {\r
+ DbpString("Info: TI tag is readonly");\r
+ }\r
+\r
+ // WARNING the order of the bytes in which we calc crc below needs checking\r
+ // i'm 99% sure the crc algorithm is correct, but it may need to eat the\r
+ // bytes in reverse or something\r
+ // calculate CRC\r
+ DWORD crc=0;\r
+\r
+ crc = update_crc16(crc, (shift0)&0xff);\r
+ crc = update_crc16(crc, (shift0>>8)&0xff);\r
+ crc = update_crc16(crc, (shift0>>16)&0xff);\r
+ crc = update_crc16(crc, (shift0>>24)&0xff);\r
+ crc = update_crc16(crc, (shift1)&0xff);\r
+ crc = update_crc16(crc, (shift1>>8)&0xff);\r
+ crc = update_crc16(crc, (shift1>>16)&0xff);\r
+ crc = update_crc16(crc, (shift1>>24)&0xff);\r
+\r
+ DbpString("Info: Tag data_hi, data_lo, crc = ");\r
+ DbpIntegers(shift1, shift0, shift2&0xffff);\r
+ if (crc != (shift2&0xffff)) {\r
+ DbpString("Error: CRC mismatch, expected");\r
+ DbpIntegers(0, 0, crc);\r
+ } else {\r
+ DbpString("Info: CRC is good");\r
+ }\r
+ }\r
+}\r
+\r
+void WriteTIbyte(BYTE b)\r
+{\r
+ int i = 0;\r
+\r
+ // modulate 8 bits out to the antenna\r
+ for (i=0; i<8; i++)\r
+ {\r
+ if (b&(1<<i)) {\r
+ // stop modulating antenna\r
+ PIO_OUTPUT_DATA_CLEAR = (1<<GPIO_SSC_DOUT);\r
+ SpinDelayUs(1000);\r
+ // modulate antenna\r
+ PIO_OUTPUT_DATA_SET = (1<<GPIO_SSC_DOUT);\r
+ SpinDelayUs(1000);\r
+ } else {\r
+ // stop modulating antenna\r
+ PIO_OUTPUT_DATA_CLEAR = (1<<GPIO_SSC_DOUT);\r
+ SpinDelayUs(300);\r
+ // modulate antenna\r
+ PIO_OUTPUT_DATA_SET = (1<<GPIO_SSC_DOUT);\r
+ SpinDelayUs(1700);\r
+ }\r
+ }\r
+}\r
+\r
void AcquireTiType(void)\r
{\r
- int i;\r
+ int i, j, n;\r
// tag transmission is <20ms, sampling at 2M gives us 40K samples max\r
// each sample is 1 bit stuffed into a DWORD so we need 1250 DWORDS\r
- int n = 1250;\r
+ #define TIBUFLEN 1250\r
\r
// clear buffer\r
memset(BigBuf,0,sizeof(BigBuf));\r
for(;;) {\r
if(SSC_STATUS & SSC_STATUS_RX_READY) {\r
BigBuf[i] = SSC_RECEIVE_HOLDING; // store 32 bit values in buffer\r
- i++; if(i >= n) return;\r
+ i++; if(i >= TIBUFLEN) break;\r
}\r
WDT_HIT();\r
}\r
// return stolen pin to SSP\r
PIO_DISABLE = (1<<GPIO_SSC_DOUT);\r
PIO_PERIPHERAL_A_SEL = (1<<GPIO_SSC_DIN) | (1<<GPIO_SSC_DOUT);\r
-}\r
\r
-void ReadTItag()\r
-{\r
-}\r
-\r
-void WriteTIbyte(BYTE b)\r
-{\r
- int i = 0;\r
-\r
- // modulate 8 bits out to the antenna\r
- for (i=0; i<8; i++)\r
- {\r
- if (b&(1<<i)) {\r
- // stop modulating antenna\r
- PIO_OUTPUT_DATA_CLEAR = (1<<GPIO_SSC_DOUT);\r
- SpinDelayUs(1000);\r
- // modulate antenna\r
- PIO_OUTPUT_DATA_SET = (1<<GPIO_SSC_DOUT);\r
- SpinDelayUs(1000);\r
- } else {\r
- // stop modulating antenna\r
- PIO_OUTPUT_DATA_CLEAR = (1<<GPIO_SSC_DOUT);\r
- SpinDelayUs(300);\r
- // modulate antenna\r
- PIO_OUTPUT_DATA_SET = (1<<GPIO_SSC_DOUT);\r
- SpinDelayUs(1700);\r
+ char *dest = (char *)BigBuf;\r
+ n = TIBUFLEN*32;\r
+ // unpack buffer\r
+ for (i=TIBUFLEN-1; i>=0; i--) {\r
+// DbpIntegers(0, 0, BigBuf[i]);\r
+ for (j=0; j<32; j++) {\r
+ if(BigBuf[i] & (1 << j)) {\r
+ dest[--n] = 1;\r
+ } else {\r
+ dest[--n] = -1;\r
+ }\r
}\r
}\r
}\r
\r
-void AcquireRawBitsTI(void)\r
-{\r
- // TI tags charge at 134.2Khz\r
- FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r
-\r
- // Place FPGA in passthrough mode, in this mode the CROSS_LO line\r
- // connects to SSP_DIN and the SSP_DOUT logic level controls\r
- // whether we're modulating the antenna (high)\r
- // or listening to the antenna (low)\r
- FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);\r
-\r
- // get TI tag data into the buffer\r
- AcquireTiType();\r
-\r
- FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
-}\r
-\r
-// this is a dummy function to get around\r
-// a possible flash bug in the bootloader\r
-// delete once you've added more code.\r
-void DummyDummyDummy(void)\r
-{\r
- FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r
- FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);\r
- AcquireTiType();\r
- FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
-}\r
-\r
// arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc\r
// if crc provided, it will be written with the data verbatim (even if bogus)\r
// if not provided a valid crc will be computed from the data and written.\r
AcquireTiType();\r
\r
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
- DbpString("Now use tibits and tidemod");\r
+ DbpString("Now use tiread to check");\r
}\r
\r
void SimulateTagLowFrequency(int period, int ledcontrol)\r
}\r
}\r
\r
+/* Provides a framework for bidirectional LF tag communication\r
+ * Encoding is currently Hitag2, but the general idea can probably\r
+ * be transferred to other encodings.\r
+ * \r
+ * The new FPGA code will, for the LF simulator mode, give on SSC_FRAME\r
+ * (PA15) a thresholded version of the signal from the ADC. Setting the\r
+ * ADC path to the low frequency peak detection signal, will enable a\r
+ * somewhat reasonable receiver for modulation on the carrier signal\r
+ * that is generated by the reader. The signal is low when the reader\r
+ * field is switched off, and high when the reader field is active. Due\r
+ * to the way that the signal looks like, mostly only the rising edge is\r
+ * useful, your mileage may vary.\r
+ * \r
+ * Neat perk: PA15 can not only be used as a bit-banging GPIO, but is also\r
+ * TIOA1, which can be used as the capture input for timer 1. This should\r
+ * make it possible to measure the exact edge-to-edge time, without processor\r
+ * intervention.\r
+ * \r
+ * Arguments: divisor is the divisor to be sent to the FPGA (e.g. 95 for 125kHz)\r
+ * t0 is the carrier frequency cycle duration in terms of MCK (384 for 125kHz)\r
+ * \r
+ * The following defines are in carrier periods: \r
+ */\r
+#define HITAG_T_0_MIN 15 /* T[0] should be 18..22 */ \r
+#define HITAG_T_1_MIN 24 /* T[1] should be 26..30 */\r
+#define HITAG_T_EOF 40 /* T_EOF should be > 36 */\r
+#define HITAG_T_WRESP 208 /* T_wresp should be 204..212 */\r
+\r
+static void hitag_handle_frame(int t0, int frame_len, char *frame);\r
+//#define DEBUG_RA_VALUES 1\r
+#define DEBUG_FRAME_CONTENTS 1\r
+void SimulateTagLowFrequencyBidir(int divisor, int t0)\r
+{\r
+#if DEBUG_RA_VALUES || DEBUG_FRAME_CONTENTS\r
+ int i = 0;\r
+#endif\r
+ char frame[10];\r
+ int frame_pos=0;\r
+ \r
+ DbpString("Starting Hitag2 emulator, press button to end");\r
+ hitag2_init();\r
+ \r
+ /* Set up simulator mode, frequency divisor which will drive the FPGA\r
+ * and analog mux selection.
+ */\r
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_SIMULATOR);\r
+ FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);\r
+ SetAdcMuxFor(GPIO_MUXSEL_LOPKD);\r
+ RELAY_OFF();\r
+ \r
+ /* Set up Timer 1:\r
+ * Capture mode, timer source MCK/2 (TIMER_CLOCK1), TIOA is external trigger,\r
+ * external trigger rising edge, load RA on rising edge of TIOA, load RB on rising\r
+ * edge of TIOA. Assign PA15 to TIOA1 (peripheral B)
+ */\r
+ \r
+ PMC_PERIPHERAL_CLK_ENABLE = (1 << PERIPH_TC1);\r
+ PIO_PERIPHERAL_B_SEL = (1 << GPIO_SSC_FRAME);\r
+ TC1_CCR = TC_CCR_CLKDIS;\r
+ TC1_CMR = TC_CMR_TCCLKS_TIMER_CLOCK1 | TC_CMR_ETRGEDG_RISING | TC_CMR_ABETRG |\r
+ TC_CMR_LDRA_RISING | TC_CMR_LDRB_RISING;\r
+ TC1_CCR = TC_CCR_CLKEN | TC_CCR_SWTRG;\r
+ \r
+ /* calculate the new value for the carrier period in terms of TC1 values */\r
+ t0 = t0/2;\r
+ \r
+ int overflow = 0;\r
+ while(!BUTTON_PRESS()) {\r
+ WDT_HIT();\r
+ if(TC1_SR & TC_SR_LDRAS) {\r
+ int ra = TC1_RA;\r
+ if((ra > t0*HITAG_T_EOF) | overflow) ra = t0*HITAG_T_EOF+1;\r
+#if DEBUG_RA_VALUES\r
+ if(ra > 255 || overflow) ra = 255;\r
+ ((char*)BigBuf)[i] = ra;\r
+ i = (i+1) % 8000;\r
+#endif\r
+ \r
+ if(overflow || (ra > t0*HITAG_T_EOF) || (ra < t0*HITAG_T_0_MIN)) {\r
+ /* Ignore */\r
+ } else if(ra >= t0*HITAG_T_1_MIN ) {\r
+ /* '1' bit */\r
+ if(frame_pos < 8*sizeof(frame)) {\r
+ frame[frame_pos / 8] |= 1<<( 7-(frame_pos%8) );\r
+ frame_pos++;\r
+ }\r
+ } else if(ra >= t0*HITAG_T_0_MIN) {\r
+ /* '0' bit */\r
+ if(frame_pos < 8*sizeof(frame)) {\r
+ frame[frame_pos / 8] |= 0<<( 7-(frame_pos%8) );\r
+ frame_pos++;\r
+ }\r
+ }\r
+ \r
+ overflow = 0;\r
+ LED_D_ON();\r
+ } else {\r
+ if(TC1_CV > t0*HITAG_T_EOF) {\r
+ /* Minor nuisance: In Capture mode, the timer can not be\r
+ * stopped by a Compare C. There's no way to stop the clock\r
+ * in software, so we'll just have to note the fact that an\r
+ * overflow happened and the next loaded timer value might\r
+ * have wrapped. Also, this marks the end of frame, and the\r
+ * still running counter can be used to determine the correct\r
+ * time for the start of the reply.
+ */ \r
+ overflow = 1;\r
+ \r
+ if(frame_pos > 0) {\r
+ /* Have a frame, do something with it */\r
+#if DEBUG_FRAME_CONTENTS\r
+ ((char*)BigBuf)[i++] = frame_pos;\r
+ memcpy( ((char*)BigBuf)+i, frame, 7);\r
+ i+=7;\r
+ i = i % sizeof(BigBuf);\r
+#endif\r
+ hitag_handle_frame(t0, frame_pos, frame);\r
+ memset(frame, 0, sizeof(frame));\r
+ }\r
+ frame_pos = 0;\r
+\r
+ }\r
+ LED_D_OFF();\r
+ }\r
+ }\r
+ DbpString("All done");\r
+}\r
+\r
+static void hitag_send_bit(int t0, int bit) {\r
+ if(bit == 1) {\r
+ /* Manchester: Loaded, then unloaded */\r
+ LED_A_ON();\r
+ SHORT_COIL();\r
+ while(TC1_CV < t0*15);\r
+ OPEN_COIL();\r
+ while(TC1_CV < t0*31);\r
+ LED_A_OFF();\r
+ } else if(bit == 0) {\r
+ /* Manchester: Unloaded, then loaded */\r
+ LED_B_ON();\r
+ OPEN_COIL();\r
+ while(TC1_CV < t0*15);\r
+ SHORT_COIL();\r
+ while(TC1_CV < t0*31);\r
+ LED_B_OFF();\r
+ }\r
+ TC1_CCR = TC_CCR_SWTRG; /* Reset clock for the next bit */\r
+ \r
+}\r
+static void hitag_send_frame(int t0, int frame_len, const char const * frame, int fdt)\r
+{\r
+ OPEN_COIL();\r
+ PIO_OUTPUT_ENABLE = (1 << GPIO_SSC_DOUT);\r
+ \r
+ /* Wait for HITAG_T_WRESP carrier periods after the last reader bit,\r
+ * not that since the clock counts since the rising edge, but T_wresp is\r
+ * with respect to the falling edge, we need to wait actually (T_wresp - T_g)\r
+ * periods. The gap time T_g varies (4..10).
+ */\r
+ while(TC1_CV < t0*(fdt-8));\r
+\r
+ int saved_cmr = TC1_CMR;\r
+ TC1_CMR &= ~TC_CMR_ETRGEDG; /* Disable external trigger for the clock */\r
+ TC1_CCR = TC_CCR_SWTRG; /* Reset the clock and use it for response timing */\r
+ \r
+ int i;\r
+ for(i=0; i<5; i++)\r
+ hitag_send_bit(t0, 1); /* Start of frame */\r
+ \r
+ for(i=0; i<frame_len; i++) {\r
+ hitag_send_bit(t0, !!(frame[i/ 8] & (1<<( 7-(i%8) ))) );\r
+ }\r
+ \r
+ OPEN_COIL();\r
+ TC1_CMR = saved_cmr;\r
+}\r
+\r
+/* Callback structure to cleanly separate tag emulation code from the radio layer. */\r
+static int hitag_cb(const char* response_data, const int response_length, const int fdt, void *cb_cookie)\r
+{\r
+ hitag_send_frame(*(int*)cb_cookie, response_length, response_data, fdt);\r
+ return 0;\r
+}\r
+/* Frame length in bits, frame contents in MSBit first format */\r
+static void hitag_handle_frame(int t0, int frame_len, char *frame)\r
+{\r
+ hitag2_handle_command(frame, frame_len, hitag_cb, &t0);\r
+}\r
+\r
// compose fc/8 fc/10 waveform\r
static void fc(int c, int *n) {\r
BYTE *dest = (BYTE *)BigBuf;\r
projects / proxmark3-svn / blobdiff