FIX: hf mf eload - now supports specifying 0,1,2,4 in card memory for the file to...

[proxmark3-svn] / armsrc / lfops.c

diff --git a/armsrc/lfops.c b/armsrc/lfops.c
index c80caf776b323d600453b62c557c5f4e4d90778f..1a7c32245411ff560f937323caf9b93ace96d217 100644 (file)
--- a/armsrc/lfops.c
+++ b/armsrc/lfops.c
@@ -452,25 +452,34 @@ void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
 {
        int i = 0;
 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
 {
        int i = 0;

-       uint8_t *buff = (uint8_t *)BigBuf;
+       uint8_t *buf = (uint8_t *)BigBuf;

 
        FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
 
        FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
-       SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
-
+       //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
+       
+       // Connect the A/D to the peak-detected low-frequency path.
+       //SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
+               

        // Configure output and enable pin that is connected to the FPGA (for modulating)
        AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;    
        // Configure output and enable pin that is connected to the FPGA (for modulating)
        AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;    

-       AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
-       
-       AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
+       AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;    // (PIO_PER) PIO Enable Register , 
+       AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;    // (PIO_OER) Output Enable Register
+       AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;     // (PIO_ODR) Output Disable Register

 
        // Give it a bit of time for the resonant antenna to settle.
 
        // Give it a bit of time for the resonant antenna to settle.

-       SpinDelay(30);
+       SpinDelay(150);
+       
+       while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)); // wait for ssp_clk to go high
+       while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK);    // wait for ssp_clk to go low
+       
+       while(!BUTTON_PRESS()) { 
+               WDT_HIT();

 
 

-       for(;;) { 
-               
-               while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
+               // PIO_PDSR = Pin Data Status Register  
+               // GPIO_SSC_CLK  = SSC Transmit Clock
+               while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {    // wait for ssp_clk to go high

                         if(BUTTON_PRESS()) {
                                 DbpString("Stopped at 0");
                                 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
                         if(BUTTON_PRESS()) {
                                 DbpString("Stopped at 0");
                                 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off


@@ -479,12 +488,21 @@ void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
                         WDT_HIT();
                }
         
                         WDT_HIT();
                }
         

-               if ( buff[i] )
-                       OPEN_COIL();
-               else
-                       SHORT_COIL();
-       
-                while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
+               // PIO_CODR = Clear Output Data Register
+               // PIO_SODR = Set Output Data Register
+               //#define LOW(x)         AT91C_BASE_PIOA->PIO_CODR = (x)
+               //#define HIGH(x)        AT91C_BASE_PIOA->PIO_SODR = (x)
+               
+               if ( buf[i] > 0 ){
+                       HIGH(GPIO_SSC_DOUT);
+                       //FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
+                       //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
+               } else {
+                       LOW(GPIO_SSC_DOUT);
+                       //FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); 
+               }
+          
+                while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {   // wait for ssp_clk to go low

                         if(BUTTON_PRESS()) {
                                DbpString("Stopped at 1");
                                FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
                         if(BUTTON_PRESS()) {
                                DbpString("Stopped at 1");
                                FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off


@@ -492,18 +510,23 @@ void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
                        }
                        WDT_HIT();
                 }
                        }
                        WDT_HIT();
                 }

-        
+               
+               //SpinDelayUs(512);
+               

                ++i;
                if(i == period) {
                        i = 0;
                        if (gap) {
                                // turn of modulation
                ++i;
                if(i == period) {
                        i = 0;
                        if (gap) {
                                // turn of modulation

-                               SHORT_COIL();
+                               LOW(GPIO_SSC_DOUT);

                                // wait
                                SpinDelay(gap);
                        } 
                }
        }
                                // wait
                                SpinDelay(gap);
                        } 
                }
        }

+       DbpString("Stopped");
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+       return;

 }
 
 #define DEBUG_FRAME_CONTENTS 1
 }
 
 #define DEBUG_FRAME_CONTENTS 1