#include "apps.h"
#include "util.h"
#include "string.h"
-
#include "iso14443crc.h"
+#include "common.h"
+#define RECEIVE_SAMPLES_TIMEOUT 600000
+#define ISO14443B_DMA_BUFFER_SIZE 256
+
-#define RECEIVE_SAMPLES_TIMEOUT 200000
-#define ISO14443B_DMA_BUFFER_SIZE 512
+// PCB Block number for APDUs
+static uint8_t pcb_blocknum = 0;
-uint8_t PowerOn = TRUE;
//=============================================================================
// An ISO 14443 Type B tag. We listen for commands from the reader, using
// a UART kind of thing that's implemented in software. When we get a
Uart.state = STATE_UNSYNCD;
Uart.byteCnt = 0;
Uart.bitCnt = 0;
+ Uart.posCnt = 0;
memset(Uart.output, 0x00, MAX_FRAME_SIZE);
}
if (tracing) LogTrace(resp, respLen, 0, 0, parity, FALSE);
}
FpgaDisableSscDma();
+ set_tracing(FALSE);
}
//=============================================================================
* false if we are still waiting for some more
*
*/
+ #define abs(x) ( ((x)<0) ? -(x) : (x) )
static RAMFUNC int Handle14443bSamplesDemod(int ci, int cq)
{
- int v;
+ int v = 0;
+ int ai = abs(ci);
+ int aq = abs(cq);
+ int halfci = (ai >> 1);
+ int halfcq = (aq >> 1);
// The soft decision on the bit uses an estimate of just the
// quadrant of the reference angle, not the exact angle.
#define SUBCARRIER_DETECT_THRESHOLD 8
-// Subcarrier amplitude v = sqrt(ci^2 + cq^2), approximated here by abs(ci) + abs(cq)
-/* #define CHECK_FOR_SUBCARRIER() { \
- v = ci; \
- if(v < 0) v = -v; \
- if(cq > 0) { \
- v += cq; \
- } else { \
- v -= cq; \
- } \
- }
- */
// Subcarrier amplitude v = sqrt(ci^2 + cq^2), approximated here by max(abs(ci),abs(cq)) + 1/2*min(abs(ci),abs(cq)))
#define CHECK_FOR_SUBCARRIER() { \
- if(ci < 0) { \
- if(cq < 0) { /* ci < 0, cq < 0 */ \
- if (cq < ci) { \
- v = -cq - (ci >> 1); \
- } else { \
- v = -ci - (cq >> 1); \
- } \
- } else { /* ci < 0, cq >= 0 */ \
- if (cq < -ci) { \
- v = -ci + (cq >> 1); \
- } else { \
- v = cq - (ci >> 1); \
- } \
- } \
- } else { \
- if(cq < 0) { /* ci >= 0, cq < 0 */ \
- if (-cq < ci) { \
- v = ci - (cq >> 1); \
- } else { \
- v = -cq + (ci >> 1); \
- } \
- } else { /* ci >= 0, cq >= 0 */ \
- if (cq < ci) { \
- v = ci + (cq >> 1); \
- } else { \
- v = cq + (ci >> 1); \
- } \
- } \
- } \
- }
-
+ v = MAX(ai, aq) + MIN(halfci, halfcq); \
+}
+
+
switch(Demod.state) {
case DEMOD_UNSYNCD:
CHECK_FOR_SUBCARRIER();
break;
case DEMOD_PHASE_REF_TRAINING:
- if(Demod.posCount < 10*2) {
+ if(Demod.posCount < 8) {
+ //if(Demod.posCount < 10*2) {
CHECK_FOR_SUBCARRIER();
if (v > SUBCARRIER_DETECT_THRESHOLD) {
// set the reference phase (will code a logic '1') by averaging over 32 1/fs.
case DEMOD_AWAITING_FALLING_EDGE_OF_SOF:
MAKE_SOFT_DECISION();
- if(v < 0) { // logic '0' detected
+ //Dbprintf("ICE: %d %d %d %d %d", v, Demod.sumI, Demod.sumQ, ci, cq );
+ if(v <= 0) { // logic '0' detected
Demod.state = DEMOD_GOT_FALLING_EDGE_OF_SOF;
Demod.posCount = 0; // start of SOF sequence
} else {
- //if(Demod.posCount > 200/4) { // maximum length of TR1 = 200 1/fs
if(Demod.posCount > 25*2) { // maximum length of TR1 = 200 1/fs
Demod.state = DEMOD_UNSYNCD;
}
if(Demod.posCount < 10*2) { // low phase of SOF too short (< 9 etu). Note: spec is >= 10, but FPGA tends to "smear" edges
Demod.state = DEMOD_UNSYNCD;
} else {
+ LED_C_ON(); // Got SOF
Demod.state = DEMOD_AWAITING_START_BIT;
Demod.posCount = 0;
Demod.len = 0;
Demod.bitCount++;
if(Demod.bitCount == 10) {
- LED_C_ON();
uint16_t s = Demod.shiftReg;
if((s & 0x200) && !(s & 0x001)) { // stop bit == '1', start bit == '0'
uint8_t b = (s >> 1);
Demod.len = 0;
Demod.state = DEMOD_UNSYNCD;
Demod.posCount = 0;
+ Demod.sumI = 0;
+ Demod.sumQ = 0;
+ Demod.bitCount = 0;
+ Demod.thisBit = 0;
+ Demod.shiftReg = 0;
memset(Demod.output, 0x00, MAX_FRAME_SIZE);
}
FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ);
// The response (tag -> reader) that we're receiving.
- uint8_t *resp = BigBuf_malloc(MAX_FRAME_SIZE);
-
// Set up the demodulator for tag -> reader responses.
- DemodInit(resp);
+ DemodInit(BigBuf_malloc(MAX_FRAME_SIZE));
// The DMA buffer, used to stream samples from the FPGA
int8_t *dmaBuf = (int8_t*) BigBuf_malloc(ISO14443B_DMA_BUFFER_SIZE);
-
+ // Setup and start DMA.
+ FpgaSetupSscDma((uint8_t*) dmaBuf, ISO14443B_DMA_BUFFER_SIZE);
+
int8_t *upTo = dmaBuf;
lastRxCounter = ISO14443B_DMA_BUFFER_SIZE;
// Signal field is ON with the appropriate LED:
LED_D_ON();
-
- // Setup and start DMA.
- FpgaSetupSscDma((uint8_t*) dmaBuf, ISO14443B_DMA_BUFFER_SIZE);
-
-
for(;;) {
int behindBy = lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR;
if(behindBy > max) max = behindBy;
}
lastRxCounter -= 2;
if(lastRxCounter <= 0) {
- lastRxCounter += ISO14443B_DMA_BUFFER_SIZE;
+ lastRxCounter = ISO14443B_DMA_BUFFER_SIZE;
}
samples += 2;
- if(Handle14443bSamplesDemod(ci, cq)) {
- gotFrame = TRUE;
+ //
+ gotFrame = Handle14443bSamplesDemod(ci , cq );
+ if ( gotFrame )
break;
}
- }
if(samples > n || gotFrame) {
break;
AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;
- if (!quiet) {
+ if (!quiet && Demod.len == 0) {
Dbprintf("max behindby = %d, samples = %d, gotFrame = %d, Demod.len = %d, Demod.sumI = %d, Demod.sumQ = %d",
max,
samples,
int c;
FpgaSetupSsc();
-
+
while(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
AT91C_BASE_SSC->SSC_THR = 0xff;
}
// Signal we are transmitting with the Green LED
LED_B_ON();
FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
- if ( !PowerOn )
- SpinDelay(200);
for(c = 0; c < 10;) {
if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
ToSendReset();
// Establish initial reference level
- for(i = 0; i < 80; i++) {
+ for(i = 0; i < 40; i++) {
ToSendStuffBit(1);
}
// Send SOF
}
}
+/* Sends an APDU to the tag
+ * TODO: check CRC and preamble
+ */
+int iso14443b_apdu(uint8_t const *message, size_t message_length, uint8_t *response)
+{
+ uint8_t message_frame[message_length + 4];
+ // PCB
+ message_frame[0] = 0x0A | pcb_blocknum;
+ pcb_blocknum ^= 1;
+ // CID
+ message_frame[1] = 0;
+ // INF
+ memcpy(message_frame + 2, message, message_length);
+ // EDC (CRC)
+ ComputeCrc14443(CRC_14443_B, message_frame, message_length + 2, &message_frame[message_length + 2], &message_frame[message_length + 3]);
+ // send
+ CodeAndTransmit14443bAsReader(message_frame, message_length + 4);
+ // get response
+ GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT*100, TRUE);
+ if(Demod.len < 3)
+ {
+ return 0;
+ }
+ // TODO: Check CRC
+ // copy response contents
+ if(response != NULL)
+ {
+ memcpy(response, Demod.output, Demod.len);
+ }
+ return Demod.len;
+}
+
+/* Perform the ISO 14443 B Card Selection procedure
+ * Currently does NOT do any collision handling.
+ * It expects 0-1 cards in the device's range.
+ * TODO: Support multiple cards (perform anticollision)
+ * TODO: Verify CRC checksums
+ */
+int iso14443b_select_card()
+{
+ // WUPB command (including CRC)
+ // Note: WUPB wakes up all tags, REQB doesn't wake up tags in HALT state
+ static const uint8_t wupb[] = { 0x05, 0x00, 0x08, 0x39, 0x73 };
+ // ATTRIB command (with space for CRC)
+ uint8_t attrib[] = { 0x1D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00};
+
+ // first, wake up the tag
+ CodeAndTransmit14443bAsReader(wupb, sizeof(wupb));
+ GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
+ // ATQB too short?
+ if (Demod.len < 14)
+ {
+ return 2;
+ }
+
+ // select the tag
+ // copy the PUPI to ATTRIB
+ memcpy(attrib + 1, Demod.output + 1, 4);
+ /* copy the protocol info from ATQB (Protocol Info -> Protocol_Type) into
+ ATTRIB (Param 3) */
+ attrib[7] = Demod.output[10] & 0x0F;
+ ComputeCrc14443(CRC_14443_B, attrib, 9, attrib + 9, attrib + 10);
+ CodeAndTransmit14443bAsReader(attrib, sizeof(attrib));
+ GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
+ // Answer to ATTRIB too short?
+ if(Demod.len < 3)
+ {
+ return 2;
+ }
+ // reset PCB block number
+ pcb_blocknum = 0;
+ return 1;
+}
+
+// Set up ISO 14443 Type B communication (similar to iso14443a_setup)
+void iso14443b_setup() {
+
+ FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
+
+ BigBuf_free();
+ // Set up the synchronous serial port
+ FpgaSetupSsc();
+ // connect Demodulated Signal to ADC:
+ SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
+
+ // Signal field is on with the appropriate LED
+ LED_D_ON();
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
+
+ //SpinDelay(100);
+
+ // Start the timer
+ //StartCountSspClk();
+
+ DemodReset();
+ UartReset();
+}
//-----------------------------------------------------------------------------
// Read a SRI512 ISO 14443B tag.
if (Demod.len == 0) {
DbpString("No response from tag");
+ set_tracing(FALSE);
return;
} else {
Dbprintf("Randomly generated Chip ID (+ 2 byte CRC): %02x %02x %02x",
GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
if (Demod.len != 3) {
Dbprintf("Expected 3 bytes from tag, got %d", Demod.len);
+ set_tracing(FALSE);
return;
}
// Check the CRC of the answer:
ComputeCrc14443(CRC_14443_B, Demod.output, 1 , &cmd1[2], &cmd1[3]);
if(cmd1[2] != Demod.output[1] || cmd1[3] != Demod.output[2]) {
DbpString("CRC Error reading select response.");
+ set_tracing(FALSE);
return;
}
// Check response from the tag: should be the same UID as the command we just sent:
if (cmd1[1] != Demod.output[0]) {
Dbprintf("Bad response to SELECT from Tag, aborting: %02x %02x", cmd1[1], Demod.output[0]);
+ set_tracing(FALSE);
return;
}
GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
if (Demod.len != 10) {
Dbprintf("Expected 10 bytes from tag, got %d", Demod.len);
+ set_tracing(FALSE);
return;
}
// The check the CRC of the answer (use cmd1 as temporary variable):
}
i++;
}
+
+ set_tracing(FALSE);
}
}
if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
- if(Handle14443bSamplesDemod(ci | 0x01, cq | 0x01)) {
+ // is this | 0x01 the error? & 0xfe in https://github.com/Proxmark/proxmark3/issues/103
+ if(Handle14443bSamplesDemod(ci & 0xfe, cq & 0xfe)) {
//Use samples as a time measurement
if(tracing)
}
TagIsActive = (Demod.state > DEMOD_GOT_FALLING_EDGE_OF_SOF);
}
-
}
FpgaDisableSscDma();
LEDsoff();
+ set_tracing(FALSE);
+
AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;
DbpString("Snoop statistics:");
Dbprintf(" Max behind by: %i", maxBehindBy);
*/
void SendRawCommand14443B(uint32_t datalen, uint32_t recv, uint8_t powerfield, uint8_t data[])
{
- FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
- BigBuf_free();
- SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
- if ( !PowerOn ){
- FpgaSetupSsc();
- }
+ iso14443b_setup();
if ( datalen == 0 && recv == 0 && powerfield == 0){
- clear_trace();
- } else {
+
+ } else {
set_tracing(TRUE);
CodeAndTransmit14443bAsReader(data, datalen);
}
if(!powerfield) {
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
FpgaDisableSscDma();
+ set_tracing(FALSE);
LED_D_OFF();
- PowerOn = 0;
}
}
projects / proxmark3-svn / blobdiff